steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-14 09:00:40 +02:00
Code Issues Packages Projects Releases 67 Wiki Activity

Arm64/VectorOps: Handle 64-bit elements in VSShr

Browse Source 
Makes it consistent with all of the other variable shift IR ops.

Now this won't explode if we ever implement VPSRAVQ from AVX-512
This commit is contained in:
Lioncache committed 2023-03-21 22:23:12 -04:00
1 parent 54e784742c
commit 91d6dc0528
1 file changed
+10 -3
Download Patch File Download Diff File Expand all files Collapse all files
External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
Vendored
+10 -3
View File
@@ -2198,10 +2198,17 @@ DEF_OP(VSShr) {
movprfx(Dst.Z(), Vector.Z());
asr(SubRegSize, Dst.Z(), Mask, Dst.Z(), VTMP1.Z());
} else {
LOGMAN_THROW_AA_FMT(ElementSize != 8, "Adv. SIMD UMIN doesn't handle 64-bit values");
if (ElementSize < 8) {
movi(SubRegSize, VTMP1.Q(), MaxShift);
umin(SubRegSize, VTMP1.Q(), VTMP1.Q(), ShiftVector.Q());
} else {
LoadConstant(ARMEmitter::Size::i64Bit, TMP1, MaxShift);
dup(SubRegSize, VTMP1.Q(), TMP1.R());
movi(SubRegSize, VTMP1.Q(), MaxShift);
umin(SubRegSize, VTMP1.Q(), VTMP1.Q(), ShiftVector.Q());
// UMIN is silly on Adv.SIMD and doesn't have a variant that handles 64-bit elements
cmhi(SubRegSize, VTMP2.Q(), ShiftVector.Q(), VTMP1.Q());
bif(VTMP1.Q(), ShiftVector.Q(), VTMP2.Q());
}
// Need to invert shift values to perform a right shift with SSHL
// (SSHR only has an immediate variant).