From 91d6dc05282a3c1a53e6e0dfd8842be3fc02bfcb Mon Sep 17 00:00:00 2001 From: Lioncache Date: Tue, 21 Mar 2023 22:23:10 -0400 Subject: [PATCH] Arm64/VectorOps: Handle 64-bit elements in VSShr Makes it consistent with all of the other variable shift IR ops. Now this won't explode if we ever implement VPSRAVQ from AVX-512 --- .../Source/Interface/Core/JIT/Arm64/VectorOps.cpp | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp index 04e0ed2cc..864af3464 100644 --- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp +++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp @@ -2198,10 +2198,17 @@ DEF_OP(VSShr) { movprfx(Dst.Z(), Vector.Z()); asr(SubRegSize, Dst.Z(), Mask, Dst.Z(), VTMP1.Z()); } else { - LOGMAN_THROW_AA_FMT(ElementSize != 8, "Adv. SIMD UMIN doesn't handle 64-bit values"); + if (ElementSize < 8) { + movi(SubRegSize, VTMP1.Q(), MaxShift); + umin(SubRegSize, VTMP1.Q(), VTMP1.Q(), ShiftVector.Q()); + } else { + LoadConstant(ARMEmitter::Size::i64Bit, TMP1, MaxShift); + dup(SubRegSize, VTMP1.Q(), TMP1.R()); - movi(SubRegSize, VTMP1.Q(), MaxShift); - umin(SubRegSize, VTMP1.Q(), VTMP1.Q(), ShiftVector.Q()); + // UMIN is silly on Adv.SIMD and doesn't have a variant that handles 64-bit elements + cmhi(SubRegSize, VTMP2.Q(), ShiftVector.Q(), VTMP1.Q()); + bif(VTMP1.Q(), ShiftVector.Q(), VTMP2.Q()); + } // Need to invert shift values to perform a right shift with SSHL // (SSHR only has an immediate variant).