Ryan Houdek
d06e98ed84
InstcountCI: Update
2026-09-15 16:40:55 -07:00
Pierre-Loup A. Griffais
ae84606da2
InstcountCI: Update
2026-09-14 22:31:16 -07:00
Pierre-Loup A. Griffais
c18deb0d0f
InstcountCI: Update
2026-09-13 17:41:53 -07:00
Ryan Houdek
82e014cf5c
InstcountCI: Add big moffset instructions
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Found out these weren't testing 64-bit immediates, so make sure it is.
2026-09-12 18:11:15 -07:00
Justin Becker
480308c021
Bump DiskCache version
2026-09-10 15:59:52 -07:00
Justin Becker
89a13cd5fd
AVX-VNNI
2026-09-10 15:56:03 -07:00
Ryan Houdek
200f59ab70
InstcountCI: Update
2026-09-10 09:53:54 -07:00
Pierre-Loup A. Griffais
cc5686de37
InstcountCI: Update
2026-09-07 22:51:31 -07:00
Pierre-Loup A. Griffais
ffaa5d6316
InstcountCI: Update
2026-09-07 00:56:39 -07:00
Pierre-Loup A. Griffais
983c5defc1
InstcountCI: Update
2026-09-06 23:25:53 -07:00
Pierre-Loup A. Griffais
4a065ad1a2
InstcountCI: Update
2026-09-05 21:58:07 -07:00
Simon Scherer
c5700cb0cc
InstcountCI: Update
2026-09-04 17:03:46 +02:00
Simon Scherer
040d3115d2
InstcountCI: Update
2026-09-04 11:53:13 +02:00
Simon Scherer
96d65cd6bc
InstcountCI: Update
2026-09-04 08:30:03 +02:00
Simon Scherer
fd64ea54fe
InstcountCI: Update
2026-09-04 07:32:09 +02:00
Simon Scherer
30e4650a8b
InstcountCI: Update
2026-09-03 08:32:59 +02:00
Ryan Houdek
fbf5187794
InstcountCI: Update
2026-09-02 18:35:36 -07:00
Ryan Houdek
20e9e2044e
InstcountCI: Update
2026-09-02 17:15:36 -07:00
Justin Becker
3471ca67c4
Bump DiskCache version number
2026-09-02 16:40:17 -07:00
jubecker
61d94ac117
Potential improvement for *PMULHRSW
2026-09-02 14:31:18 -07:00
Simon Scherer
bce8b13366
InstcountCI: Update
2026-09-02 07:47:24 +02:00
Pierre-Loup A. Griffais
c01bfcd52f
InstcountCI: Update
2026-09-01 03:51:12 -07:00
Ryan Houdek
1558a2c65d
InstcountCI: Update
2026-08-31 19:23:20 -07:00
Pierre-Loup A. Griffais
0d3a5f96f0
InstcountCI: Update
2026-08-30 17:17:54 -07:00
Ryan Houdek
b695c5ae11
InstCountCI: Update
...
Only adds DiskCache version to json to ensure it's tracked. No asm
changes here.
2026-08-30 14:26:45 -07:00
LC
62c9c130c4
Merge pull request #5864 from simon902/pf2id_saturation
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Fix pf2id overflow saturation
2026-08-27 09:16:04 -04:00
LC
fca23d88c3
Merge pull request #5863 from simon902/vfaddp-mmx-width
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Fix PFACC producing wrong results due to missing MMX-sized path in VFAddP
2026-08-27 09:15:30 -04:00
Simon Scherer
fe17c447d9
InstcountCI: Update
2026-08-27 11:50:52 +02:00
Simon Scherer
79ef5031eb
InstcountCI: Update
2026-08-27 10:36:31 +02:00
Simon Scherer
e6748ea1ed
InstcountCI: Update
2026-08-27 09:36:28 +02:00
Ryan Houdek
485f1c6acf
InstcountCI: Update
2026-08-25 15:18:17 -07:00
Ryan Houdek
2a76d3b153
Merge pull request #5809 from simon902/fcomi_flag_zero
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FCOMI fails to clear OF, SF, AF
2026-08-25 13:22:28 -07:00
Paris Oplopoios
635befb4c8
FEXCore: Fix CF calculation for BLSMSK and BLSR for 32-bit operands
2026-08-22 15:47:50 +03:00
Ryan Houdek
a3d609ebb1
Merge pull request #5820 from javelina-pkwy/lea-reg-reg
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Decoder: fix illegal LEA encoding
2026-08-17 09:58:47 -07:00
Justin Becker
c156498c5c
Add 16 bit and 32 bit variants
2026-08-11 16:19:49 -07:00
Simon Scherer
6284c39eb3
InstcountCI: Update
2026-08-06 16:31:49 +02:00
Justin Becker
34a87cc94c
Decoder: fix illegal LEA encoding
2026-07-27 15:48:35 -07:00
Ryan Houdek
f73b93dbc2
InstcountCI: Update
2026-07-17 13:17:39 -07:00
moonfloww
7189e1e280
InstcountCI: Update
2026-07-16 14:44:04 +02:00
LC
ba8b0afe7a
VectorOps: Use unpredicated shifts where applicable for 256-bit scalar shifts
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Lets us trim some output
2026-07-15 09:10:57 -04:00
LC
98d45a6a9b
VectorOps: Make use of unpredicated immediate shifts
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Same behavior, just without introducing a predicate register dependency.
2026-07-15 08:00:58 -04:00
LC
842e22915c
VectorOps: Simplify SVE 256-bit VOrn with BSL2N
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Lets us shave off an instruction and also avoid using a temporary
register in some cases. We can also tweak our worst case that requires a
predicate to eliminate the temporary as well.
We can also expand our cmpps cases, so that we can reflect the
BSL2N usages in instcountci.
2026-07-13 12:27:54 -04:00
LC
9d3c388664
Crypto: Make use of XAR in SHA1NEXTE when available
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Lets us shave an instruction off on hardware that supports XAR.
Closes #5730
2026-07-12 16:02:12 -04:00
LC
613e9ef701
MiscOps: Fix round mode clearing for RP/RM modes in PushRoundingMode
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Previously this had the potential to not clear rounding bits properly
depending on incoming FPCR state.
2026-07-11 10:24:07 -04:00
LC
b5660c8a92
MiscOps: Avoid stack misalignment in ProcessorID
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This needs to be an add.
2026-07-10 05:41:54 -04:00
LC
9b7c9f0fb6
Vector: Trim one instruction off insertq
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We can fold a bitwise not and and pair into a bic
2026-07-09 14:58:04 -04:00
Ryan Houdek
5f2455c502
Merge pull request #5665 from lioncash/blendop
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[SVE256] Handle 256-bit blend operations much more efficiently
2026-07-08 16:43:20 -07:00
LC
6bc67609a3
[SVE256] Handle 256-bit blend operations much more efficiently
...
We can massage a given selector into a valid predicate register bitmask
and then simply perform a merging move, which eliminates most busywork
around optimizing 256-bit blends.
In the future, once we drop SVE2.1 support in, we can use PMOV to
eliminate the load from memory and related constant management.
2026-07-08 17:35:12 -04:00
LC
8a8827c980
Merge pull request #5664 from simon902/CMPXCHGZeroing
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OpcodeDispatcher: Fix 32bit cmpxchg zero extension with eax as first operand
2026-07-08 15:14:12 -04:00
Simon Scherer
84fab84b3f
InstcountCI: Update
2026-07-08 15:00:18 +02:00
Ryan Houdek