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InstcountCI: Update
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@@ -652,16 +652,17 @@
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]
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},
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"shld ax, bx, 16": {
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"ExpectedInstructionCount": 7,
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"ExpectedInstructionCount": 8,
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"Comment": "0x0f 0xac",
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"ExpectedArm64ASM": [
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"uxth w20, w6",
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"uxth w21, w4",
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"lsl x21, x21, #16",
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"orr x26, x21, x20",
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"lsl x22, x21, #16",
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"orr x26, x22, x20",
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"cmn wzr, w26, lsl #16",
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"bfxil x4, x26, #0, #16",
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"cfinv"
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"eor x20, x21, #0x1",
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"rmif x20, #63, #nzCv",
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"bfxil x4, x26, #0, #16"
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]
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},
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"shld ax, bx, 31": {
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@@ -1591,18 +1591,20 @@
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]
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},
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"shld ax, bx, 16": {
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"ExpectedInstructionCount": 9,
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"ExpectedInstructionCount": 11,
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"Comment": "0x0f 0xac",
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"ExpectedArm64ASM": [
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"uxth w20, w6",
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"uxth w21, w4",
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"lsl x21, x21, #16",
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"orr x26, x21, x20",
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"lsl x22, x21, #16",
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"orr x26, x22, x20",
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"cmn wzr, w26, lsl #16",
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"bfxil x4, x26, #0, #16",
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"mrs x20, nzcv",
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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"eor x20, x21, #0x1",
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"ubfx x20, x20, #0, #1",
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"mrs x21, nzcv",
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"bfi w21, w20, #29, #1",
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"msr nzcv, x21",
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"bfxil x4, x26, #0, #16"
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]
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},
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"shld ax, bx, 31": {
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