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Code Issues Packages Projects Releases 67 Wiki Activity
14,693 Commits 11 Branches 71 Tags
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Commit Graph
3523 Commits
Author SHA1 Message Date
LC 4254c0f5a9 RegisterAllocationPass: Function cleanup 
Marks a few functions const or static to clarify usage a little more.
 2026-07-13 15:26:51 -04:00
LC 2934b01d58 Vector: Indicate 128-bit zero vector in DefaultX87State() 
Same functional behavior, just makes it visually match the store size
below. Technically also avoids delegating off to the 64-bit element
path if a 128-bit constant zero is already loaded.
 2026-07-13 14:07:12 -04:00
Ryan Houdek 1287365616 64BitAllocator: Removes unused additional size argument 
This used to be used for the intrusively allocated `LiveVMARegion` but
that is all handled internally to the object now, making this
unnecessary. It was always receiving zero and doing nothing so just
remove it.
 2026-07-13 10:18:46 -07:00
Ryan Houdek 4fa539fbb2 Merge pull request #5733 from lioncash/alloc 
64BitAllocator: Avoid madvising more than necessary in InitializeVMARegionsUsed()
 2026-07-13 10:16:57 -07:00
Ryan Houdek 28cdae4687 Merge pull request #5737 from lioncash/bsl 
VectorOps: Simplify SVE 256-bit VOrn with BSL2N
 2026-07-13 10:05:08 -07:00
LC 842e22915c VectorOps: Simplify SVE 256-bit VOrn with BSL2N 
Lets us shave off an instruction and also avoid using a temporary
register in some cases. We can also tweak our worst case that requires a
predicate to eliminate the temporary as well.

We can also expand our cmpps cases, so that we can reflect the
BSL2N usages in instcountci.
 2026-07-13 12:27:54 -04:00
Ryan Houdek bd150233ce Merge pull request #5736 from lioncash/ushrni 
VectorOps: Make SVE shift==0 case symmetric with ASIMD
 2026-07-13 07:56:25 -07:00
LC 24720b67da VectorOps: Make SVE shift==0 case symmetric with ASIMD 
Ensures that we have consistent behavior.
 2026-07-13 10:26:42 -04:00
Ryan Houdek 356d461123 Merge pull request #5734 from lioncash/bytes 
Common/BitSet: Amend byte size retrieval
 2026-07-13 07:07:00 -07:00
LC c0b2eec5de IR: Enclose straggler Desc comments in brackets 
Ensures the comments get rendered properly in output. We can also
make sure that the IR generation script catches this in the future.
 2026-07-13 08:59:45 -04:00
LC 9b8ae25491 Common/BitSet: Amend byte size retrieval 
This needs to divide by 8 to get a proper byte size for all type sizes.
The only usage of this is currently a uint64_t, so it worked by
coincidence, since sizeof(uint64_t) == 8.
 2026-07-13 08:17:27 -04:00
LC c0ee865e3e 64BitAllocator: Avoid madvising more than necessary in InitializeVMARegionsUsed 
Because our bitset type is uint64_t, then that means Memory + ManagedSize
is more like: Memory + (ManagedSize * 8), which is way larger of a base
than we need.
 2026-07-12 20:38:19 -04:00
LC fb2cdc8541 Crypto: Clarify zero vector size in SHA1RNDS4Op() 
This ends up zeroing out the whole 128-bit vector.
 2026-07-12 18:49:27 -04:00
LC 9d3c388664 Crypto: Make use of XAR in SHA1NEXTE when available 
Lets us shave an instruction off on hardware that supports XAR.

Closes #5730
 2026-07-12 16:02:12 -04:00
LC 8b30f7dbb5 64BitAllocator: Remove duplicate headers 
These are already included.
 2026-07-11 23:08:29 -04:00
Ryan Houdek 76b35dfeb0 Merge pull request #5719 from lioncash/small 
64BitAllocator: Avoid overwriting Region[0] in Create64BitAllocatorWithRegions
 2026-07-11 19:30:08 -07:00
Ryan Houdek 066250851f Merge pull request #5717 from lioncash/reg 
RegisterAllocationPass: Amend type cast in DecodeSRANode()
 2026-07-11 17:10:27 -07:00
LC c72d59a3f1 64BitAllocator: Avoid overwriting Region[0] in Create64BitAllocatorWithRegions 
Since this was a reference, this would end up overwriting Region[0] with
whatever the smallest region was instead of just being a running pointer
to what happened to be the current smallest region.

We can switch over to a pointer to avoid obliterating the first memory
region.
 2026-07-11 16:52:01 -04:00
LC 995e2657bb RegisterAllocationPass: Amend type cast in DecodeSRANode() 
Uses the proper type for StoreRegister. Same behavior though, due to
layout.
 2026-07-11 16:39:35 -04:00
LC c7f52bcee4 Vector: Centralize masking in InsertScalarFCMPOp 
Ensures that even if someone threw bogus constants in the upper bits of
the immediate, that the special-cased comparison types would still be
handled properly.

We can move the masking in the AVX variant too, just to be consistent.
 2026-07-11 16:07:19 -04:00
LC 929f9a7ad2 Dispatcher: Avoid loading unnecessary reg in vixl single step 
CompileSingleStep only takes one uint64_t, not two.
 2026-07-11 15:03:29 -04:00
Ryan Houdek 7ce172a497 Merge pull request #5709 from lioncash/size 
FlexBitSet: Simplify MemClear/MemSet
 2026-07-11 10:57:58 -07:00
Ryan Houdek 821dfe5b98 Merge pull request #5708 from lioncash/mrs 
MiscOps: Fix round mode clearing for RP/RM modes in PushRoundingMode
 2026-07-11 10:56:27 -07:00
LC 570d1f2271 FlexBitSet: Simplify MemClear/MemSet 
We can just make use of the helpers already in the interface.
 2026-07-11 10:33:47 -04:00
LC 613e9ef701 MiscOps: Fix round mode clearing for RP/RM modes in PushRoundingMode 
Previously this had the potential to not clear rounding bits properly
depending on incoming FPCR state.
 2026-07-11 10:24:07 -04:00
LC 5080c6ffc5 MemoryOps: Avoid double application of base offset in {Load,Store}ContextIndexed unaligned case 2026-07-11 09:56:56 -04:00
LC 8b0f07b2dc Syscalls: Remove unnecessary usages of namespace FEXCore::IR 
These aren't necessary.
 2026-07-10 21:02:12 -04:00
Ryan Houdek 87301ca154 Merge pull request #5700 from lioncash/bitset 
Common/Bitset: Minor API changes
 2026-07-10 10:35:45 -07:00
Ryan Houdek 650f5b784d Merge pull request #5699 from lioncash/spillops 
Arm64Emitter: Wire up conditional FPR spilling in SpillForPreserveAllABICall
 2026-07-10 10:35:19 -07:00
Ryan Houdek c8dd9eefa6 Merge pull request #5698 from lioncash/dead 
ConversionOps: Remove redundant code in Vector_FToS
 2026-07-10 10:35:06 -07:00
Ryan Houdek d5572e322f Merge pull request #5693 from lioncash/ir 
IR: Use begin block type in operator--
 2026-07-10 10:27:13 -07:00
Ryan Houdek 37814111de Merge pull request #5692 from lioncash/unary 
Vector: Use unary handler for scalar unary insertions
 2026-07-10 10:26:44 -07:00
Ryan Houdek 1417888a89 Merge pull request #5691 from lioncash/fpr 
Vector: LoadSourceGPR -> LoadSourceFPR for MASKMOVOp
 2026-07-10 10:25:26 -07:00
LC 46f3bec37e Common/BitSet: Ensure internal pointer is always initialized 
Provides deterministic state.
 2026-07-10 10:31:45 -04:00
LC f5d2e0db29 Common/BitSet: Mark getters as const 
These don't modify internal state.
 2026-07-10 10:31:05 -04:00
LC 88ee56f471 Common/BitSet: Amend Clear() behavior 
Ensures the bits are actually being unset.
 2026-07-10 10:26:07 -04:00
LC 8436154276 Arm64Emitter: Wire up conditional FPR spilling in SpillForPreserveAllABICall 
Technically, this parameter wasn't being used at all. It was wired up
for filling, but not spilling.
 2026-07-10 10:10:25 -04:00
LC 150b25f29e ConversionOps: Remove redundant code in Vector_FToS 
These are already defined in an outer scope.
 2026-07-10 09:16:35 -04:00
LC 0bfef9008b IR: Use begin block type in operator-- 
Same behavior, just more correct from a descriptive PoV
 2026-07-10 07:31:25 -04:00
LC 401e542fcd Vector: Use unary handler for scalar unary insertions 
Same behavior, but just uses a more proper handler.
 2026-07-10 07:27:54 -04:00
LC 210514f74b Vector: LoadSourceGPR -> LoadSourceFPR for MASKMOVOp 2026-07-10 07:24:39 -04:00
LC dd838d4ad3 MemoryOps: Make use of current working reg for cache operations 
TMP1 technically isn't initialized properly here until after the first
iteration.
 2026-07-10 07:13:17 -04:00
Ryan Houdek 5f2d19c7aa Merge pull request #5685 from lioncash/faddv 2026-07-10 03:33:43 -07:00
Ryan Houdek 95e7c866cf Merge pull request #5682 from lioncash/pid 2026-07-10 03:20:23 -07:00
Ryan Houdek 2effdb04bd Merge pull request #5684 from lioncash/midr 2026-07-10 03:18:25 -07:00
LC ede09a03db VectorOps: Fix 256-bit FADDV path 
Avoids falling down to the SVE-128 path.
 2026-07-10 05:50:22 -04:00
LC 849d60253c CPUID: Fix MIDR walking in SetupHostHybridFlag() 2026-07-10 05:46:16 -04:00
LC b5660c8a92 MiscOps: Avoid stack misalignment in ProcessorID 
This needs to be an add.
 2026-07-10 05:41:54 -04:00
LC 54263bb5a7 ALUOps: Fix 32-bit MulH case 
These need to be 64-bit multiply and ubfx. Thankfully this case wasn't
actually hit in practice.
 2026-07-10 05:39:14 -04:00
LC caa030714b IR: Remove unused VUShraI 
Given that this is currently unused and that we don't have the signed
equivalent implemented, we can just remove this for now.
 2026-07-10 04:15:52 -04:00