Merge pull request #5909 from simon902/fxch_tag_word

Mark both operands valid in the tag word for FXCH
This commit is contained in:
LC authored and GitHub committed 2026-09-04 02:50:17 -04:00
commit a454845ffd
105 files changed
+509 -273

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@@ -1074,8 +1074,8 @@ void X87StackOptimization::Run(IREmitter* Emit) {
// Slow path: do actual memory operations
Ref ValueTop = LoadStackValue();
Ref ValueOffset = LoadStackValue(Offset);
StoreStackValue(ValueOffset);
StoreStackValue(ValueTop, Offset);
StoreStackValue(ValueOffset, 0, true);
StoreStackValue(ValueTop, Offset, true);
} else {
// Fast path: swap complete StackMemberInfo preserving Source metadata
StackData.setTop(StackMemberOffset, 0);
+1 -1
View File
@@ -210,7 +210,7 @@ namespace DiskCache {
// TODO: This header is in global installed header path, but uses internal headers.
// Migrate this once that is fixed.
static constexpr uint16_t FormatVersion = 12;
static constexpr uint16_t FormatVersion = 13;
FEX_DEFAULT_VISIBILITY uint16_t GetFormatVersion();
} // namespace DiskCache
+40
View File
@@ -0,0 +1,40 @@
%ifdef CONFIG
{
"RegData": {
"RAX": "0x3",
"RBX": "0x81"
}
}
%endif
; FXCH: empty and empty operands -> mark both valid
fxrstor [rel .fxsave_data]
fxch st0, st1
fxsave [rel .save]
movzx eax, byte [rel .save + 4]
; FXCH: valid and empty operands -> mark both valid
finit
fldz
fxch st0, st1
fxsave [rel .save2]
movzx ebx, byte [rel .save2 + 4]
hlt
align 16
.fxsave_data:
dw 0x037f ; FCW
dw 0x0000 ; FSW
dw 0x0000 ; FTW
times 506 db 0
align 16
.save:
times 64 dq 0
align 16
.save2:
times 64 dq 0
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"roundss xmm0, xmm1, 00000000b": {
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"cvtpi2ps xmm0, [rax]": {
@@ -9,7 +9,7 @@
"DisabledHostFeatures": [
"RPRES"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"cvtsi2ss xmm0, eax": {
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"cvtsi2sd xmm0, eax": {
@@ -8,7 +8,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"cvtpi2ps xmm0, [rax]": {
@@ -9,7 +9,7 @@
"SVE256",
"RPRES"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"cvtsi2ss xmm0, eax": {
@@ -8,7 +8,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"cvtsi2sd xmm0, eax": {
@@ -9,7 +9,7 @@
"DisabledHostFeatures": [
"RPRES"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vsqrtss xmm0, xmm1, xmm2": {
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vroundss xmm0, xmm1, 00000000b": {
@@ -7,7 +7,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vfmaddsubps xmm0, xmm1, xmm2, xmm3": {
@@ -13,7 +13,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vmovups xmm0, xmm0": {
@@ -9,7 +9,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vaddsubpd xmm0, xmm1, xmm2": {
@@ -10,7 +10,7 @@
"FLAGM2",
"SVE256"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vmovntps [rax], xmm0": {
@@ -10,7 +10,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vucomiss xmm0, xmm1": {
@@ -9,7 +9,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vpshufb xmm0, xmm1, xmm2": {
@@ -8,7 +8,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vfmadd132ss xmm0, xmm1, xmm2": {
@@ -10,7 +10,7 @@
"FLAGM2",
"SVE256"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vmovntdqa xmm0, [rax]": {
@@ -11,7 +11,7 @@
"SVE256",
"SVEBITPERM"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vtestps xmm0, xmm1": {
@@ -7,7 +7,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vpermq ymm0, ymm1, 1": {
@@ -8,7 +8,7 @@
"AFP",
"SVE256"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vblendvps xmm0, xmm1, xmm2, xmm3": {
@@ -9,7 +9,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vpsrlw xmm0, xmm1, 0": {
+1 -1
View File
@@ -9,7 +9,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"lock add byte [rax], cl": {
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"sha1nexte xmm0, xmm1": {
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"sha1nexte xmm0, xmm1": {
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"pclmulqdq xmm0, xmm1, 00000b": {
+1 -1
View File
@@ -10,7 +10,7 @@
"AFP",
"RPRES"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Comment": [
"These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers",
@@ -8,7 +8,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Comment": [
"Instructions that explicitly push against the limits of ARM's loadstore instructions"
@@ -8,7 +8,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Comment": [
"Instructions that explicitly push against the limits of ARM's loadstore instructions"
@@ -13,7 +13,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
@@ -11,7 +11,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
@@ -9,7 +9,7 @@
"SVE256",
"RPRES"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
@@ -14,7 +14,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
@@ -14,7 +14,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
@@ -12,7 +12,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Comment": [],
"Instructions": {
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"lock add byte [rax], cl": {
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"Chained add": {
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"ptest xmm0, xmm1": {
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"The Witcher 3": {
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"Sonic Mania movie player": {
@@ -10,7 +10,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"FMOD scalar loop": {
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"The Sims 1 hot block": {
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"add bl, cl": {
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"add al, 1": {
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"push es": {
@@ -11,7 +11,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"ucomiss xmm0, xmm1": {
@@ -11,7 +11,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"sgdt [rax]": {
@@ -11,7 +11,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"xgetbv": {
@@ -11,7 +11,7 @@
"AFP",
"FCMA"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"ucomisd xmm0, xmm1": {
@@ -12,7 +12,7 @@
"AFP",
"CSSC"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"popcnt ax, bx": {
@@ -12,7 +12,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"popcnt ax, bx": {
@@ -12,7 +12,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vucomiss xmm0, xmm1": {
@@ -10,7 +10,7 @@
"AFP",
"SVEBITPERM"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vtestps xmm0, xmm1": {
@@ -9,7 +9,7 @@
"DisabledHostFeatures": [
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"blsr eax, ebx": {
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"Block1": {
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"Block1": {
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"Block1": {
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"Block1": {
+92 -43
View File
@@ -11,7 +11,7 @@
"CSSC",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"fadd dword [rax]": {
@@ -2364,7 +2364,7 @@
]
},
"fxch st0, st1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xc9 /1"
],
@@ -2372,17 +2372,24 @@
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str q3, [x21, #1056]",
"str q2, [x20, #1056]"
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x303",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st2": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xca /1"
],
@@ -2390,17 +2397,24 @@
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"add w22, w20, #0x2 (2)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str q3, [x21, #1056]",
"str q2, [x20, #1056]"
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x505",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st3": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xcb /1"
],
@@ -2408,17 +2422,24 @@
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x3 (3)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"add w22, w20, #0x3 (3)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str q3, [x21, #1056]",
"str q2, [x20, #1056]"
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x909",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st4": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xcc /1"
],
@@ -2426,17 +2447,24 @@
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"add w22, w20, #0x4 (4)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str q3, [x21, #1056]",
"str q2, [x20, #1056]"
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x1111",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st5": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xcd /1"
],
@@ -2444,17 +2472,24 @@
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"add w22, w20, #0x5 (5)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str q3, [x21, #1056]",
"str q2, [x20, #1056]"
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x2121",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st6": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xce /1"
],
@@ -2462,17 +2497,24 @@
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"add w22, w20, #0x6 (6)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str q3, [x21, #1056]",
"str q2, [x20, #1056]"
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x4141",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st7": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xcf /1"
],
@@ -2480,13 +2522,20 @@
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"add w22, w20, #0x7 (7)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str q3, [x21, #1056]",
"str q2, [x20, #1056]"
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x8181",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fnop": {
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"Block1": {
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"Block1": {
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"Block1": {
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"Block1": {
+92 -43
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"fadd dword [rax]": {
@@ -1774,7 +1774,7 @@
]
},
"fxch st0, st1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xc9 /1"
],
@@ -1782,17 +1782,24 @@
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr d3, [x20, #1056]",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr d3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str d3, [x21, #1056]",
"str d2, [x20, #1056]"
"str d2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x303",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st2": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xca /1"
],
@@ -1800,17 +1807,24 @@
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1056]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr d3, [x20, #1056]",
"add w22, w20, #0x2 (2)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr d3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str d3, [x21, #1056]",
"str d2, [x20, #1056]"
"str d2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x505",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st3": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xcb /1"
],
@@ -1818,17 +1832,24 @@
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1056]",
"add w20, w20, #0x3 (3)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr d3, [x20, #1056]",
"add w22, w20, #0x3 (3)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr d3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str d3, [x21, #1056]",
"str d2, [x20, #1056]"
"str d2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x909",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st4": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xcc /1"
],
@@ -1836,17 +1857,24 @@
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1056]",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr d3, [x20, #1056]",
"add w22, w20, #0x4 (4)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr d3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str d3, [x21, #1056]",
"str d2, [x20, #1056]"
"str d2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x1111",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st5": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xcd /1"
],
@@ -1854,17 +1882,24 @@
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1056]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr d3, [x20, #1056]",
"add w22, w20, #0x5 (5)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr d3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str d3, [x21, #1056]",
"str d2, [x20, #1056]"
"str d2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x2121",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st6": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xce /1"
],
@@ -1872,17 +1907,24 @@
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1056]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr d3, [x20, #1056]",
"add w22, w20, #0x6 (6)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr d3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str d3, [x21, #1056]",
"str d2, [x20, #1056]"
"str d2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x4141",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st7": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xcf /1"
],
@@ -1890,13 +1932,20 @@
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr d3, [x20, #1056]",
"add w22, w20, #0x7 (7)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr d3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str d3, [x21, #1056]",
"str d2, [x20, #1056]"
"str d2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x8181",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fnop": {
+1 -1
View File
@@ -10,7 +10,7 @@
"FLAGM2",
"CRYPTO"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"pshufb mm0, mm1": {
+1 -1
View File
@@ -8,7 +8,7 @@
"AFP",
"CRYPTO"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Comment": [
"SSE4.2 string instructions are skipped here.",
@@ -8,7 +8,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"dpps xmm0, xmm1, 00000000b": {
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"rep movsb": {
+1 -1
View File
@@ -10,7 +10,7 @@
"FLAGM2",
"MOPS"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"add bl, cl": {
@@ -9,7 +9,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Comment": [
"Instructions in this table that are marked optimal don't have their flag calculation part of this assumption",
@@ -9,7 +9,7 @@
"FlagM",
"FlagM2"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"push es": {
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"pfrcpv mm0, mm1": {
@@ -9,7 +9,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"rsqrtps xmm0, xmm1": {
@@ -9,7 +9,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"rsqrtss xmm0, xmm1": {
@@ -8,7 +8,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vrsqrtps xmm0, xmm1": {
+1 -1
View File
@@ -6,7 +6,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {}
}
@@ -33,7 +33,7 @@
" - 1b: ECX = MSB",
"[7] - Reserved"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"pcmpestrm xmm0, xmm1, 0_0_00_00_00b": {
+1 -1
View File
@@ -12,7 +12,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Comment": [
"MMX instructions are defined as optimal without SRA being used for these instructions.",
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"sgdt [rax]": {
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"xgetbv": {
@@ -7,7 +7,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"push fs": {
@@ -12,7 +12,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"movupd xmm0, xmm0": {
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"addsubpd xmm0, xmm1": {
@@ -8,7 +8,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"psrlw xmm0, xmm1": {
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"pmulhuw xmm0, xmm1": {
@@ -12,7 +12,7 @@
"FRINTTS",
"CSSC"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"movss xmm0, xmm1": {
@@ -10,7 +10,7 @@
"FCMA",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"movsd xmm0, xmm1": {
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"addsubps xmm0, xmm1": {
@@ -10,7 +10,7 @@
"FCMA",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"cvtpd2dq xmm0, xmm1": {
@@ -12,7 +12,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"cvttss2si eax, xmm0": {
@@ -8,7 +8,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"movmskps eax, xmm0": {
+1 -1
View File
@@ -13,7 +13,7 @@
"FLAGM2",
"FRINTTS"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vmovups xmm0, xmm0": {
@@ -8,7 +8,7 @@
"FCMA"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vaddsubpd xmm0, xmm1, xmm2": {
@@ -13,7 +13,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vcvttss2si eax, xmm0": {
+1 -1
View File
@@ -11,7 +11,7 @@
"FLAGM2",
"SVEBITPERM"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vpshufb xmm0, xmm1, xmm2": {
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"pext eax, ebx, ecx": {
+1 -1
View File
@@ -8,7 +8,7 @@
"DisabledHostFeatures": [
"AFP"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vpermq ymm0, ymm1, 1": {
@@ -9,7 +9,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 12
"BinaryCacheVersion": 13
},
"Instructions": {
"vpsrlw xmm0, xmm1, 0": {
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