mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 08:00:15 +02:00
753 lines
20 KiB
JSON
753 lines
20 KiB
JSON
{
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"Features": {
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"Bitness": 64,
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"EnabledHostFeatures": [
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"FLAGM",
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"FLAGM2"
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],
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"DisabledHostFeatures": [
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"AFP",
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"SVE128",
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"SVE256",
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"SVEBITPERM"
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],
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"BinaryCacheVersion": 13
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},
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"Instructions": {
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"vtestps xmm0, xmm1": {
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"ExpectedInstructionCount": 16,
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"Comment": [
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"Map 2 0b01 0x0e 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov w20, #0x80000000",
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"dup v2.4s, w20",
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"and v3.16b, v17.16b, v16.16b",
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"bic v4.16b, v17.16b, v16.16b",
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"and v3.16b, v3.16b, v2.16b",
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"and v2.16b, v4.16b, v2.16b",
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"umaxv h3, v3.8h",
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"umaxv h2, v2.8h",
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"umov w20, v3.h[0]",
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"umov w21, v2.h[0]",
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"mov w27, #0x0",
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"cmp x21, #0x0 (0)",
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"cset x21, ne",
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"cmp w20, #0x0 (0)",
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"rmif x21, #63, #nzCv",
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"mov w26, #0x1"
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]
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},
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"vtestps ymm0, ymm1": {
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"ExpectedInstructionCount": 22,
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"Comment": [
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"Map 2 0b01 0x0e 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #192]",
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"ldr q3, [x28, #208]",
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"and v4.16b, v17.16b, v16.16b",
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"and v5.16b, v3.16b, v2.16b",
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"ushr v4.4s, v4.4s, #31",
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"ushr v5.4s, v5.4s, #31",
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"add v4.4s, v5.4s, v4.4s",
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"addv s4, v4.4s",
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"mov w20, v4.s[0]",
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"bic v4.16b, v17.16b, v16.16b",
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"bic v2.16b, v3.16b, v2.16b",
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"ushr v4.4s, v4.4s, #31",
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"ushr v2.4s, v2.4s, #31",
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"add v2.4s, v2.4s, v4.4s",
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"addv s2, v2.4s",
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"mov w21, v2.s[0]",
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"mov w27, #0x0",
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"cmp x21, #0x0 (0)",
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"cset x21, ne",
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"cmp w20, #0x0 (0)",
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"rmif x21, #63, #nzCv",
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"mov w26, #0x1"
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]
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},
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"vtestpd xmm0, xmm1": {
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"ExpectedInstructionCount": 16,
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"Comment": [
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"Map 2 0b01 0x0f 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov x20, #0x8000000000000000",
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"dup v2.2d, x20",
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"and v3.16b, v17.16b, v16.16b",
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"bic v4.16b, v17.16b, v16.16b",
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"and v3.16b, v3.16b, v2.16b",
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"and v2.16b, v4.16b, v2.16b",
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"umaxv h3, v3.8h",
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"umaxv h2, v2.8h",
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"umov w20, v3.h[0]",
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"umov w21, v2.h[0]",
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"mov w27, #0x0",
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"cmp x21, #0x0 (0)",
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"cset x21, ne",
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"cmp w20, #0x0 (0)",
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"rmif x21, #63, #nzCv",
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"mov w26, #0x1"
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]
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},
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"vtestpd ymm0, ymm1": {
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"ExpectedInstructionCount": 22,
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"Comment": [
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"Map 2 0b01 0x0f 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #192]",
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"ldr q3, [x28, #208]",
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"and v4.16b, v17.16b, v16.16b",
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"and v5.16b, v3.16b, v2.16b",
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"ushr v4.2d, v4.2d, #63",
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"ushr v5.2d, v5.2d, #63",
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"add v4.2d, v5.2d, v4.2d",
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"addp v4.2d, v4.2d, v4.2d",
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"mov x20, v4.d[0]",
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"bic v4.16b, v17.16b, v16.16b",
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"bic v2.16b, v3.16b, v2.16b",
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"ushr v4.2d, v4.2d, #63",
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"ushr v2.2d, v2.2d, #63",
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"add v2.2d, v2.2d, v4.2d",
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"addp v2.2d, v2.2d, v2.2d",
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"mov x21, v2.d[0]",
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"mov w27, #0x0",
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"cmp x21, #0x0 (0)",
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"cset x21, ne",
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"cmp w20, #0x0 (0)",
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"rmif x21, #63, #nzCv",
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"mov w26, #0x1"
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]
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},
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"vptest xmm0, xmm1": {
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"ExpectedInstructionCount": 12,
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"Comment": [
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"Map 2 0b01 0x16 128-bit"
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],
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"ExpectedArm64ASM": [
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"and v2.16b, v16.16b, v17.16b",
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"bic v3.16b, v17.16b, v16.16b",
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"umaxv h2, v2.8h",
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"umaxv h3, v3.8h",
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"umov w20, v2.h[0]",
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"umov w21, v3.h[0]",
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"mov w27, #0x0",
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"cmp x21, #0x0 (0)",
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"cset x21, ne",
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"cmp w20, #0x0 (0)",
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"rmif x21, #63, #nzCv",
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"mov w26, #0x1"
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]
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},
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"vptest ymm0, ymm1": {
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"ExpectedInstructionCount": 18,
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"Comment": [
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"Map 2 0b01 0x16 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #192]",
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"ldr q3, [x28, #208]",
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"and v4.16b, v16.16b, v17.16b",
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"bic v5.16b, v17.16b, v16.16b",
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"and v6.16b, v2.16b, v3.16b",
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"bic v2.16b, v3.16b, v2.16b",
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"umax v3.8h, v4.8h, v6.8h",
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"umax v2.8h, v5.8h, v2.8h",
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"umaxv h3, v3.8h",
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"umaxv h2, v2.8h",
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"umov w20, v3.h[0]",
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"umov w21, v2.h[0]",
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"mov w27, #0x0",
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"cmp x21, #0x0 (0)",
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"cset x21, ne",
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"cmp w20, #0x0 (0)",
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"rmif x21, #63, #nzCv",
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"mov w26, #0x1"
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]
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},
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"vmaskmovps xmm0, xmm1, [rax]": {
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"ExpectedInstructionCount": 18,
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"Comment": [
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"Map 2 0b01 0x2c 128-bit"
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],
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"ExpectedArm64ASM": [
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"movi v0.2d, #0x0",
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"mov w0, v17.s[0]",
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"tbz w0, #31, #+0x8",
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"ld1 {v0.s}[0], [x4]",
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"add x1, x4, #0x4 (4)",
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"mov w0, v17.s[1]",
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"tbz w0, #31, #+0x8",
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"ld1 {v0.s}[1], [x1]",
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"add x1, x1, #0x4 (4)",
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"mov w0, v17.s[2]",
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"tbz w0, #31, #+0x8",
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"ld1 {v0.s}[2], [x1]",
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"add x1, x1, #0x4 (4)",
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"mov w0, v17.s[3]",
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"tbz w0, #31, #+0x8",
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"ld1 {v0.s}[3], [x1]",
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"mov v16.16b, v0.16b",
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"stp xzr, xzr, [x28, #192]"
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]
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},
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"vmaskmovps ymm0, ymm1, [rax]": {
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"ExpectedInstructionCount": 37,
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"Comment": [
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"Map 2 0b01 0x2c 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #208]",
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"movi v0.2d, #0x0",
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"mov w0, v17.s[0]",
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"tbz w0, #31, #+0x8",
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"ld1 {v0.s}[0], [x4]",
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"add x1, x4, #0x4 (4)",
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"mov w0, v17.s[1]",
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"tbz w0, #31, #+0x8",
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"ld1 {v0.s}[1], [x1]",
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"add x1, x1, #0x4 (4)",
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"mov w0, v17.s[2]",
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"tbz w0, #31, #+0x8",
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"ld1 {v0.s}[2], [x1]",
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"add x1, x1, #0x4 (4)",
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"mov w0, v17.s[3]",
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"tbz w0, #31, #+0x8",
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"ld1 {v0.s}[3], [x1]",
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"mov v16.16b, v0.16b",
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"movi v0.2d, #0x0",
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"add x1, x4, #0x10 (16)",
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"mov w0, v2.s[0]",
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"tbz w0, #31, #+0x8",
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"ld1 {v0.s}[0], [x1]",
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"add x1, x1, #0x4 (4)",
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"mov w0, v2.s[1]",
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"tbz w0, #31, #+0x8",
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"ld1 {v0.s}[1], [x1]",
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"add x1, x1, #0x4 (4)",
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"mov w0, v2.s[2]",
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"tbz w0, #31, #+0x8",
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"ld1 {v0.s}[2], [x1]",
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"add x1, x1, #0x4 (4)",
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"mov w0, v2.s[3]",
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"tbz w0, #31, #+0x8",
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"ld1 {v0.s}[3], [x1]",
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"mov v2.16b, v0.16b",
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"str q2, [x28, #192]"
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]
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},
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"vmaskmovpd xmm0, xmm1, [rax]": {
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"ExpectedInstructionCount": 10,
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"Comment": [
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"Map 2 0b01 0x2d 128-bit"
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],
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"ExpectedArm64ASM": [
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"movi v0.2d, #0x0",
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"mov x0, v17.d[0]",
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"tbz x0, #63, #+0x8",
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"ld1 {v0.d}[0], [x4]",
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"add x1, x4, #0x8 (8)",
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"mov x0, v17.d[1]",
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"tbz x0, #63, #+0x8",
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"ld1 {v0.d}[1], [x1]",
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"mov v16.16b, v0.16b",
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"stp xzr, xzr, [x28, #192]"
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]
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},
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"vmaskmovpd ymm0, ymm1, [rax]": {
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"ExpectedInstructionCount": 21,
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"Comment": [
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"Map 2 0b01 0x2d 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #208]",
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"movi v0.2d, #0x0",
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"mov x0, v17.d[0]",
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"tbz x0, #63, #+0x8",
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"ld1 {v0.d}[0], [x4]",
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"add x1, x4, #0x8 (8)",
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"mov x0, v17.d[1]",
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"tbz x0, #63, #+0x8",
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"ld1 {v0.d}[1], [x1]",
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"mov v16.16b, v0.16b",
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"movi v0.2d, #0x0",
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"add x1, x4, #0x10 (16)",
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"mov x0, v2.d[0]",
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"tbz x0, #63, #+0x8",
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"ld1 {v0.d}[0], [x1]",
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"add x1, x1, #0x8 (8)",
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"mov x0, v2.d[1]",
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"tbz x0, #63, #+0x8",
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"ld1 {v0.d}[1], [x1]",
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"mov v2.16b, v0.16b",
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"str q2, [x28, #192]"
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]
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},
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"vmaskmovps [rax], xmm0, xmm1": {
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"ExpectedInstructionCount": 15,
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"Comment": [
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"Map 2 0b01 0x2e 128-bit"
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],
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"ExpectedArm64ASM": [
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"mov w0, v16.s[0]",
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"tbz w0, #31, #+0x8",
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"st1 {v17.s}[0], [x4]",
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"add x1, x4, #0x4 (4)",
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"mov w0, v16.s[1]",
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"tbz w0, #31, #+0x8",
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"st1 {v17.s}[1], [x1]",
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"add x1, x1, #0x4 (4)",
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"mov w0, v16.s[2]",
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"tbz w0, #31, #+0x8",
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"st1 {v17.s}[2], [x1]",
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"add x1, x1, #0x4 (4)",
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"mov w0, v16.s[3]",
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"tbz w0, #31, #+0x8",
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"st1 {v17.s}[3], [x1]"
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]
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},
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"vmaskmovps [rax], ymm0, ymm1": {
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"ExpectedInstructionCount": 33,
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"Comment": [
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"Map 2 0b01 0x2e 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #192]",
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"ldr q3, [x28, #208]",
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"mov w0, v16.s[0]",
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"tbz w0, #31, #+0x8",
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"st1 {v17.s}[0], [x4]",
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"add x1, x4, #0x4 (4)",
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"mov w0, v16.s[1]",
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"tbz w0, #31, #+0x8",
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"st1 {v17.s}[1], [x1]",
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"add x1, x1, #0x4 (4)",
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"mov w0, v16.s[2]",
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"tbz w0, #31, #+0x8",
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"st1 {v17.s}[2], [x1]",
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"add x1, x1, #0x4 (4)",
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"mov w0, v16.s[3]",
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"tbz w0, #31, #+0x8",
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"st1 {v17.s}[3], [x1]",
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"add x1, x4, #0x10 (16)",
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"mov w0, v2.s[0]",
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"tbz w0, #31, #+0x8",
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"st1 {v3.s}[0], [x1]",
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"add x1, x1, #0x4 (4)",
|
|
"mov w0, v2.s[1]",
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|
"tbz w0, #31, #+0x8",
|
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"st1 {v3.s}[1], [x1]",
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|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v2.s[2]",
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"tbz w0, #31, #+0x8",
|
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"st1 {v3.s}[2], [x1]",
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|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v2.s[3]",
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|
"tbz w0, #31, #+0x8",
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"st1 {v3.s}[3], [x1]"
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]
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|
},
|
|
"vmaskmovpd [rax], xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 2 0b01 0x2f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov x0, v16.d[0]",
|
|
"tbz x0, #63, #+0x8",
|
|
"st1 {v17.d}[0], [x4]",
|
|
"add x1, x4, #0x8 (8)",
|
|
"mov x0, v16.d[1]",
|
|
"tbz x0, #63, #+0x8",
|
|
"st1 {v17.d}[1], [x1]"
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|
]
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|
},
|
|
"vmaskmovpd [rax], ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"Map 2 0b01 0x2f 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #208]",
|
|
"mov x0, v16.d[0]",
|
|
"tbz x0, #63, #+0x8",
|
|
"st1 {v17.d}[0], [x4]",
|
|
"add x1, x4, #0x8 (8)",
|
|
"mov x0, v16.d[1]",
|
|
"tbz x0, #63, #+0x8",
|
|
"st1 {v17.d}[1], [x1]",
|
|
"add x1, x4, #0x10 (16)",
|
|
"mov x0, v2.d[0]",
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|
"tbz x0, #63, #+0x8",
|
|
"st1 {v3.d}[0], [x1]",
|
|
"add x1, x1, #0x8 (8)",
|
|
"mov x0, v2.d[1]",
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|
"tbz x0, #63, #+0x8",
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"st1 {v3.d}[1], [x1]"
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]
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},
|
|
"vpmaskmovd xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Comment": [
|
|
"Map 2 0b01 0x8c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"movi v0.2d, #0x0",
|
|
"mov w0, v17.s[0]",
|
|
"tbz w0, #31, #+0x8",
|
|
"ld1 {v0.s}[0], [x4]",
|
|
"add x1, x4, #0x4 (4)",
|
|
"mov w0, v17.s[1]",
|
|
"tbz w0, #31, #+0x8",
|
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"ld1 {v0.s}[1], [x1]",
|
|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v17.s[2]",
|
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"tbz w0, #31, #+0x8",
|
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"ld1 {v0.s}[2], [x1]",
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"add x1, x1, #0x4 (4)",
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"mov w0, v17.s[3]",
|
|
"tbz w0, #31, #+0x8",
|
|
"ld1 {v0.s}[3], [x1]",
|
|
"mov v16.16b, v0.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmaskmovd ymm0, ymm1, [rax]": {
|
|
"ExpectedInstructionCount": 37,
|
|
"Comment": [
|
|
"Map 2 0b01 0x8c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"movi v0.2d, #0x0",
|
|
"mov w0, v17.s[0]",
|
|
"tbz w0, #31, #+0x8",
|
|
"ld1 {v0.s}[0], [x4]",
|
|
"add x1, x4, #0x4 (4)",
|
|
"mov w0, v17.s[1]",
|
|
"tbz w0, #31, #+0x8",
|
|
"ld1 {v0.s}[1], [x1]",
|
|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v17.s[2]",
|
|
"tbz w0, #31, #+0x8",
|
|
"ld1 {v0.s}[2], [x1]",
|
|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v17.s[3]",
|
|
"tbz w0, #31, #+0x8",
|
|
"ld1 {v0.s}[3], [x1]",
|
|
"mov v16.16b, v0.16b",
|
|
"movi v0.2d, #0x0",
|
|
"add x1, x4, #0x10 (16)",
|
|
"mov w0, v2.s[0]",
|
|
"tbz w0, #31, #+0x8",
|
|
"ld1 {v0.s}[0], [x1]",
|
|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v2.s[1]",
|
|
"tbz w0, #31, #+0x8",
|
|
"ld1 {v0.s}[1], [x1]",
|
|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v2.s[2]",
|
|
"tbz w0, #31, #+0x8",
|
|
"ld1 {v0.s}[2], [x1]",
|
|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v2.s[3]",
|
|
"tbz w0, #31, #+0x8",
|
|
"ld1 {v0.s}[3], [x1]",
|
|
"mov v2.16b, v0.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmaskmovq xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
|
"Map 2 0b01 0x8c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"movi v0.2d, #0x0",
|
|
"mov x0, v17.d[0]",
|
|
"tbz x0, #63, #+0x8",
|
|
"ld1 {v0.d}[0], [x4]",
|
|
"add x1, x4, #0x8 (8)",
|
|
"mov x0, v17.d[1]",
|
|
"tbz x0, #63, #+0x8",
|
|
"ld1 {v0.d}[1], [x1]",
|
|
"mov v16.16b, v0.16b",
|
|
"stp xzr, xzr, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmaskmovq ymm0, ymm1, [rax]": {
|
|
"ExpectedInstructionCount": 21,
|
|
"Comment": [
|
|
"Map 2 0b01 0x8c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #208]",
|
|
"movi v0.2d, #0x0",
|
|
"mov x0, v17.d[0]",
|
|
"tbz x0, #63, #+0x8",
|
|
"ld1 {v0.d}[0], [x4]",
|
|
"add x1, x4, #0x8 (8)",
|
|
"mov x0, v17.d[1]",
|
|
"tbz x0, #63, #+0x8",
|
|
"ld1 {v0.d}[1], [x1]",
|
|
"mov v16.16b, v0.16b",
|
|
"movi v0.2d, #0x0",
|
|
"add x1, x4, #0x10 (16)",
|
|
"mov x0, v2.d[0]",
|
|
"tbz x0, #63, #+0x8",
|
|
"ld1 {v0.d}[0], [x1]",
|
|
"add x1, x1, #0x8 (8)",
|
|
"mov x0, v2.d[1]",
|
|
"tbz x0, #63, #+0x8",
|
|
"ld1 {v0.d}[1], [x1]",
|
|
"mov v2.16b, v0.16b",
|
|
"str q2, [x28, #192]"
|
|
]
|
|
},
|
|
"vpmaskmovd [rax], xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"Map 2 0b01 0x8e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov w0, v16.s[0]",
|
|
"tbz w0, #31, #+0x8",
|
|
"st1 {v17.s}[0], [x4]",
|
|
"add x1, x4, #0x4 (4)",
|
|
"mov w0, v16.s[1]",
|
|
"tbz w0, #31, #+0x8",
|
|
"st1 {v17.s}[1], [x1]",
|
|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v16.s[2]",
|
|
"tbz w0, #31, #+0x8",
|
|
"st1 {v17.s}[2], [x1]",
|
|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v16.s[3]",
|
|
"tbz w0, #31, #+0x8",
|
|
"st1 {v17.s}[3], [x1]"
|
|
]
|
|
},
|
|
"vpmaskmovd [rax], ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 33,
|
|
"Comment": [
|
|
"Map 2 0b01 0x8e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #208]",
|
|
"mov w0, v16.s[0]",
|
|
"tbz w0, #31, #+0x8",
|
|
"st1 {v17.s}[0], [x4]",
|
|
"add x1, x4, #0x4 (4)",
|
|
"mov w0, v16.s[1]",
|
|
"tbz w0, #31, #+0x8",
|
|
"st1 {v17.s}[1], [x1]",
|
|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v16.s[2]",
|
|
"tbz w0, #31, #+0x8",
|
|
"st1 {v17.s}[2], [x1]",
|
|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v16.s[3]",
|
|
"tbz w0, #31, #+0x8",
|
|
"st1 {v17.s}[3], [x1]",
|
|
"add x1, x4, #0x10 (16)",
|
|
"mov w0, v2.s[0]",
|
|
"tbz w0, #31, #+0x8",
|
|
"st1 {v3.s}[0], [x1]",
|
|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v2.s[1]",
|
|
"tbz w0, #31, #+0x8",
|
|
"st1 {v3.s}[1], [x1]",
|
|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v2.s[2]",
|
|
"tbz w0, #31, #+0x8",
|
|
"st1 {v3.s}[2], [x1]",
|
|
"add x1, x1, #0x4 (4)",
|
|
"mov w0, v2.s[3]",
|
|
"tbz w0, #31, #+0x8",
|
|
"st1 {v3.s}[3], [x1]"
|
|
]
|
|
},
|
|
"vpmaskmovq [rax], xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": [
|
|
"Map 2 0b01 0x8e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov x0, v16.d[0]",
|
|
"tbz x0, #63, #+0x8",
|
|
"st1 {v17.d}[0], [x4]",
|
|
"add x1, x4, #0x8 (8)",
|
|
"mov x0, v16.d[1]",
|
|
"tbz x0, #63, #+0x8",
|
|
"st1 {v17.d}[1], [x1]"
|
|
]
|
|
},
|
|
"vpmaskmovq [rax], ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": [
|
|
"Map 2 0b01 0x8e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #192]",
|
|
"ldr q3, [x28, #208]",
|
|
"mov x0, v16.d[0]",
|
|
"tbz x0, #63, #+0x8",
|
|
"st1 {v17.d}[0], [x4]",
|
|
"add x1, x4, #0x8 (8)",
|
|
"mov x0, v16.d[1]",
|
|
"tbz x0, #63, #+0x8",
|
|
"st1 {v17.d}[1], [x1]",
|
|
"add x1, x4, #0x10 (16)",
|
|
"mov x0, v2.d[0]",
|
|
"tbz x0, #63, #+0x8",
|
|
"st1 {v3.d}[0], [x1]",
|
|
"add x1, x1, #0x8 (8)",
|
|
"mov x0, v2.d[1]",
|
|
"tbz x0, #63, #+0x8",
|
|
"st1 {v3.d}[1], [x1]"
|
|
]
|
|
},
|
|
"andn eax, ebx, ecx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 2 0b00 0xf2 32-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"bic w4, w7, w6",
|
|
"subs w26, w4, #0x0 (0)"
|
|
]
|
|
},
|
|
"andn rax, rbx, rcx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Map 2 0b00 0xf2 64-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"bic x4, x7, x6",
|
|
"subs x26, x4, #0x0 (0)"
|
|
]
|
|
},
|
|
"bzhi eax, ebx, ecx": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"Map 2 0b00 0xf5 32-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"lsl w20, w20, w7",
|
|
"bic w20, w6, w20",
|
|
"tst x7, #0xe0",
|
|
"csel w4, w6, w20, ne",
|
|
"cset x20, eq",
|
|
"cmp w4, #0x0 (0)",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"bzhi rax, rbx, rcx": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": [
|
|
"Map 2 0b00 0xf5 64-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"lsl x20, x20, x7",
|
|
"bic x20, x6, x20",
|
|
"tst x7, #0xc0",
|
|
"csel x4, x6, x20, ne",
|
|
"cset x20, eq",
|
|
"cmp x4, #0x0 (0)",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"pdep eax, ebx, ecx": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"Map 2 0b11 0xf5 32-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov x0, x6",
|
|
"mov x1, x7",
|
|
"mov w4, #0x0",
|
|
"cbz w1, #+0x2c",
|
|
"neg w2, w1",
|
|
"and w2, w2, w1",
|
|
"sbfx w3, w0, #0, #1",
|
|
"eor w1, w1, w2",
|
|
"and w2, w3, w2",
|
|
"neg w3, w1",
|
|
"orr w4, w4, w2",
|
|
"lsr w0, w0, #1",
|
|
"and w2, w1, w3",
|
|
"cbnz w2, #-0x1c"
|
|
]
|
|
},
|
|
"pdep rax, rbx, rcx": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"Map 2 0b11 0xf5 64-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov x0, x6",
|
|
"mov x1, x7",
|
|
"mov x4, #0x0",
|
|
"cbz x1, #+0x2c",
|
|
"neg x2, x1",
|
|
"and x2, x2, x1",
|
|
"sbfx x3, x0, #0, #1",
|
|
"eor x1, x1, x2",
|
|
"and x2, x3, x2",
|
|
"neg x3, x1",
|
|
"orr x4, x4, x2",
|
|
"lsr x0, x0, #1",
|
|
"and x2, x1, x3",
|
|
"cbnz x2, #-0x1c"
|
|
]
|
|
},
|
|
"bextr eax, ebx, ecx": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"Map 2 0b00 0xf7 32-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w7",
|
|
"lsr w21, w6, w20",
|
|
"mov w22, #0x0",
|
|
"cmp w20, #0x1f (31)",
|
|
"csel w20, w21, w22, ls",
|
|
"ubfx w21, w7, #8, #8",
|
|
"mov x22, #0xffffffffffffffff",
|
|
"lsl w22, w22, w21",
|
|
"bic w22, w20, w22",
|
|
"cmp w21, #0x1f (31)",
|
|
"csel w4, w22, w20, ls",
|
|
"cmp w4, #0x0 (0)"
|
|
]
|
|
},
|
|
"bextr rax, rbx, rcx": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": [
|
|
"Map 2 0b00 0xf7 64-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uxtb x20, w7",
|
|
"lsr x21, x6, x20",
|
|
"mov w22, #0x0",
|
|
"cmp x20, #0x3f (63)",
|
|
"csel x20, x21, x22, ls",
|
|
"ubfx x21, x7, #8, #8",
|
|
"mov x22, #0xffffffffffffffff",
|
|
"lsl x22, x22, x21",
|
|
"bic x22, x20, x22",
|
|
"cmp x21, #0x3f (63)",
|
|
"csel x4, x22, x20, ls",
|
|
"cmp x4, #0x0 (0)"
|
|
]
|
|
}
|
|
}
|
|
}
|