diff --git a/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp b/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp
index dfaf74a96..8dcc220e3 100644
--- a/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp
+++ b/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp
@@ -1074,8 +1074,8 @@ void X87StackOptimization::Run(IREmitter* Emit) {
           // Slow path: do actual memory operations
           Ref ValueTop = LoadStackValue();
           Ref ValueOffset = LoadStackValue(Offset);
-          StoreStackValue(ValueOffset);
-          StoreStackValue(ValueTop, Offset);
+          StoreStackValue(ValueOffset, 0, true);
+          StoreStackValue(ValueTop, Offset, true);
         } else {
           // Fast path: swap complete StackMemberInfo preserving Source metadata
           StackData.setTop(StackMemberOffset, 0);
diff --git a/FEXCore/include/FEXCore/Core/DiskCache.h b/FEXCore/include/FEXCore/Core/DiskCache.h
index 769ada51e..b81ad5302 100644
--- a/FEXCore/include/FEXCore/Core/DiskCache.h
+++ b/FEXCore/include/FEXCore/Core/DiskCache.h
@@ -210,7 +210,7 @@ namespace DiskCache {
 
   // TODO: This header is in global installed header path, but uses internal headers.
   // Migrate this once that is fixed.
-  static constexpr uint16_t FormatVersion = 12;
+  static constexpr uint16_t FormatVersion = 13;
   FEX_DEFAULT_VISIBILITY uint16_t GetFormatVersion();
 
 } // namespace DiskCache
diff --git a/unittests/ASM/FEX_bugs/fxch_tag_word.asm b/unittests/ASM/FEX_bugs/fxch_tag_word.asm
new file mode 100644
index 000000000..b601510bf
--- /dev/null
+++ b/unittests/ASM/FEX_bugs/fxch_tag_word.asm
@@ -0,0 +1,40 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x3",
+    "RBX": "0x81"
+  }
+}
+%endif
+
+; FXCH: empty and empty operands -> mark both valid
+fxrstor [rel .fxsave_data]
+fxch st0, st1
+
+fxsave [rel .save]
+movzx eax, byte [rel .save + 4]
+
+; FXCH: valid and empty operands -> mark both valid
+finit
+fldz
+fxch st0, st1
+
+fxsave [rel .save2]
+movzx ebx, byte [rel .save2 + 4]
+
+hlt
+
+align 16
+.fxsave_data:
+dw 0x037f       ; FCW
+dw 0x0000       ; FSW
+dw 0x0000       ; FTW
+times 506 db 0
+
+align 16
+.save:
+times 64 dq 0
+
+align 16
+.save2:
+times 64 dq 0
diff --git a/unittests/InstructionCountCI/AFP/H0F3A.json b/unittests/InstructionCountCI/AFP/H0F3A.json
index eaf1b7875..5b4612e17 100644
--- a/unittests/InstructionCountCI/AFP/H0F3A.json
+++ b/unittests/InstructionCountCI/AFP/H0F3A.json
@@ -8,7 +8,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "roundss xmm0, xmm1, 00000000b": {
diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json
index 015f0b013..2c5d356f8 100644
--- a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json
+++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json
@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "cvtpi2ps xmm0, [rax]": {
diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json
index 820abc701..8cbdbb996 100644
--- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json
+++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json
@@ -9,7 +9,7 @@
     "DisabledHostFeatures": [
       "RPRES"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "cvtsi2ss xmm0, eax": {
diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json
index fb43e7938..0fb575dc3 100644
--- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json
+++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json
@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "cvtsi2sd xmm0, eax": {
diff --git a/unittests/InstructionCountCI/AFP/Secondary.json b/unittests/InstructionCountCI/AFP/Secondary.json
index d61e25a00..5c06da71e 100644
--- a/unittests/InstructionCountCI/AFP/Secondary.json
+++ b/unittests/InstructionCountCI/AFP/Secondary.json
@@ -8,7 +8,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "cvtpi2ps xmm0, [rax]": {
diff --git a/unittests/InstructionCountCI/AFP/Secondary_REP.json b/unittests/InstructionCountCI/AFP/Secondary_REP.json
index a2fe3dee7..5c7b89661 100644
--- a/unittests/InstructionCountCI/AFP/Secondary_REP.json
+++ b/unittests/InstructionCountCI/AFP/Secondary_REP.json
@@ -9,7 +9,7 @@
       "SVE256",
       "RPRES"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "cvtsi2ss xmm0, eax": {
diff --git a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json
index fad8d967a..3ff904827 100644
--- a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json
+++ b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json
@@ -8,7 +8,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "cvtsi2sd xmm0, eax": {
diff --git a/unittests/InstructionCountCI/AFP/VEX_map1.json b/unittests/InstructionCountCI/AFP/VEX_map1.json
index 4f36705ea..dfea0cfc4 100644
--- a/unittests/InstructionCountCI/AFP/VEX_map1.json
+++ b/unittests/InstructionCountCI/AFP/VEX_map1.json
@@ -9,7 +9,7 @@
     "DisabledHostFeatures": [
       "RPRES"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vsqrtss xmm0, xmm1, xmm2": {
diff --git a/unittests/InstructionCountCI/AFP/VEX_map3.json b/unittests/InstructionCountCI/AFP/VEX_map3.json
index cd35b55fa..c93411f2c 100644
--- a/unittests/InstructionCountCI/AFP/VEX_map3.json
+++ b/unittests/InstructionCountCI/AFP/VEX_map3.json
@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vroundss xmm0, xmm1, 00000000b": {
diff --git a/unittests/InstructionCountCI/AVX128/FMA4.json b/unittests/InstructionCountCI/AVX128/FMA4.json
index 8f37a0c32..b1a829a44 100644
--- a/unittests/InstructionCountCI/AVX128/FMA4.json
+++ b/unittests/InstructionCountCI/AVX128/FMA4.json
@@ -7,7 +7,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vfmaddsubps xmm0, xmm1, xmm2, xmm3": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json
index 79fa504d9..3cb177e3e 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map1.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json
@@ -13,7 +13,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vmovups xmm0, xmm0": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json b/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json
index 62fb8fc16..dfe385eeb 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json
@@ -9,7 +9,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vaddsubpd xmm0, xmm1, xmm2": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json
index 9506c5a20..63715406c 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json
@@ -10,7 +10,7 @@
       "FLAGM2",
       "SVE256"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vmovntps [rax], xmm0": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json
index 901f30ef0..9601af5c3 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json
@@ -10,7 +10,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vucomiss xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json
index 3af5e1c93..1188543eb 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json
@@ -9,7 +9,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vpshufb xmm0, xmm1, xmm2": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json b/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json
index f164a10ec..e95eff5d2 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json
@@ -8,7 +8,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vfmadd132ss xmm0, xmm1, xmm2": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
index 2dfba9fe9..2bc68bc09 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
@@ -10,7 +10,7 @@
       "FLAGM2",
       "SVE256"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vmovntdqa xmm0, [rax]": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
index 596e61825..fbad602a6 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
@@ -11,7 +11,7 @@
       "SVE256",
       "SVEBITPERM"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vtestps xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3.json b/unittests/InstructionCountCI/AVX128/VEX_map3.json
index 7b2346da5..fcf688cd6 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map3.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map3.json
@@ -7,7 +7,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vpermq ymm0, ymm1, 1": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json
index 71a01134f..8f2725abd 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json
@@ -8,7 +8,7 @@
       "AFP",
       "SVE256"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vblendvps xmm0, xmm1, xmm2, xmm3": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map_group.json b/unittests/InstructionCountCI/AVX128/VEX_map_group.json
index b58cd97a4..6074a7931 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map_group.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map_group.json
@@ -9,7 +9,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vpsrlw xmm0, xmm1, 0": {
diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json
index 11b285171..21c575457 100644
--- a/unittests/InstructionCountCI/Atomics.json
+++ b/unittests/InstructionCountCI/Atomics.json
@@ -9,7 +9,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "lock add byte [rax], cl": {
diff --git a/unittests/InstructionCountCI/Crypto/H0F38.json b/unittests/InstructionCountCI/Crypto/H0F38.json
index f6f989c60..e7ea937a2 100644
--- a/unittests/InstructionCountCI/Crypto/H0F38.json
+++ b/unittests/InstructionCountCI/Crypto/H0F38.json
@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "sha1nexte xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json b/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json
index 5f9cac41b..8496071a2 100644
--- a/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json
+++ b/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json
@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "sha1nexte xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json
index 0e7d11b42..71325119d 100644
--- a/unittests/InstructionCountCI/Crypto/H0F3A.json
+++ b/unittests/InstructionCountCI/Crypto/H0F3A.json
@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "pclmulqdq xmm0, xmm1, 00000b": {
diff --git a/unittests/InstructionCountCI/DDD.json b/unittests/InstructionCountCI/DDD.json
index eea195023..626e73935 100644
--- a/unittests/InstructionCountCI/DDD.json
+++ b/unittests/InstructionCountCI/DDD.json
@@ -10,7 +10,7 @@
       "AFP",
       "RPRES"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Comment": [
     "These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers",
diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
index 01b1b7276..0461a99a9 100644
--- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
+++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
@@ -8,7 +8,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Comment": [
     "Instructions that explicitly push against the limits of ARM's loadstore instructions"
diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json
index db3dce566..d35af386b 100644
--- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json
+++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json
@@ -8,7 +8,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Comment": [
     "Instructions that explicitly push against the limits of ARM's loadstore instructions"
diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst.json b/unittests/InstructionCountCI/FEXOpt/MultiInst.json
index 4bb77d82d..39e99f0da 100644
--- a/unittests/InstructionCountCI/FEXOpt/MultiInst.json
+++ b/unittests/InstructionCountCI/FEXOpt/MultiInst.json
@@ -13,7 +13,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"
diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json
index 89c735a5d..d7d4737a8 100644
--- a/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json
+++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json
@@ -11,7 +11,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"
diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json
index 33ef07c46..4488e4bba 100644
--- a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json
+++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json
@@ -9,7 +9,7 @@
       "SVE256",
       "RPRES"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"
diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json
index 323a95bb3..d6b2193b6 100644
--- a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json
+++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json
@@ -14,7 +14,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"
diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json
index cd2b7dfec..4f8b863fe 100644
--- a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json
+++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json
@@ -14,7 +14,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"
diff --git a/unittests/InstructionCountCI/FEXOpt/libnss.json b/unittests/InstructionCountCI/FEXOpt/libnss.json
index 08e522bda..ba3b4f90c 100644
--- a/unittests/InstructionCountCI/FEXOpt/libnss.json
+++ b/unittests/InstructionCountCI/FEXOpt/libnss.json
@@ -12,7 +12,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Comment": [],
   "Instructions": {
diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json
index 5d4f3b9ca..5d914c106 100644
--- a/unittests/InstructionCountCI/FlagM/Atomics.json
+++ b/unittests/InstructionCountCI/FlagM/Atomics.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "lock add byte [rax], cl": {
diff --git a/unittests/InstructionCountCI/FlagM/FlagOpts.json b/unittests/InstructionCountCI/FlagM/FlagOpts.json
index 67b77744c..5c6cab9e9 100644
--- a/unittests/InstructionCountCI/FlagM/FlagOpts.json
+++ b/unittests/InstructionCountCI/FlagM/FlagOpts.json
@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "Chained add": {
diff --git a/unittests/InstructionCountCI/FlagM/H0F38.json b/unittests/InstructionCountCI/FlagM/H0F38.json
index 47d2c9755..e53f9d916 100644
--- a/unittests/InstructionCountCI/FlagM/H0F38.json
+++ b/unittests/InstructionCountCI/FlagM/H0F38.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "ptest xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json
index 34f4818e0..7ed6ccd86 100644
--- a/unittests/InstructionCountCI/FlagM/HotBlocks.json
+++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "The Witcher 3": {
diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
index 660fce59d..3f775d891 100644
--- a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
+++ b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "Sonic Mania movie player": {
diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json
index 7420aafef..52fe76411 100644
--- a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json
+++ b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json
@@ -10,7 +10,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "FMOD scalar loop": {
diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json
index fde8b946d..093f3a26b 100644
--- a/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json
+++ b/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json
@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "The Sims 1 hot block": {
diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json
index e052b88f5..7de9d6883 100644
--- a/unittests/InstructionCountCI/FlagM/Primary.json
+++ b/unittests/InstructionCountCI/FlagM/Primary.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "add bl, cl": {
diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
index f1d394ae9..a9124f1d8 100644
--- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "add al, 1": {
diff --git a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json
index 1f15d522f..a34199c9b 100644
--- a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json
+++ b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "push es": {
diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json
index e4639bf10..596006b5b 100644
--- a/unittests/InstructionCountCI/FlagM/Secondary.json
+++ b/unittests/InstructionCountCI/FlagM/Secondary.json
@@ -11,7 +11,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "ucomiss xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json
index 0845826d0..2800d7a98 100644
--- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json
+++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json
@@ -11,7 +11,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "sgdt [rax]": {
diff --git a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json
index 2b964d815..7ccd5d525 100644
--- a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json
+++ b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json
@@ -11,7 +11,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "xgetbv": {
diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
index 8b09fe5ac..ac46b5d58 100644
--- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
+++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
@@ -11,7 +11,7 @@
       "AFP",
       "FCMA"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "ucomisd xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP.json b/unittests/InstructionCountCI/FlagM/Secondary_REP.json
index 9220a5af4..fa0e12859 100644
--- a/unittests/InstructionCountCI/FlagM/Secondary_REP.json
+++ b/unittests/InstructionCountCI/FlagM/Secondary_REP.json
@@ -12,7 +12,7 @@
       "AFP",
       "CSSC"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "popcnt ax, bx": {
diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json b/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json
index 0c17f33b7..9df1a39a7 100644
--- a/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json
+++ b/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json
@@ -12,7 +12,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "popcnt ax, bx": {
diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json
index 388416560..384f94f11 100644
--- a/unittests/InstructionCountCI/FlagM/VEX_map1.json
+++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json
@@ -12,7 +12,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vucomiss xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/FlagM/VEX_map2.json b/unittests/InstructionCountCI/FlagM/VEX_map2.json
index 4e41be482..314b88026 100644
--- a/unittests/InstructionCountCI/FlagM/VEX_map2.json
+++ b/unittests/InstructionCountCI/FlagM/VEX_map2.json
@@ -10,7 +10,7 @@
       "AFP",
       "SVEBITPERM"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vtestps xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/FlagM/VEX_map_group.json b/unittests/InstructionCountCI/FlagM/VEX_map_group.json
index 8d1dadd04..3de397905 100644
--- a/unittests/InstructionCountCI/FlagM/VEX_map_group.json
+++ b/unittests/InstructionCountCI/FlagM/VEX_map_group.json
@@ -9,7 +9,7 @@
     "DisabledHostFeatures": [
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "blsr eax, ebx": {
diff --git a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json
index 597ba7d84..164932f4d 100644
--- a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json
+++ b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "Block1": {
diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json
index c8d5c71a1..044597c10 100644
--- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json
+++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "Block1": {
diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json
index 70e84fc4c..482455235 100644
--- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json
+++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "Block1": {
diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
index 83b4d1f7d..cd8dd67b9 100644
--- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
+++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "Block1": {
diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json
index 22909fa82..5ccebb052 100644
--- a/unittests/InstructionCountCI/FlagM/x87.json
+++ b/unittests/InstructionCountCI/FlagM/x87.json
@@ -11,7 +11,7 @@
       "CSSC",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "fadd dword [rax]": {
@@ -2364,7 +2364,7 @@
       ]
     },
     "fxch st0, st1": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xc9 /1"
       ],
@@ -2372,17 +2372,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q2, [x21, #1056]",
-        "add w20, w20, #0x1 (1)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr q3, [x20, #1056]",
+        "add w22, w20, #0x1 (1)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr q3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str q3, [x21, #1056]",
-        "str q2, [x20, #1056]"
+        "str q2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x303",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st2": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xca /1"
       ],
@@ -2390,17 +2397,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q2, [x21, #1056]",
-        "add w20, w20, #0x2 (2)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr q3, [x20, #1056]",
+        "add w22, w20, #0x2 (2)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr q3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str q3, [x21, #1056]",
-        "str q2, [x20, #1056]"
+        "str q2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x505",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st3": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcb /1"
       ],
@@ -2408,17 +2422,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q2, [x21, #1056]",
-        "add w20, w20, #0x3 (3)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr q3, [x20, #1056]",
+        "add w22, w20, #0x3 (3)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr q3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str q3, [x21, #1056]",
-        "str q2, [x20, #1056]"
+        "str q2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x909",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st4": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcc /1"
       ],
@@ -2426,17 +2447,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q2, [x21, #1056]",
-        "add w20, w20, #0x4 (4)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr q3, [x20, #1056]",
+        "add w22, w20, #0x4 (4)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr q3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str q3, [x21, #1056]",
-        "str q2, [x20, #1056]"
+        "str q2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x1111",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st5": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcd /1"
       ],
@@ -2444,17 +2472,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q2, [x21, #1056]",
-        "add w20, w20, #0x5 (5)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr q3, [x20, #1056]",
+        "add w22, w20, #0x5 (5)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr q3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str q3, [x21, #1056]",
-        "str q2, [x20, #1056]"
+        "str q2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x2121",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st6": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xce /1"
       ],
@@ -2462,17 +2497,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q2, [x21, #1056]",
-        "add w20, w20, #0x6 (6)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr q3, [x20, #1056]",
+        "add w22, w20, #0x6 (6)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr q3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str q3, [x21, #1056]",
-        "str q2, [x20, #1056]"
+        "str q2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x4141",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st7": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcf /1"
       ],
@@ -2480,13 +2522,20 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q2, [x21, #1056]",
-        "add w20, w20, #0x7 (7)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr q3, [x20, #1056]",
+        "add w22, w20, #0x7 (7)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr q3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str q3, [x21, #1056]",
-        "str q2, [x20, #1056]"
+        "str q2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x8181",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fnop": {
diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json
index 3507dc1ef..1e651a012 100644
--- a/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json
+++ b/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json
@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "Block1": {
diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json
index 55129ee74..da0e99ac3 100644
--- a/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json
+++ b/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json
@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "Block1": {
diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json
index fc22a79ba..9a8b449ec 100644
--- a/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json
+++ b/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json
@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "Block1": {
diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json
index 63f03d772..082e0fc17 100644
--- a/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json
+++ b/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json
@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "Block1": {
diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json
index 75871f70f..287491757 100644
--- a/unittests/InstructionCountCI/FlagM/x87_f64.json
+++ b/unittests/InstructionCountCI/FlagM/x87_f64.json
@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "fadd dword [rax]": {
@@ -1774,7 +1774,7 @@
       ]
     },
     "fxch st0, st1": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xc9 /1"
       ],
@@ -1782,17 +1782,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
-        "add w20, w20, #0x1 (1)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr d3, [x20, #1056]",
+        "add w22, w20, #0x1 (1)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr d3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str d3, [x21, #1056]",
-        "str d2, [x20, #1056]"
+        "str d2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x303",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st2": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xca /1"
       ],
@@ -1800,17 +1807,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
-        "add w20, w20, #0x2 (2)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr d3, [x20, #1056]",
+        "add w22, w20, #0x2 (2)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr d3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str d3, [x21, #1056]",
-        "str d2, [x20, #1056]"
+        "str d2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x505",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st3": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcb /1"
       ],
@@ -1818,17 +1832,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
-        "add w20, w20, #0x3 (3)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr d3, [x20, #1056]",
+        "add w22, w20, #0x3 (3)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr d3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str d3, [x21, #1056]",
-        "str d2, [x20, #1056]"
+        "str d2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x909",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st4": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcc /1"
       ],
@@ -1836,17 +1857,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
-        "add w20, w20, #0x4 (4)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr d3, [x20, #1056]",
+        "add w22, w20, #0x4 (4)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr d3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str d3, [x21, #1056]",
-        "str d2, [x20, #1056]"
+        "str d2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x1111",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st5": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcd /1"
       ],
@@ -1854,17 +1882,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
-        "add w20, w20, #0x5 (5)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr d3, [x20, #1056]",
+        "add w22, w20, #0x5 (5)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr d3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str d3, [x21, #1056]",
-        "str d2, [x20, #1056]"
+        "str d2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x2121",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st6": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xce /1"
       ],
@@ -1872,17 +1907,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
-        "add w20, w20, #0x6 (6)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr d3, [x20, #1056]",
+        "add w22, w20, #0x6 (6)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr d3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str d3, [x21, #1056]",
-        "str d2, [x20, #1056]"
+        "str d2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x4141",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st7": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcf /1"
       ],
@@ -1890,13 +1932,20 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
-        "add w20, w20, #0x7 (7)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr d3, [x20, #1056]",
+        "add w22, w20, #0x7 (7)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr d3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str d3, [x21, #1056]",
-        "str d2, [x20, #1056]"
+        "str d2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x8181",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fnop": {
diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json
index 7770c7947..bb0945f2a 100644
--- a/unittests/InstructionCountCI/H0F38.json
+++ b/unittests/InstructionCountCI/H0F38.json
@@ -10,7 +10,7 @@
       "FLAGM2",
       "CRYPTO"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "pshufb mm0, mm1": {
diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json
index 789628d71..24e2af7cd 100644
--- a/unittests/InstructionCountCI/H0F3A.json
+++ b/unittests/InstructionCountCI/H0F3A.json
@@ -8,7 +8,7 @@
       "AFP",
       "CRYPTO"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Comment": [
     "SSE4.2 string instructions are skipped here.",
diff --git a/unittests/InstructionCountCI/H0F3A_SVE128.json b/unittests/InstructionCountCI/H0F3A_SVE128.json
index 757990df5..33a4d4301 100644
--- a/unittests/InstructionCountCI/H0F3A_SVE128.json
+++ b/unittests/InstructionCountCI/H0F3A_SVE128.json
@@ -8,7 +8,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "dpps xmm0, xmm1, 00000000b": {
diff --git a/unittests/InstructionCountCI/MOPS/Primary.json b/unittests/InstructionCountCI/MOPS/Primary.json
index 82748ed7c..0eac8ae69 100644
--- a/unittests/InstructionCountCI/MOPS/Primary.json
+++ b/unittests/InstructionCountCI/MOPS/Primary.json
@@ -11,7 +11,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "rep movsb": {
diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json
index 3c7acbea8..087ab4856 100644
--- a/unittests/InstructionCountCI/Primary.json
+++ b/unittests/InstructionCountCI/Primary.json
@@ -10,7 +10,7 @@
       "FLAGM2",
       "MOPS"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "add bl, cl": {
diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json
index 11be3eed5..bb425e50f 100644
--- a/unittests/InstructionCountCI/PrimaryGroup.json
+++ b/unittests/InstructionCountCI/PrimaryGroup.json
@@ -9,7 +9,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Comment": [
     "Instructions in this table that are marked optimal don't have their flag calculation part of this assumption",
diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json
index 5c12dd55a..68685683e 100644
--- a/unittests/InstructionCountCI/Primary_32Bit.json
+++ b/unittests/InstructionCountCI/Primary_32Bit.json
@@ -9,7 +9,7 @@
       "FlagM",
       "FlagM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "push es": {
diff --git a/unittests/InstructionCountCI/RPRES/DDD.json b/unittests/InstructionCountCI/RPRES/DDD.json
index 590e08a95..b67d29dad 100644
--- a/unittests/InstructionCountCI/RPRES/DDD.json
+++ b/unittests/InstructionCountCI/RPRES/DDD.json
@@ -9,7 +9,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "pfrcpv mm0, mm1": {
diff --git a/unittests/InstructionCountCI/RPRES/Secondary.json b/unittests/InstructionCountCI/RPRES/Secondary.json
index 3f6ac73a7..daeebf430 100644
--- a/unittests/InstructionCountCI/RPRES/Secondary.json
+++ b/unittests/InstructionCountCI/RPRES/Secondary.json
@@ -9,7 +9,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "rsqrtps xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json
index d99489bc5..48e70bbe6 100644
--- a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json
+++ b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json
@@ -9,7 +9,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "rsqrtss xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json
index 38b122c0c..d1836de15 100644
--- a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json
+++ b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json
@@ -8,7 +8,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vrsqrtps xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Repeat.json b/unittests/InstructionCountCI/Repeat.json
index 06430a415..919b79ac5 100644
--- a/unittests/InstructionCountCI/Repeat.json
+++ b/unittests/InstructionCountCI/Repeat.json
@@ -6,7 +6,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {}
 }
diff --git a/unittests/InstructionCountCI/SSE42_Strings.json b/unittests/InstructionCountCI/SSE42_Strings.json
index ef41577ab..ffcfaaa32 100644
--- a/unittests/InstructionCountCI/SSE42_Strings.json
+++ b/unittests/InstructionCountCI/SSE42_Strings.json
@@ -33,7 +33,7 @@
       "      - 1b: ECX = MSB",
       "[7]   - Reserved"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "pcmpestrm xmm0, xmm1, 0_0_00_00_00b": {
diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json
index 703ffcc13..9c2deda8b 100644
--- a/unittests/InstructionCountCI/Secondary.json
+++ b/unittests/InstructionCountCI/Secondary.json
@@ -12,7 +12,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Comment": [
     "MMX instructions are defined as optimal without SRA being used for these instructions.",
diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json
index 0a48248f7..da4339536 100644
--- a/unittests/InstructionCountCI/SecondaryGroup.json
+++ b/unittests/InstructionCountCI/SecondaryGroup.json
@@ -11,7 +11,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "sgdt [rax]": {
diff --git a/unittests/InstructionCountCI/SecondaryModRM.json b/unittests/InstructionCountCI/SecondaryModRM.json
index dec703b1d..aaaac72bd 100644
--- a/unittests/InstructionCountCI/SecondaryModRM.json
+++ b/unittests/InstructionCountCI/SecondaryModRM.json
@@ -11,7 +11,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "xgetbv": {
diff --git a/unittests/InstructionCountCI/Secondary_32Bit.json b/unittests/InstructionCountCI/Secondary_32Bit.json
index a554d3f37..fdd30d309 100644
--- a/unittests/InstructionCountCI/Secondary_32Bit.json
+++ b/unittests/InstructionCountCI/Secondary_32Bit.json
@@ -7,7 +7,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "push fs": {
diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json
index ed8cd1070..50b9786e6 100644
--- a/unittests/InstructionCountCI/Secondary_OpSize.json
+++ b/unittests/InstructionCountCI/Secondary_OpSize.json
@@ -12,7 +12,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "movupd xmm0, xmm0": {
diff --git a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json
index 9b0cafdfe..9ea47d593 100644
--- a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json
+++ b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json
@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "addsubpd xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json
index ee541339e..d9788ad5a 100644
--- a/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json
+++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json
@@ -8,7 +8,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "psrlw xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json
index f826d11c7..cd78de9b6 100644
--- a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json
+++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json
@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "pmulhuw xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json
index e2a1a1d70..ae95c6160 100644
--- a/unittests/InstructionCountCI/Secondary_REP.json
+++ b/unittests/InstructionCountCI/Secondary_REP.json
@@ -12,7 +12,7 @@
       "FRINTTS",
       "CSSC"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "movss xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json
index 97497ff25..d2e4cc18c 100644
--- a/unittests/InstructionCountCI/Secondary_REPNE.json
+++ b/unittests/InstructionCountCI/Secondary_REPNE.json
@@ -10,7 +10,7 @@
       "FCMA",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "movsd xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json
index f0fe6a9b8..52e64fa38 100644
--- a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json
+++ b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json
@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "addsubps xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json
index 2fe9e2413..ed6ed2315 100644
--- a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json
+++ b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json
@@ -10,7 +10,7 @@
       "FCMA",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "cvtpd2dq xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json b/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json
index 3ee39916a..c2919a0e7 100644
--- a/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json
+++ b/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json
@@ -12,7 +12,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "cvttss2si eax, xmm0": {
diff --git a/unittests/InstructionCountCI/Secondary_SVE128.json b/unittests/InstructionCountCI/Secondary_SVE128.json
index 14a9ca151..248025628 100644
--- a/unittests/InstructionCountCI/Secondary_SVE128.json
+++ b/unittests/InstructionCountCI/Secondary_SVE128.json
@@ -8,7 +8,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "movmskps eax, xmm0": {
diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json
index a6fe25e7e..03ffc7b86 100644
--- a/unittests/InstructionCountCI/VEX_map1.json
+++ b/unittests/InstructionCountCI/VEX_map1.json
@@ -13,7 +13,7 @@
       "FLAGM2",
       "FRINTTS"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vmovups xmm0, xmm0": {
diff --git a/unittests/InstructionCountCI/VEX_map1_FCMA.json b/unittests/InstructionCountCI/VEX_map1_FCMA.json
index 21c24cedd..5734a1155 100644
--- a/unittests/InstructionCountCI/VEX_map1_FCMA.json
+++ b/unittests/InstructionCountCI/VEX_map1_FCMA.json
@@ -8,7 +8,7 @@
       "FCMA"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vaddsubpd xmm0, xmm1, xmm2": {
diff --git a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json
index 0c2efa4e6..f1ebb77c0 100644
--- a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json
+++ b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json
@@ -13,7 +13,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vcvttss2si eax, xmm0": {
diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json
index 888a851fa..8d93db926 100644
--- a/unittests/InstructionCountCI/VEX_map2.json
+++ b/unittests/InstructionCountCI/VEX_map2.json
@@ -11,7 +11,7 @@
       "FLAGM2",
       "SVEBITPERM"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vpshufb xmm0, xmm1, xmm2": {
diff --git a/unittests/InstructionCountCI/VEX_map2_svebitperm.json b/unittests/InstructionCountCI/VEX_map2_svebitperm.json
index f5cd49fab..3f06859d4 100644
--- a/unittests/InstructionCountCI/VEX_map2_svebitperm.json
+++ b/unittests/InstructionCountCI/VEX_map2_svebitperm.json
@@ -11,7 +11,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "pext eax, ebx, ecx": {
diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json
index e1297781d..73cfa837a 100644
--- a/unittests/InstructionCountCI/VEX_map3.json
+++ b/unittests/InstructionCountCI/VEX_map3.json
@@ -8,7 +8,7 @@
     "DisabledHostFeatures": [
       "AFP"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vpermq ymm0, ymm1, 1": {
diff --git a/unittests/InstructionCountCI/VEX_map_group.json b/unittests/InstructionCountCI/VEX_map_group.json
index 047cfca51..4307dc624 100644
--- a/unittests/InstructionCountCI/VEX_map_group.json
+++ b/unittests/InstructionCountCI/VEX_map_group.json
@@ -9,7 +9,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "vpsrlw xmm0, xmm1, 0": {
diff --git a/unittests/InstructionCountCI/X87ldst-SVE.json b/unittests/InstructionCountCI/X87ldst-SVE.json
index 4044b9748..4433fbff8 100644
--- a/unittests/InstructionCountCI/X87ldst-SVE.json
+++ b/unittests/InstructionCountCI/X87ldst-SVE.json
@@ -11,7 +11,7 @@
       "FLAGM2",
       "RPRES"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "fstp tword [rax]": {
diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json
index b52b2e8ca..db8b1b45b 100644
--- a/unittests/InstructionCountCI/x87.json
+++ b/unittests/InstructionCountCI/x87.json
@@ -10,7 +10,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "fadd dword [rax]": {
@@ -2363,7 +2363,7 @@
       ]
     },
     "fxch st0, st1": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xc9 /1"
       ],
@@ -2371,17 +2371,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q2, [x21, #1056]",
-        "add w20, w20, #0x1 (1)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr q3, [x20, #1056]",
+        "add w22, w20, #0x1 (1)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr q3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str q3, [x21, #1056]",
-        "str q2, [x20, #1056]"
+        "str q2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x303",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st2": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xca /1"
       ],
@@ -2389,17 +2396,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q2, [x21, #1056]",
-        "add w20, w20, #0x2 (2)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr q3, [x20, #1056]",
+        "add w22, w20, #0x2 (2)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr q3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str q3, [x21, #1056]",
-        "str q2, [x20, #1056]"
+        "str q2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x505",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st3": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcb /1"
       ],
@@ -2407,17 +2421,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q2, [x21, #1056]",
-        "add w20, w20, #0x3 (3)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr q3, [x20, #1056]",
+        "add w22, w20, #0x3 (3)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr q3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str q3, [x21, #1056]",
-        "str q2, [x20, #1056]"
+        "str q2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x909",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st4": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcc /1"
       ],
@@ -2425,17 +2446,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q2, [x21, #1056]",
-        "add w20, w20, #0x4 (4)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr q3, [x20, #1056]",
+        "add w22, w20, #0x4 (4)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr q3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str q3, [x21, #1056]",
-        "str q2, [x20, #1056]"
+        "str q2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x1111",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st5": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcd /1"
       ],
@@ -2443,17 +2471,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q2, [x21, #1056]",
-        "add w20, w20, #0x5 (5)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr q3, [x20, #1056]",
+        "add w22, w20, #0x5 (5)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr q3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str q3, [x21, #1056]",
-        "str q2, [x20, #1056]"
+        "str q2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x2121",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st6": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xce /1"
       ],
@@ -2461,17 +2496,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q2, [x21, #1056]",
-        "add w20, w20, #0x6 (6)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr q3, [x20, #1056]",
+        "add w22, w20, #0x6 (6)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr q3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str q3, [x21, #1056]",
-        "str q2, [x20, #1056]"
+        "str q2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x4141",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st7": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcf /1"
       ],
@@ -2479,13 +2521,20 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q2, [x21, #1056]",
-        "add w20, w20, #0x7 (7)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr q3, [x20, #1056]",
+        "add w22, w20, #0x7 (7)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr q3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str q3, [x21, #1056]",
-        "str q2, [x20, #1056]"
+        "str q2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x8181",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fnop": {
diff --git a/unittests/InstructionCountCI/x87_32Bit.json b/unittests/InstructionCountCI/x87_32Bit.json
index b485793f5..a43b01521 100644
--- a/unittests/InstructionCountCI/x87_32Bit.json
+++ b/unittests/InstructionCountCI/x87_32Bit.json
@@ -10,7 +10,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "Multiple fld/fst": {
diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json
index f7bf9d4e5..90d218723 100644
--- a/unittests/InstructionCountCI/x87_f64.json
+++ b/unittests/InstructionCountCI/x87_f64.json
@@ -12,7 +12,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "fadd dword [rax]": {
@@ -1791,7 +1791,7 @@
       ]
     },
     "fxch st0, st1": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xc9 /1"
       ],
@@ -1799,17 +1799,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
-        "add w20, w20, #0x1 (1)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr d3, [x20, #1056]",
+        "add w22, w20, #0x1 (1)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr d3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str d3, [x21, #1056]",
-        "str d2, [x20, #1056]"
+        "str d2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x303",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st2": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xca /1"
       ],
@@ -1817,17 +1824,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
-        "add w20, w20, #0x2 (2)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr d3, [x20, #1056]",
+        "add w22, w20, #0x2 (2)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr d3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str d3, [x21, #1056]",
-        "str d2, [x20, #1056]"
+        "str d2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x505",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st3": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcb /1"
       ],
@@ -1835,17 +1849,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
-        "add w20, w20, #0x3 (3)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr d3, [x20, #1056]",
+        "add w22, w20, #0x3 (3)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr d3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str d3, [x21, #1056]",
-        "str d2, [x20, #1056]"
+        "str d2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x909",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st4": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcc /1"
       ],
@@ -1853,17 +1874,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
-        "add w20, w20, #0x4 (4)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr d3, [x20, #1056]",
+        "add w22, w20, #0x4 (4)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr d3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str d3, [x21, #1056]",
-        "str d2, [x20, #1056]"
+        "str d2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x1111",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st5": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcd /1"
       ],
@@ -1871,17 +1899,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
-        "add w20, w20, #0x5 (5)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr d3, [x20, #1056]",
+        "add w22, w20, #0x5 (5)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr d3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str d3, [x21, #1056]",
-        "str d2, [x20, #1056]"
+        "str d2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x2121",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st6": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xce /1"
       ],
@@ -1889,17 +1924,24 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
-        "add w20, w20, #0x6 (6)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr d3, [x20, #1056]",
+        "add w22, w20, #0x6 (6)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr d3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str d3, [x21, #1056]",
-        "str d2, [x20, #1056]"
+        "str d2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x4141",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fxch st0, st7": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 17,
       "Comment": [
         "0xd9 11b 0xcf /1"
       ],
@@ -1907,13 +1949,20 @@
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
-        "add w20, w20, #0x7 (7)",
-        "and w20, w20, #0x7",
-        "add x20, x28, x20, lsl #4",
-        "ldr d3, [x20, #1056]",
+        "add w22, w20, #0x7 (7)",
+        "and w22, w22, #0x7",
+        "add x22, x28, x22, lsl #4",
+        "ldr d3, [x22, #1056]",
         "strb wzr, [x28, #1049]",
         "str d3, [x21, #1056]",
-        "str d2, [x20, #1056]"
+        "str d2, [x22, #1056]",
+        "ldrb w21, [x28, #1202]",
+        "mov w22, #0x8",
+        "sub w20, w22, w20",
+        "mov w22, #0x8181",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1202]"
       ]
     },
     "fnop": {
diff --git a/unittests/InstructionCountCI/x87_f64_32Bit.json b/unittests/InstructionCountCI/x87_f64_32Bit.json
index 0bf193668..3b0d79966 100644
--- a/unittests/InstructionCountCI/x87_f64_32Bit.json
+++ b/unittests/InstructionCountCI/x87_f64_32Bit.json
@@ -15,7 +15,7 @@
       "SVE256",
       "CSSC"
     ],
-    "BinaryCacheVersion": 12
+    "BinaryCacheVersion": 13
   },
   "Instructions": {
     "fstp dword [ebx*4+0x204a20]": {