FEX-Emu--FEX/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json

{
  "Features": {
    "Bitness": 64,
    "EnabledHostFeatures": [
      "AFP",
      "FCMA"
    ],
    "DisabledHostFeatures": [
      "SVE256",
      "SVE128"
    ],
    "BinaryCacheVersion": 13
  },
  "Instructions": {
    "vaddsubpd xmm0, xmm1, xmm2": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "Map 1 0b01 0xd0 128-bit"
      ],
      "ExpectedArm64ASM": [
        "ext v2.16b, v18.16b, v18.16b, #8",
        "fcadd v16.2d, v17.2d, v2.2d, #90",
        "stp xzr, xzr, [x28, #192]"
      ]
    },
    "vaddsubpd ymm0, ymm0, ymm2": {
      "ExpectedInstructionCount": 7,
      "Comment": [
        "Aliasing source and destination",
        "Map 1 0b01 0xd0 256-bit"
      ],
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #192]",
        "ldr q3, [x28, #224]",
        "ext v4.16b, v18.16b, v18.16b, #8",
        "fcadd v16.2d, v16.2d, v4.2d, #90",
        "ext v3.16b, v3.16b, v3.16b, #8",
        "fcadd v2.2d, v2.2d, v3.2d, #90",
        "str q2, [x28, #192]"
      ]
    },
    "vaddsubpd ymm0, ymm1, ymm0": {
      "ExpectedInstructionCount": 7,
      "Comment": [
        "Aliasing source and destination",
        "Map 1 0b01 0xd0 256-bit"
      ],
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #208]",
        "ldr q3, [x28, #192]",
        "ext v4.16b, v16.16b, v16.16b, #8",
        "fcadd v16.2d, v17.2d, v4.2d, #90",
        "ext v3.16b, v3.16b, v3.16b, #8",
        "fcadd v2.2d, v2.2d, v3.2d, #90",
        "str q2, [x28, #192]"
      ]
    },
    "vaddsubpd ymm0, ymm1, ymm2": {
      "ExpectedInstructionCount": 7,
      "Comment": [
        "Map 1 0b01 0xd0 256-bit"
      ],
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #208]",
        "ldr q3, [x28, #224]",
        "ext v4.16b, v18.16b, v18.16b, #8",
        "fcadd v16.2d, v17.2d, v4.2d, #90",
        "ext v3.16b, v3.16b, v3.16b, #8",
        "fcadd v2.2d, v2.2d, v3.2d, #90",
        "str q2, [x28, #192]"
      ]
    },
    "vaddsubps xmm0, xmm1, xmm2": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "Map 1 0b11 0xd0 128-bit"
      ],
      "ExpectedArm64ASM": [
        "rev64 v2.4s, v18.4s",
        "fcadd v16.4s, v17.4s, v2.4s, #90",
        "stp xzr, xzr, [x28, #192]"
      ]
    },
    "vaddsubps ymm0, ymm1, ymm0": {
      "ExpectedInstructionCount": 7,
      "Comment": [
        "Aliasing source and destination",
        "Map 1 0b11 0xd0 256-bit"
      ],
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #208]",
        "ldr q3, [x28, #192]",
        "rev64 v4.4s, v16.4s",
        "fcadd v16.4s, v17.4s, v4.4s, #90",
        "rev64 v3.4s, v3.4s",
        "fcadd v2.4s, v2.4s, v3.4s, #90",
        "str q2, [x28, #192]"
      ]
    },
    "vaddsubps ymm0, ymm0, ymm2": {
      "ExpectedInstructionCount": 7,
      "Comment": [
        "Aliasing source and destination",
        "Map 1 0b11 0xd0 256-bit"
      ],
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #192]",
        "ldr q3, [x28, #224]",
        "rev64 v4.4s, v18.4s",
        "fcadd v16.4s, v16.4s, v4.4s, #90",
        "rev64 v3.4s, v3.4s",
        "fcadd v2.4s, v2.4s, v3.4s, #90",
        "str q2, [x28, #192]"
      ]
    },
    "vaddsubps ymm0, ymm1, ymm2": {
      "ExpectedInstructionCount": 7,
      "Comment": [
        "Map 1 0b11 0xd0 256-bit"
      ],
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #208]",
        "ldr q3, [x28, #224]",
        "rev64 v4.4s, v18.4s",
        "fcadd v16.4s, v17.4s, v4.4s, #90",
        "rev64 v3.4s, v3.4s",
        "fcadd v2.4s, v2.4s, v3.4s, #90",
        "str q2, [x28, #192]"
      ]
    }
  }
}