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Code Issues Packages Projects Releases 66 Wiki Activity
14,977 Commits 11 Branches 70 Tags
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2360 Commits
Author SHA1 Message Date
Pierre-Loup A. Griffais 0d3a5f96f0 InstcountCI: Update 2026-08-30 17:17:54 -07:00
Ryan Houdek b695c5ae11 InstCountCI: Update 
Only adds DiskCache version to json to ensure it's tracked. No asm
changes here.
 2026-08-30 14:26:45 -07:00
LC 62c9c130c4 Merge pull request #5864 from simon902/pf2id_saturation 
Fix pf2id overflow saturation
 2026-08-27 09:16:04 -04:00
LC fca23d88c3 Merge pull request #5863 from simon902/vfaddp-mmx-width 
Fix PFACC producing wrong results due to missing MMX-sized path in VFAddP
 2026-08-27 09:15:30 -04:00
Simon Scherer fe17c447d9 InstcountCI: Update 2026-08-27 11:50:52 +02:00
Simon Scherer 926a871dd4 unittests/ASM: Test pf2id overflow saturation 2026-08-27 11:40:20 +02:00
Simon Scherer 79ef5031eb InstcountCI: Update 2026-08-27 10:36:31 +02:00
Simon Scherer 566b25a35b unittests/ASM: Test pfacc simple addition 2026-08-27 10:33:05 +02:00
Simon Scherer e6748ea1ed InstcountCI: Update 2026-08-27 09:36:28 +02:00
Simon Scherer cac8785aca unittests/ASM: Test pf2iw with values falling outside of 16-bit range 2026-08-27 09:29:40 +02:00
Ryan Houdek 485f1c6acf InstcountCI: Update 2026-08-25 15:18:17 -07:00
Ryan Houdek 6646a5cc72 OpcodeDispatcher: Fixes SHLD by 16 behaviour 
We were assuming that SHLD undefined behaviour matches SHL, but the
specification actually changes a `ge` comparison to `gt`, which means a
shift of 16 isn't UB!

Thanks to the impeccable @OFFTKP in #5842 for bringing this up as it took a bit
for me to figure out what was actually wrong here. I modified their
unittest to cover more just to ensure we don't break it.
 2026-08-25 15:15:36 -07:00
Ryan Houdek 2a76d3b153 Merge pull request #5809 from simon902/fcomi_flag_zero 
FCOMI fails to clear OF, SF, AF
 2026-08-25 13:22:28 -07:00
Ryan Houdek 8d69852785 unittests/FEXLinuxTests: Fixes race condition in signal_sra_state 
This was using a one second alarm which could catch the JIT while it is
still busy. Instead wait for it to let an alarm thread that it is ready,
then tgkill the thread. This removes the race that this was hitting.
 2026-08-24 19:02:39 -07:00
Paris Oplopoios 635befb4c8 FEXCore: Fix CF calculation for BLSMSK and BLSR for 32-bit operands 2026-08-22 15:47:50 +03:00
Paris Oplopoios a69daa2524 unittests/ASM: Test BLSR/BLSMSK CF flag 2026-08-22 15:34:13 +03:00
Ryan Houdek 492dac719f unittests: Disable siglongjmp_branch_invalid on 32-bit 
This test is trying to execute "invalid" code from the last two pages of
the address space to the first two pages of the address space. But
failed to noticed that the last two pages of the 32-bit x86 address
space are actually valid, usually containing VDSO things.
 2026-08-17 18:22:03 -07:00
Ryan Houdek 9377bac5e7 Merge pull request #5825 from javelina-pkwy/fix/siglongjmp-deadlock 
FEXCore: prevent deadlock when branching to MAX_UINT64
 2026-08-17 17:55:39 -07:00
Ryan Houdek a3d609ebb1 Merge pull request #5820 from javelina-pkwy/lea-reg-reg 
Decoder: fix illegal LEA encoding
 2026-08-17 09:58:47 -07:00
Justin Becker 6f29dfcbb8 Probe before taking lock in Compile*() 2026-08-13 16:53:05 -07:00
Justin Becker c156498c5c Add 16 bit and 32 bit variants 2026-08-11 16:19:49 -07:00
Paris Oplopoios f4e362c477 unittests/ASM: Ensure ffreep always has an operand 2026-08-09 16:46:13 +03:00
Simon Scherer 6284c39eb3 InstcountCI: Update 2026-08-06 16:31:49 +02:00
Simon Scherer 015beff4cc unittests/ASM: Test OF,SF,AF flags for fcomi 2026-08-06 16:14:27 +02:00
Simon Scherer 4844729e93 unittests/ASM: Test lossy precision non-SVE path in Vector_F64ToI32 2026-08-05 13:13:04 +02:00
Iaying 7629323548 Fix an XMM register bug in SpillSRA, along with adding a test that reproduces the bug 2026-08-03 15:15:41 -07:00
Justin Becker 34a87cc94c Decoder: fix illegal LEA encoding 2026-07-27 15:48:35 -07:00
Ryan Houdek 27315e33ab Merge pull request #5784 from FrontMage/fix/instruction-fetch-fault-priority 
Frontend: Prioritize instruction fetch faults
 2026-07-27 12:54:53 -07:00
FrontMage 151b4d4c2d Frontend: Prioritize instruction fetch faults 2026-07-25 09:01:21 +08:00
Paris Oplopoios 86c20d0519 Extend FIST tests to check for indefinite value 2026-07-24 17:04:10 +03:00
FrontMage fcf9fd77d7 FEXCore: Isolate multiblock error state per block 2026-07-23 16:52:19 +08:00
Ryan Houdek f73b93dbc2 InstcountCI: Update 2026-07-17 13:17:39 -07:00
Ryan Houdek f129ca0c61 unittests/vmovmskpd: Extend test to have different lower and upper results between 128-bit lanes. 2026-07-17 13:12:27 -07:00
moonfloww 7189e1e280 InstcountCI: Update 2026-07-16 14:44:04 +02:00
LC ba8b0afe7a VectorOps: Use unpredicated shifts where applicable for 256-bit scalar shifts 
Lets us trim some output
 2026-07-15 09:10:57 -04:00
LC 98d45a6a9b VectorOps: Make use of unpredicated immediate shifts 
Same behavior, just without introducing a predicate register dependency.
 2026-07-15 08:00:58 -04:00
LC 4afa49824e StringUtils: Handle strings entirely composed of whitespace in trims 
Previously this wouldn't handle fully whitespaced strings.
 2026-07-13 17:37:09 -04:00
LC 842e22915c VectorOps: Simplify SVE 256-bit VOrn with BSL2N 
Lets us shave off an instruction and also avoid using a temporary
register in some cases. We can also tweak our worst case that requires a
predicate to eliminate the temporary as well.

We can also expand our cmpps cases, so that we can reflect the
BSL2N usages in instcountci.
 2026-07-13 12:27:54 -04:00
LC 9d3c388664 Crypto: Make use of XAR in SHA1NEXTE when available 
Lets us shave an instruction off on hardware that supports XAR.

Closes #5730
 2026-07-12 16:02:12 -04:00
LC 613e9ef701 MiscOps: Fix round mode clearing for RP/RM modes in PushRoundingMode 
Previously this had the potential to not clear rounding bits properly
depending on incoming FPCR state.
 2026-07-11 10:24:07 -04:00
LC b5660c8a92 MiscOps: Avoid stack misalignment in ProcessorID 
This needs to be an add.
 2026-07-10 05:41:54 -04:00
Ryan Houdek 3370d9af15 Merge pull request #5670 from simon902/MOVDoverride 
Fix movd when prefixed with 0x66
 2026-07-09 13:02:08 -07:00
Ryan Houdek 9306de79ad Merge pull request #5667 from simon902/CVTTSS2SIOverride 
Fix cvttss2si when prefixed with 0x66
 2026-07-09 12:52:00 -07:00
Ryan Houdek ff7a54add8 Merge pull request #5668 from OFFTKP/inf 
Fix element getting overwritten in 66_5B test
 2026-07-09 12:26:46 -07:00
Ryan Houdek c3d1157696 Merge pull request #5669 from OFFTKP/lzcnt 
Fix LZCNT tests reading out of bounds
 2026-07-09 12:24:43 -07:00
LC 9b7c9f0fb6 Vector: Trim one instruction off insertq 
We can fold a bitwise not and and pair into a bic
 2026-07-09 14:58:04 -04:00
Simon Scherer c06468025c unittests/ASM: Test movd prefixed with 0x66 2026-07-09 11:46:10 +02:00
Paris Oplopoios 148e539025 Fix LZCNT tests reading out of bounds 2026-07-09 12:36:18 +03:00
Paris Oplopoios 92b96ff30d Fix element getting overwritten in 66_5B test 2026-07-09 11:54:38 +03:00
Simon Scherer 778df0c93b unittests/ASM: Test cvttss2si prefixed with 0x66 2026-07-09 09:24:59 +02:00