Simon Scherer
96d65cd6bc
InstcountCI: Update
2026-09-04 08:30:03 +02:00
Simon Scherer
fd64ea54fe
InstcountCI: Update
2026-09-04 07:32:09 +02:00
Simon Scherer
30e4650a8b
InstcountCI: Update
2026-09-03 08:32:59 +02:00
Ryan Houdek
fbf5187794
InstcountCI: Update
2026-09-02 18:35:36 -07:00
Ryan Houdek
20e9e2044e
InstcountCI: Update
2026-09-02 17:15:36 -07:00
Justin Becker
3471ca67c4
Bump DiskCache version number
2026-09-02 16:40:17 -07:00
Simon Scherer
bce8b13366
InstcountCI: Update
2026-09-02 07:47:24 +02:00
Pierre-Loup A. Griffais
c01bfcd52f
InstcountCI: Update
2026-09-01 03:51:12 -07:00
Ryan Houdek
1558a2c65d
InstcountCI: Update
2026-08-31 19:23:20 -07:00
Pierre-Loup A. Griffais
0d3a5f96f0
InstcountCI: Update
2026-08-30 17:17:54 -07:00
Ryan Houdek
b695c5ae11
InstCountCI: Update
...
Only adds DiskCache version to json to ensure it's tracked. No asm
changes here.
2026-08-30 14:26:45 -07:00
Ryan Houdek
5875a121db
InstcountCI: Update for alignment change
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NFC but touches everything.
2026-02-21 15:24:13 -08:00
Ryan Houdek
11946ffc4c
InstcountCI: Update
2025-10-24 11:11:54 -07:00
Alyssa Rosenzweig
c971d4044f
InstCountCI: Update
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2025-03-27 11:06:57 -04:00
Alyssa Rosenzweig
d935d25f0c
InstCountCI: Update
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-08-21 11:48:03 -04:00
Alyssa Rosenzweig
a299d6b1a5
InstCountCI: Update
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-08-20 20:17:06 -04:00
Alyssa Rosenzweig
75644b33df
InstCountCI: Update
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-08-20 18:36:50 -04:00
Alyssa Rosenzweig
65a4de221b
InstructionCountCI: add AddressingLimitations for AVX
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig
d78b0ea435
InstCountCI: Update
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-07-11 13:21:14 -04:00
Ryan Houdek
2d617ad173
InstcountCI: Update
2024-07-02 20:24:58 -07:00
Alyssa Rosenzweig
1b496cda8f
InstCountCI: Update
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-06-26 14:49:58 -04:00
Alyssa Rosenzweig
a474f86ea8
InstCountCI: add segment register cases
...
add a bit of coverage for this funny addressing corner. We do handle this
optimally but I had to write this to check ;)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-06-20 11:37:35 -04:00
Alyssa Rosenzweig
f5625093bb
InstCountCI: Update
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
2024-06-01 09:42:50 -04:00
Ryan Houdek
1226069b4c
InstCountCI: Update for fixes
...
Only prefetch hit currently since ConstProp is limited to optimizing the
ADD IROp atm.
2024-05-29 04:42:40 -07:00
Ryan Houdek
95919a1ddf
InstcountCI: Add addressing limit tests for base + offset<<shift
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These need to be tested.
2024-05-29 04:28:24 -07:00
Ryan Houdek
ba7b69eea2
InstCountCI: Adds prefetch addressing limits
2024-03-12 21:38:28 -07:00
Ryan Houdek
da263834f8
InstcountCI: Adds addressing limitations to instcountci
...
Spurred on by #3421
This does a bunch of GPR and vector loads to showcase addressing
limitations between ARM and x86.
Tests:
- 8/16/32/64-bit GPR loads
- Both 32-bit and 64-bit addressing modes
- 32/64/128-bit Vector loads
- Both 32-bit and 64-bit addressing modes
- Duplicate the tests for 32-bit addressing mode with a 32-bit process
- Since it should change behaviour.
Untested:
- 8/16-bit vector loadstores since those don't exist on x86
- 16-bit x87 integer load exists but that doesn't go through a vector
load in FEX.
2024-02-21 16:50:00 -08:00
Simon Scherer