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InstructionCountCI: add AddressingLimitations for AVX

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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Alyssa Rosenzweig committed 2024-08-20 18:31:19 -04:00
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commit 65a4de221b
1 file changed
+98
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unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
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@@ -1052,6 +1052,104 @@
"ldr x20, [x28, #960]",
"ldur x7, [x20, #20]"
]
},
"vmovdqu ymm7,yword [rsi+0x60]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"ldr q23, [x10, #96]",
"ldr q2, [x10, #112]",
"str q2, [x28, #128]"
]
},
"vmovdqu ymm7,yword [rsi+0x120]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"ldr q23, [x10, #288]",
"ldr q2, [x10, #304]",
"str q2, [x28, #128]"
]
},
"vmovdqu ymm7,yword [rsi-0x60]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"ldur q23, [x10, #-96]",
"ldur q2, [x10, #-80]",
"str q2, [x28, #128]"
]
},
"vmovdqu ymm7,yword [rsi-0x400]": {
"ExpectedInstructionCount": 5,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffc00",
"ldr q23, [x10, x20, sxtx]",
"mov x20, #0xfffffffffffffc10",
"ldr q2, [x10, x20, sxtx]",
"str q2, [x28, #128]"
]
},
"vmovdqu ymm7,yword [rsi-0x420]": {
"ExpectedInstructionCount": 5,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffbe0",
"ldr q23, [x10, x20, sxtx]",
"mov x20, #0xfffffffffffffbf0",
"ldr q2, [x10, x20, sxtx]",
"str q2, [x28, #128]"
]
},
"vmovdqu ymm7,yword [rsi+0x3d0]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"ldr q23, [x10, #976]",
"ldr q2, [x10, #992]",
"str q2, [x28, #128]"
]
},
"vmovdqu ymm7,yword [rsi+0x400]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"ldr q23, [x10, #1024]",
"ldr q2, [x10, #1040]",
"str q2, [x28, #128]"
]
},
"vmovdqa yword [rcx+0x60],ymm1": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q17, [x5, #96]",
"str q2, [x5, #112]"
]
},
"vmovdqa yword [rcx+0x3d0],ymm1": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q17, [x5, #976]",
"str q2, [x5, #992]"
]
},
"vmovdqa yword [rcx-0x3d0],ymm1": {
"ExpectedInstructionCount": 5,
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"mov x20, #0xfffffffffffffc30",
"str q17, [x5, x20, sxtx]",
"mov x20, #0xfffffffffffffc40",
"str q2, [x5, x20, sxtx]"
]
},
"vmovdqa yword [rcx+rsi-0x3d0],ymm1": {
"ExpectedInstructionCount": 7,
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"add x20, x5, x10",
"mov x21, #0xfffffffffffffc30",
"str q17, [x20, x21, sxtx]",
"add x20, x5, x10",
"mov x21, #0xfffffffffffffc40",
"str q2, [x20, x21, sxtx]"
]
}
}
}