From 65a4de221b156a8869901bdc85fb800dc9e3fb58 Mon Sep 17 00:00:00 2001
From: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Date: Mon, 19 Aug 2024 19:52:56 -0400
Subject: [PATCH] InstructionCountCI: add AddressingLimitations for AVX

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
---
 .../FEXOpt/AddressingLimitations.json         | 98 +++++++++++++++++++
 1 file changed, 98 insertions(+)

diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
index 8c0f0fef9..ff054043d 100644
--- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
+++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
@@ -1052,6 +1052,104 @@
         "ldr x20, [x28, #960]",
         "ldur x7, [x20, #20]"
       ]
+    },
+    "vmovdqu ymm7,yword [rsi+0x60]": {
+      "ExpectedInstructionCount": 3,
+      "ExpectedArm64ASM": [
+        "ldr q23, [x10, #96]",
+        "ldr q2, [x10, #112]",
+        "str q2, [x28, #128]"
+      ]
+    },
+    "vmovdqu ymm7,yword [rsi+0x120]": {
+      "ExpectedInstructionCount": 3,
+      "ExpectedArm64ASM": [
+        "ldr q23, [x10, #288]",
+        "ldr q2, [x10, #304]",
+        "str q2, [x28, #128]"
+      ]
+    },
+    "vmovdqu ymm7,yword [rsi-0x60]": {
+      "ExpectedInstructionCount": 3,
+      "ExpectedArm64ASM": [
+        "ldur q23, [x10, #-96]",
+        "ldur q2, [x10, #-80]",
+        "str q2, [x28, #128]"
+      ]
+    },
+    "vmovdqu ymm7,yword [rsi-0x400]": {
+      "ExpectedInstructionCount": 5,
+      "ExpectedArm64ASM": [
+        "mov x20, #0xfffffffffffffc00",
+        "ldr q23, [x10, x20, sxtx]",
+        "mov x20, #0xfffffffffffffc10",
+        "ldr q2, [x10, x20, sxtx]",
+        "str q2, [x28, #128]"
+      ]
+    },
+    "vmovdqu ymm7,yword [rsi-0x420]": {
+      "ExpectedInstructionCount": 5,
+      "ExpectedArm64ASM": [
+        "mov x20, #0xfffffffffffffbe0",
+        "ldr q23, [x10, x20, sxtx]",
+        "mov x20, #0xfffffffffffffbf0",
+        "ldr q2, [x10, x20, sxtx]",
+        "str q2, [x28, #128]"
+      ]
+    },
+    "vmovdqu ymm7,yword [rsi+0x3d0]": {
+      "ExpectedInstructionCount": 3,
+      "ExpectedArm64ASM": [
+        "ldr q23, [x10, #976]",
+        "ldr q2, [x10, #992]",
+        "str q2, [x28, #128]"
+      ]
+    },
+    "vmovdqu ymm7,yword [rsi+0x400]": {
+      "ExpectedInstructionCount": 3,
+      "ExpectedArm64ASM": [
+        "ldr q23, [x10, #1024]",
+        "ldr q2, [x10, #1040]",
+        "str q2, [x28, #128]"
+      ]
+    },
+    "vmovdqa yword [rcx+0x60],ymm1": {
+      "ExpectedInstructionCount": 3,
+      "ExpectedArm64ASM": [
+        "ldr q2, [x28, #32]",
+        "str q17, [x5, #96]",
+        "str q2, [x5, #112]"
+      ]
+    },
+    "vmovdqa yword [rcx+0x3d0],ymm1": {
+      "ExpectedInstructionCount": 3,
+      "ExpectedArm64ASM": [
+        "ldr q2, [x28, #32]",
+        "str q17, [x5, #976]",
+        "str q2, [x5, #992]"
+      ]
+    },
+    "vmovdqa yword [rcx-0x3d0],ymm1": {
+      "ExpectedInstructionCount": 5,
+      "ExpectedArm64ASM": [
+        "ldr q2, [x28, #32]",
+        "mov x20, #0xfffffffffffffc30",
+        "str q17, [x5, x20, sxtx]",
+        "mov x20, #0xfffffffffffffc40",
+        "str q2, [x5, x20, sxtx]"
+      ]
+    },
+    "vmovdqa yword [rcx+rsi-0x3d0],ymm1": {
+      "ExpectedInstructionCount": 7,
+      "ExpectedArm64ASM": [
+        "ldr q2, [x28, #32]",
+        "add x20, x5, x10",
+        "mov x21, #0xfffffffffffffc30",
+        "str q17, [x20, x21, sxtx]",
+        "add x20, x5, x10",
+        "mov x21, #0xfffffffffffffc40",
+        "str q2, [x20, x21, sxtx]"
+      ]
     }
   }
 }