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InstcountCI: Update

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Ryan Houdek committed 2025-10-24 11:11:54 -07:00
1 parent f44cd9c545
commit 11946ffc4c
52 files changed
+29116 -29116
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unittests/InstructionCountCI/AFP/SVE256/Secondary.json
+3 -3
View File
@@ -27,10 +27,10 @@
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"scvtf v0.2s, v2.2s",
"ptrue p0.d, vl1",
"mov z16.d, p0/m, z0.d"
unittests/InstructionCountCI/AFP/Secondary.json
+3 -3
View File
@@ -27,10 +27,10 @@
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"scvtf v0.2s, v2.2s",
"mov v16.d[0], v0.d[0]"
]
unittests/InstructionCountCI/AVX128/FMA4.json
+60 -60
View File
@@ -18,8 +18,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -32,8 +32,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -46,8 +46,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -60,8 +60,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -74,8 +74,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -88,8 +88,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -102,8 +102,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -116,8 +116,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -130,8 +130,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -144,8 +144,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -158,8 +158,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -172,8 +172,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -186,8 +186,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -200,8 +200,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -214,8 +214,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -228,8 +228,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -242,8 +242,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -256,8 +256,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -270,8 +270,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -284,8 +284,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -298,8 +298,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -312,8 +312,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -326,8 +326,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -340,8 +340,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -354,8 +354,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -368,8 +368,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -382,8 +382,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -396,8 +396,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -410,8 +410,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
},
@@ -424,8 +424,8 @@
"mov w20, #0x10000",
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1472]",
"ldr x0, [x28, #2864]",
"str x1, [x28, #1488]",
"ldr x0, [x28, #2880]",
"br x0"
]
}
unittests/InstructionCountCI/AVX128/VEX_map1.json
+24 -24
View File
@@ -1122,7 +1122,7 @@
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2624]",
"ldr x0, [x28, #2640]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1134,7 +1134,7 @@
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2624]",
"ldr x0, [x28, #2640]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1146,7 +1146,7 @@
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2624]",
"ldr x0, [x28, #2640]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1171,7 +1171,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2624]",
"ldr x0, [x28, #2640]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1185,7 +1185,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2624]",
"ldr x0, [x28, #2640]",
"ldr q3, [x0, #32]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1199,7 +1199,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2624]",
"ldr x0, [x28, #2640]",
"ldr q3, [x0, #48]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1223,7 +1223,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2616]",
"ldr x0, [x28, #2632]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1235,7 +1235,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2616]",
"ldr x0, [x28, #2632]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1247,7 +1247,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2616]",
"ldr x0, [x28, #2632]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1274,7 +1274,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2616]",
"ldr x0, [x28, #2632]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1288,7 +1288,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2616]",
"ldr x0, [x28, #2632]",
"ldr q3, [x0, #32]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1302,7 +1302,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2616]",
"ldr x0, [x28, #2632]",
"ldr q3, [x0, #48]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1326,7 +1326,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2608]",
"ldr x0, [x28, #2624]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1338,7 +1338,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2608]",
"ldr x0, [x28, #2624]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1350,7 +1350,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2608]",
"ldr x0, [x28, #2624]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1377,7 +1377,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2608]",
"ldr x0, [x28, #2624]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1391,7 +1391,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2608]",
"ldr x0, [x28, #2624]",
"ldr q3, [x0, #32]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1405,7 +1405,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2608]",
"ldr x0, [x28, #2624]",
"ldr q3, [x0, #48]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -2288,7 +2288,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2632]",
"ldr x0, [x28, #2648]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -2302,7 +2302,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #64]",
"ldr x0, [x28, #2632]",
"ldr x0, [x28, #2648]",
"ldr q4, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2315,7 +2315,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2632]",
"ldr x0, [x28, #2648]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -2329,7 +2329,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #64]",
"ldr x0, [x28, #2632]",
"ldr x0, [x28, #2648]",
"ldr q4, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2342,7 +2342,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2632]",
"ldr x0, [x28, #2648]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -2356,7 +2356,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #64]",
"ldr x0, [x28, #2632]",
"ldr x0, [x28, #2648]",
"ldr q4, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
unittests/InstructionCountCI/Crypto/H0F38.json
+1 -1
View File
@@ -31,7 +31,7 @@
"0x66 0x0f 0x38 0xca"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2624]",
"ldr x0, [x28, #2640]",
"ldr q2, [x0, #432]",
"tbl v3.16b, {v16.16b}, v2.16b",
"tbl v4.16b, {v17.16b}, v2.16b",
unittests/InstructionCountCI/Crypto/H0F3A.json
+4 -4
View File
@@ -86,7 +86,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #3488]",
"movi v3.2d, #0x0",
"ldr x0, [x28, #2624]",
"ldr x0, [x28, #2640]",
"ldr q4, [x0, #432]",
"tbl v5.16b, {v16.16b}, v4.16b",
"tbl v6.16b, {v17.16b}, v4.16b",
@@ -103,7 +103,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #3504]",
"movi v3.2d, #0x0",
"ldr x0, [x28, #2624]",
"ldr x0, [x28, #2640]",
"ldr q4, [x0, #432]",
"tbl v5.16b, {v16.16b}, v4.16b",
"tbl v6.16b, {v17.16b}, v4.16b",
@@ -120,7 +120,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #3520]",
"movi v3.2d, #0x0",
"ldr x0, [x28, #2624]",
"ldr x0, [x28, #2640]",
"ldr q4, [x0, #432]",
"tbl v5.16b, {v16.16b}, v4.16b",
"tbl v6.16b, {v17.16b}, v4.16b",
@@ -137,7 +137,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #3536]",
"movi v3.2d, #0x0",
"ldr x0, [x28, #2624]",
"ldr x0, [x28, #2640]",
"ldr q4, [x0, #432]",
"tbl v5.16b, {v16.16b}, v4.16b",
"tbl v6.16b, {v17.16b}, v4.16b",
unittests/InstructionCountCI/DDD.json
+138 -138
View File
@@ -23,15 +23,15 @@
"0x0f 0x0f 0x0c"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"uzp1 v2.4h, v2.4h, v2.4h",
"sxtl v2.4s, v2.4h",
"scvtf v2.2s, v2.2s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pi2fd mm0, mm1": {
@@ -40,13 +40,13 @@
"0x0f 0x0f 0x0d"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"scvtf v2.2s, v2.2s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pf2iw mm0, mm1": {
@@ -55,15 +55,15 @@
"0x0f 0x0f 0x1c"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"fcvtzs v2.2s, v2.2s",
"uzp1 v2.4h, v2.4h, v2.4h",
"sxtl v2.4s, v2.4h",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pf2id mm0, mm1": {
@@ -72,14 +72,14 @@
"0x0f 0x0f 0x1d"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"frint32z v2.4s, v2.4s",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrcpv mm0, mm1": {
@@ -88,14 +88,14 @@
"0x0f 0x0f 0x86"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"fmov v0.4s, #0x70 (1.0000)",
"fdiv v2.4s, v0.4s, v2.4s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrsqrtv mm0, mm1": {
@@ -104,80 +104,80 @@
"0x0f 0x0f 0x87"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"fabs v3.4s, v2.4s",
"fmov v0.4s, #0x70 (1.0000)",
"fsqrt v1.4s, v3.4s",
"fdiv v3.4s, v0.4s, v1.4s",
"movi v0.2s, #0x80, lsl #24",
"bit v3.8b, v2.8b, v0.8b",
"str d3, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d3, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfnacc mm0, mm1": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0x0f 0x8a",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"uzp1 v4.2s, v2.2s, v3.2s",
"uzp2 v2.2s, v2.2s, v3.2s",
"fsub v2.4s, v4.4s, v2.4s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfpnacc mm0, mm1": {
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0x0f 0x8e",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"dup v4.2s, v2.s[1]",
"fsub s2, s2, s4",
"faddp v3.4s, v3.4s, v3.4s",
"mov v2.s[1], v3.s[0]",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfcmpge mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0x90",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fcmge v2.4s, v3.4s, v2.4s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfmin mm0, mm1": {
"ExpectedInstructionCount": 9,
"Comment": "0x0f 0x0f 0x94",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fcmgt v0.4s, v2.4s, v3.4s",
"bif v3.16b, v2.16b, v0.16b",
"str d3, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d3, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrcp mm0, mm1": {
@@ -186,15 +186,15 @@
"0x0f 0x0f 0x96"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"fmov s0, #0x70 (1.0000)",
"fdiv s2, s0, s2",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrsqrt mm0, mm1": {
@@ -203,10 +203,10 @@
"0x0f 0x0f 0x97"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"fabs v3.4s, v2.4s",
"fmov v0.4s, #0x70 (1.0000)",
"fsqrt v1.4s, v3.4s",
@@ -214,77 +214,77 @@
"movi v0.2s, #0x80, lsl #24",
"bit v3.8b, v2.8b, v0.8b",
"dup v2.2s, v3.s[0]",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfsub mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0x9a",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fsub v2.4s, v3.4s, v2.4s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfadd mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0x9e",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fadd v2.4s, v3.4s, v2.4s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfcmpgt mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0xa0",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fcmgt v2.4s, v3.4s, v2.4s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfmax mm0, mm1": {
"ExpectedInstructionCount": 9,
"Comment": "0x0f 0x0f 0xa4",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fcmgt v0.4s, v2.4s, v3.4s",
"bit v3.16b, v2.16b, v0.16b",
"str d3, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d3, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrcpit1 mm0, mm1": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x0f 0xa6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrcpit1 mm0, mm0": {
@@ -296,12 +296,12 @@
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x0f 0xa7",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrsqit1 mm0, mm0": {
@@ -313,54 +313,54 @@
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0xaa",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fsub v2.4s, v2.4s, v3.4s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfcmpeq mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0xb0",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fcmeq v2.4s, v3.4s, v2.4s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfmul mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0xb4",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"fmul v2.4s, v3.4s, v2.4s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrcpit2 mm0, mm1": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x0f 0xb6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrcpit2 mm0, mm0": {
@@ -376,44 +376,44 @@
"0x0f 0x0f 0xb7"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"smull v2.4s, v2.4h, v3.4h",
"movi v3.4s, #0x80, lsl #8",
"add v2.4s, v2.4s, v3.4s",
"shrn v2.4h, v2.4s, #16",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pswapd mm0, mm1": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x0f 0xbb",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"rev64 v2.2s, v2.2s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pavgusb mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x0f 0xbf",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"urhadd v2.16b, v3.16b, v2.16b",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
}
}
unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
+4 -4
View File
@@ -1029,14 +1029,14 @@
"mov ebx, fs:0x14": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldr x20, [x28, #968]",
"ldr x20, [x28, #1000]",
"ldr w6, [x20, #20]"
]
},
"mov rbx, gs:0x14": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldr x20, [x28, #960]",
"ldr x20, [x28, #992]",
"ldur x6, [x20, #20]"
]
},
@@ -1048,9 +1048,9 @@
"x86InstructionCount": 2,
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"ldr x20, [x28, #960]",
"ldr x20, [x28, #992]",
"ldr x4, [x20, #256]",
"ldr x20, [x28, #960]",
"ldr x20, [x28, #992]",
"ldur x6, [x20, #20]"
]
},
unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json
+4 -4
View File
@@ -301,14 +301,14 @@
"mov ebx, fs:0x14": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldr w20, [x28, #968]",
"ldr w20, [x28, #1000]",
"ldr w6, [x20, #20]"
]
},
"mov ebx, gs:0x14": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldr w20, [x28, #960]",
"ldr w20, [x28, #992]",
"ldr w6, [x20, #20]"
]
},
@@ -320,9 +320,9 @@
"x86InstructionCount": 2,
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"ldr w20, [x28, #960]",
"ldr w20, [x28, #992]",
"ldr w4, [x20, #256]",
"ldr w20, [x28, #960]",
"ldr w20, [x28, #992]",
"ldr w6, [x20, #20]"
]
}
unittests/InstructionCountCI/FEXOpt/MultiInst.json
+24 -24
View File
@@ -217,7 +217,7 @@
"strb w21, [x11]",
"add x10, x10, #0x1 (1)",
"add x11, x11, #0x1 (1)",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"positive movsw": {
@@ -237,7 +237,7 @@
"strh w21, [x11]",
"add x10, x10, #0x2 (2)",
"add x11, x11, #0x2 (2)",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"positive movsd": {
@@ -257,7 +257,7 @@
"str w21, [x11]",
"add x10, x10, #0x4 (4)",
"add x11, x11, #0x4 (4)",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"positive movsq": {
@@ -277,7 +277,7 @@
"str x21, [x11]",
"add x10, x10, #0x8 (8)",
"add x11, x11, #0x8 (8)",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"negative movsb": {
@@ -297,7 +297,7 @@
"strb w21, [x11]",
"sub x10, x10, #0x1 (1)",
"sub x11, x11, #0x1 (1)",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"negative movsw": {
@@ -317,7 +317,7 @@
"strh w21, [x11]",
"sub x10, x10, #0x2 (2)",
"sub x11, x11, #0x2 (2)",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"negative movsd": {
@@ -337,7 +337,7 @@
"str w21, [x11]",
"sub x10, x10, #0x4 (4)",
"sub x11, x11, #0x4 (4)",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"negative movsq": {
@@ -357,7 +357,7 @@
"str x21, [x11]",
"sub x10, x10, #0x8 (8)",
"sub x11, x11, #0x8 (8)",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"positive rep movsb": {
@@ -412,7 +412,7 @@
"add x22, x0, x2",
"add x21, x1, x2",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"strb w20, [x28, #1018]",
"mov x11, x22",
"mov x10, x21"
]
@@ -469,7 +469,7 @@
"add x22, x0, x2, lsl #1",
"add x21, x1, x2, lsl #1",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"strb w20, [x28, #1018]",
"mov x11, x22",
"mov x10, x21"
]
@@ -526,7 +526,7 @@
"add x22, x0, x2, lsl #2",
"add x21, x1, x2, lsl #2",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"strb w20, [x28, #1018]",
"mov x11, x22",
"mov x10, x21"
]
@@ -583,7 +583,7 @@
"add x22, x0, x2, lsl #3",
"add x21, x1, x2, lsl #3",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"strb w20, [x28, #1018]",
"mov x11, x22",
"mov x10, x21"
]
@@ -644,7 +644,7 @@
"sub x22, x0, x2",
"sub x21, x1, x2",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"strb w20, [x28, #1018]",
"mov x11, x22",
"mov x10, x21"
]
@@ -705,7 +705,7 @@
"sub x22, x0, x2, lsl #1",
"sub x21, x1, x2, lsl #1",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"strb w20, [x28, #1018]",
"mov x11, x22",
"mov x10, x21"
]
@@ -766,7 +766,7 @@
"sub x22, x0, x2, lsl #2",
"sub x21, x1, x2, lsl #2",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"strb w20, [x28, #1018]",
"mov x11, x22",
"mov x10, x21"
]
@@ -827,7 +827,7 @@
"sub x22, x0, x2, lsl #3",
"sub x21, x1, x2, lsl #3",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"strb w20, [x28, #1018]",
"mov x11, x22",
"mov x10, x21"
]
@@ -872,7 +872,7 @@
"cbnz x0, #-0x8",
"add x11, x11, x7",
"mov w7, #0x0",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"positive rep stosw": {
@@ -915,7 +915,7 @@
"cbnz x0, #-0x8",
"add x11, x11, x7, lsl #1",
"mov w7, #0x0",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"positive rep stosd": {
@@ -958,7 +958,7 @@
"cbnz x0, #-0x8",
"add x11, x11, x7, lsl #2",
"mov w7, #0x0",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"positive rep stosq": {
@@ -1000,7 +1000,7 @@
"cbnz x0, #-0x8",
"add x11, x11, x7, lsl #3",
"mov w7, #0x0",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"negative rep stosb": {
@@ -1045,7 +1045,7 @@
"cbnz x0, #-0x8",
"sub x11, x11, x7",
"mov w7, #0x0",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"negative rep stosw": {
@@ -1090,7 +1090,7 @@
"cbnz x0, #-0x8",
"sub x11, x11, x7, lsl #1",
"mov w7, #0x0",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"negative rep stosd": {
@@ -1135,7 +1135,7 @@
"cbnz x0, #-0x8",
"sub x11, x11, x7, lsl #2",
"mov w7, #0x0",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"negative rep stosq": {
@@ -1179,7 +1179,7 @@
"cbnz x0, #-0x8",
"sub x11, x11, x7, lsl #3",
"mov w7, #0x0",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"Sekiro spill block": {
unittests/InstructionCountCI/FlagM/HotBlocks.json
+2 -2
View File
@@ -895,8 +895,8 @@
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w0, #0xd",
"ldr x1, [x28, #2280]",
"ldr x3, [x28, #2288]",
"ldr x1, [x28, #2296]",
"ldr x3, [x28, #2304]",
"blr x1",
"ldr x30, [sp], #16",
"mov w20, w0",
unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
+3 -3
View File
@@ -351,14 +351,14 @@
"ldr w4, [x9, #8]",
"mov x8, x9",
"ldr w9, [x8], #4",
"ldrb w20, [x28, #1019]",
"ldrb w21, [x28, #1186]",
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
}
}
unittests/InstructionCountCI/FlagM/Primary.json
+58 -58
View File
@@ -1669,30 +1669,30 @@
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
"ldrb w21, [x28, #984]",
"ldrb w21, [x28, #1016]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #985]",
"ldrb w21, [x28, #1017]",
"orr x20, x20, x21, lsl #9",
"ldrsb x21, [x28, #986]",
"ldrsb x21, [x28, #1018]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset x21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #988]",
"ldrb w21, [x28, #1020]",
"orr x20, x20, x21, lsl #12",
"ldrb w21, [x28, #990]",
"ldrb w21, [x28, #1022]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #992]",
"ldrb w21, [x28, #1024]",
"orr x20, x20, x21, lsl #16",
"ldrb w21, [x28, #993]",
"ldrb w21, [x28, #1025]",
"orr x20, x20, x21, lsl #17",
"ldrb w21, [x28, #994]",
"ldrb w21, [x28, #1026]",
"orr x20, x20, x21, lsl #18",
"ldrb w21, [x28, #995]",
"ldrb w21, [x28, #1027]",
"orr x20, x20, x21, lsl #19",
"ldrb w21, [x28, #996]",
"ldrb w21, [x28, #1028]",
"orr x20, x20, x21, lsl #20",
"ldrb w21, [x28, #997]",
"ldrb w21, [x28, #1029]",
"orr x20, x20, x21, lsl #21",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
@@ -1714,30 +1714,30 @@
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
"ldrb w21, [x28, #984]",
"ldrb w21, [x28, #1016]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #985]",
"ldrb w21, [x28, #1017]",
"orr x20, x20, x21, lsl #9",
"ldrsb x21, [x28, #986]",
"ldrsb x21, [x28, #1018]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset x21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #988]",
"ldrb w21, [x28, #1020]",
"orr x20, x20, x21, lsl #12",
"ldrb w21, [x28, #990]",
"ldrb w21, [x28, #1022]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #992]",
"ldrb w21, [x28, #1024]",
"orr x20, x20, x21, lsl #16",
"ldrb w21, [x28, #993]",
"ldrb w21, [x28, #1025]",
"orr x20, x20, x21, lsl #17",
"ldrb w21, [x28, #994]",
"ldrb w21, [x28, #1026]",
"orr x20, x20, x21, lsl #18",
"ldrb w21, [x28, #995]",
"ldrb w21, [x28, #1027]",
"orr x20, x20, x21, lsl #19",
"ldrb w21, [x28, #996]",
"ldrb w21, [x28, #1028]",
"orr x20, x20, x21, lsl #20",
"ldrb w21, [x28, #997]",
"ldrb w21, [x28, #1029]",
"orr x20, x20, x21, lsl #21",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
@@ -1764,37 +1764,37 @@
"rmif x27, #4, #nZcv",
"rmif x27, #4, #Nzcv",
"ubfx w20, w27, #8, #1",
"ldrb w21, [x28, #984]",
"ldrb w21, [x28, #1016]",
"and w21, w21, #0xfffffffe",
"mov w22, #0x1",
"mrs x23, nzcv",
"cmp x20, #0x0 (0)",
"csel x20, x21, x22, eq",
"strb w20, [x28, #984]",
"strb w20, [x28, #1016]",
"ubfx w20, w27, #9, #1",
"strb w20, [x28, #985]",
"strb w20, [x28, #1017]",
"ubfx w20, w27, #10, #1",
"sub x20, x22, x20, lsl #1",
"msr nzcv, x23",
"rmif x27, #11, #nzcV",
"ubfx w21, w27, #12, #1",
"strb w21, [x28, #988]",
"strb w21, [x28, #1020]",
"ubfx w21, w27, #14, #1",
"strb w21, [x28, #990]",
"strb w21, [x28, #1022]",
"ubfx w21, w27, #16, #1",
"strb w21, [x28, #992]",
"strb w21, [x28, #1024]",
"ubfx w21, w27, #17, #1",
"strb w21, [x28, #993]",
"strb w21, [x28, #1025]",
"ubfx w21, w27, #18, #1",
"strb w21, [x28, #994]",
"strb w21, [x28, #1026]",
"ubfx w21, w27, #19, #1",
"strb w21, [x28, #995]",
"strb w21, [x28, #1027]",
"ubfx w21, w27, #20, #1",
"strb w21, [x28, #996]",
"strb w21, [x28, #1028]",
"ubfx w21, w27, #21, #1",
"strb w21, [x28, #997]",
"strb w21, [x28, #1029]",
"mov w21, #0x10001",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"sahf": {
@@ -1844,7 +1844,7 @@
"lsl w0, w21, #24",
"cmp w0, w20, lsl #24",
"sub w26, w21, w20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x11, x11, x20",
"add x10, x10, x20"
]
@@ -1861,7 +1861,7 @@
"lsl w0, w21, #16",
"cmp w0, w20, lsl #16",
"sub w26, w21, w20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #1",
"add x11, x11, x20",
"add x10, x10, x20"
@@ -1877,7 +1877,7 @@
"ldr w21, [x10]",
"eor x27, x21, x20",
"subs w26, w21, w20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #2",
"add x11, x11, x20",
"add x10, x10, x20"
@@ -1893,7 +1893,7 @@
"ldr x21, [x10]",
"eor x27, x21, x20",
"subs x26, x21, x20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #3",
"add x11, x11, x20",
"add x10, x10, x20"
@@ -1904,7 +1904,7 @@
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x7, #+0x64",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -1935,7 +1935,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x7, #+0x64",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -1966,7 +1966,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x7, #+0x5c",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -1995,7 +1995,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x7, #+0x5c",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -2024,7 +2024,7 @@
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x7, #+0x64",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -2055,7 +2055,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x7, #+0x64",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -2086,7 +2086,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x7, #+0x5c",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -2115,7 +2115,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x7, #+0x5c",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -2212,7 +2212,7 @@
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, w20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x11, x11, x20"
]
},
@@ -2225,7 +2225,7 @@
"lsl w0, w4, #16",
"cmp w0, w20, lsl #16",
"sub w26, w4, w20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x11, x11, x20, lsl #1"
]
},
@@ -2236,7 +2236,7 @@
"ldr w20, [x11]",
"eor x27, x4, x20",
"subs w26, w4, w20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x11, x11, x20, lsl #2"
]
},
@@ -2247,7 +2247,7 @@
"ldr x20, [x11]",
"eor x27, x4, x20",
"subs x26, x4, x20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x11, x11, x20, lsl #3"
]
},
@@ -2255,7 +2255,7 @@
"ExpectedInstructionCount": 23,
"Comment": "0xae",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x2c",
@@ -2284,7 +2284,7 @@
"ExpectedInstructionCount": 23,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x2c",
@@ -2313,7 +2313,7 @@
"ExpectedInstructionCount": 19,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -2338,7 +2338,7 @@
"ExpectedInstructionCount": 19,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -2363,7 +2363,7 @@
"ExpectedInstructionCount": 23,
"Comment": "0xae",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x2c",
@@ -2392,7 +2392,7 @@
"ExpectedInstructionCount": 23,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x2c",
@@ -2421,7 +2421,7 @@
"ExpectedInstructionCount": 19,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -2446,7 +2446,7 @@
"ExpectedInstructionCount": 19,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
unittests/InstructionCountCI/FlagM/Primary_32Bit.json
+38 -38
View File
@@ -16,7 +16,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x06",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #928]",
"ldrh w20, [x28, #960]",
"str w20, [x8, #-4]!"
]
},
@@ -25,24 +25,24 @@
"Comment": "0x07",
"ExpectedArm64ASM": [
"ldr w20, [x8], #4",
"strh w20, [x28, #928]",
"strh w20, [x28, #960]",
"ubfx w21, w20, #2, #1",
"and w20, w20, #0xfff8",
"add x0, x28, x21, lsl #3",
"ldr x21, [x0, #1168]",
"ldr x21, [x0, #1184]",
"ldr x20, [x21, w20, uxtw]",
"lsr x21, x20, #32",
"and w22, w21, #0xff000000",
"orr w20, w22, w20, lsr #16",
"bfi w20, w21, #16, #8",
"str w20, [x28, #944]"
"str w20, [x28, #976]"
]
},
"push cs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0e",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #930]",
"ldrh w20, [x28, #962]",
"str w20, [x8, #-4]!"
]
},
@@ -50,7 +50,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x16",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #932]",
"ldrh w20, [x28, #964]",
"str w20, [x8, #-4]!"
]
},
@@ -59,26 +59,26 @@
"Comment": "0x17",
"ExpectedArm64ASM": [
"ldr w20, [x8], #4",
"ldrb w21, [x28, #984]",
"ldrb w21, [x28, #1016]",
"mov w22, #0x1",
"and w21, w21, #0x1",
"ldrb w23, [x28, #984]",
"ldrb w23, [x28, #1016]",
"and w23, w23, #0xfffffffe",
"mrs x12, nzcv",
"cmp x21, #0x0 (0)",
"csel x21, x23, x22, eq",
"strb w21, [x28, #984]",
"strh w20, [x28, #932]",
"strb w21, [x28, #1016]",
"strh w20, [x28, #964]",
"ubfx w21, w20, #2, #1",
"and w20, w20, #0xfff8",
"add x0, x28, x21, lsl #3",
"ldr x21, [x0, #1168]",
"ldr x21, [x0, #1184]",
"ldr x20, [x21, w20, uxtw]",
"lsr x21, x20, #32",
"and w22, w21, #0xff000000",
"orr w20, w22, w20, lsr #16",
"bfi w20, w21, #16, #8",
"str w20, [x28, #952]",
"str w20, [x28, #984]",
"msr nzcv, x12"
]
},
@@ -86,7 +86,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x1e",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #934]",
"ldrh w20, [x28, #966]",
"str w20, [x8, #-4]!"
]
},
@@ -95,17 +95,17 @@
"Comment": "0x1f",
"ExpectedArm64ASM": [
"ldr w20, [x8], #4",
"strh w20, [x28, #934]",
"strh w20, [x28, #966]",
"ubfx w21, w20, #2, #1",
"and w20, w20, #0xfff8",
"add x0, x28, x21, lsl #3",
"ldr x21, [x0, #1168]",
"ldr x21, [x0, #1184]",
"ldr x20, [x21, w20, uxtw]",
"lsr x21, x20, #32",
"and w22, w21, #0xff000000",
"orr w20, w22, w20, lsr #16",
"bfi w20, w21, #16, #8",
"str w20, [x28, #956]"
"str w20, [x28, #988]"
]
},
"daa": {
@@ -320,30 +320,30 @@
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
"ldrb w21, [x28, #984]",
"ldrb w21, [x28, #1016]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #985]",
"ldrb w21, [x28, #1017]",
"orr x20, x20, x21, lsl #9",
"ldrsb x21, [x28, #986]",
"ldrsb x21, [x28, #1018]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset x21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #988]",
"ldrb w21, [x28, #1020]",
"orr x20, x20, x21, lsl #12",
"ldrb w21, [x28, #990]",
"ldrb w21, [x28, #1022]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #992]",
"ldrb w21, [x28, #1024]",
"orr x20, x20, x21, lsl #16",
"ldrb w21, [x28, #993]",
"ldrb w21, [x28, #1025]",
"orr x20, x20, x21, lsl #17",
"ldrb w21, [x28, #994]",
"ldrb w21, [x28, #1026]",
"orr x20, x20, x21, lsl #18",
"ldrb w21, [x28, #995]",
"ldrb w21, [x28, #1027]",
"orr x20, x20, x21, lsl #19",
"ldrb w21, [x28, #996]",
"ldrb w21, [x28, #1028]",
"orr x20, x20, x21, lsl #20",
"ldrb w21, [x28, #997]",
"ldrb w21, [x28, #1029]",
"orr x20, x20, x21, lsl #21",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
@@ -365,30 +365,30 @@
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
"ldrb w21, [x28, #984]",
"ldrb w21, [x28, #1016]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #985]",
"ldrb w21, [x28, #1017]",
"orr x20, x20, x21, lsl #9",
"ldrsb x21, [x28, #986]",
"ldrsb x21, [x28, #1018]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset x21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #988]",
"ldrb w21, [x28, #1020]",
"orr x20, x20, x21, lsl #12",
"ldrb w21, [x28, #990]",
"ldrb w21, [x28, #1022]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #992]",
"ldrb w21, [x28, #1024]",
"orr x20, x20, x21, lsl #16",
"ldrb w21, [x28, #993]",
"ldrb w21, [x28, #1025]",
"orr x20, x20, x21, lsl #17",
"ldrb w21, [x28, #994]",
"ldrb w21, [x28, #1026]",
"orr x20, x20, x21, lsl #18",
"ldrb w21, [x28, #995]",
"ldrb w21, [x28, #1027]",
"orr x20, x20, x21, lsl #19",
"ldrb w21, [x28, #996]",
"ldrb w21, [x28, #1028]",
"orr x20, x20, x21, lsl #20",
"ldrb w21, [x28, #997]",
"ldrb w21, [x28, #1029]",
"orr x20, x20, x21, lsl #21",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
unittests/InstructionCountCI/FlagM/Secondary.json
+7 -7
View File
@@ -1604,10 +1604,10 @@
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xd7",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #3216]",
"cmlt v2.16b, v2.16b, #0",
"and v2.8b, v2.8b, v3.8b",
@@ -1621,12 +1621,12 @@
"ExpectedInstructionCount": 9,
"Comment": "0x0f 0xf7",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"cmlt v2.16b, v2.16b, #0",
"ldr d3, [x28, #1040]",
"ldr d3, [x28, #1056]",
"ldr d4, [x11]",
"bsl v2.8b, v3.8b, v4.8b",
"str d2, [x11]"
unittests/InstructionCountCI/FlagM/SecondaryGroup.json
+187 -187
View File
@@ -814,13 +814,13 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ushr v2.8h, v2.8h, #15",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrlw mm0, 16": {
@@ -828,13 +828,13 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrlw xmm0, 0": {
@@ -870,13 +870,13 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psraw mm0, 16": {
@@ -884,13 +884,13 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psraw xmm0, 0": {
@@ -926,13 +926,13 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"shl v2.8h, v2.8h, #15",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psllw mm0, 16": {
@@ -940,13 +940,13 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psllw xmm0, 0": {
@@ -982,13 +982,13 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ushr v2.4s, v2.4s, #31",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrld mm0, 32": {
@@ -996,13 +996,13 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrld xmm0, 0": {
@@ -1038,13 +1038,13 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrad mm0, 32": {
@@ -1052,13 +1052,13 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrad xmm0, 0": {
@@ -1094,13 +1094,13 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"shl v2.4s, v2.4s, #31",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pslld mm0, 32": {
@@ -1108,13 +1108,13 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pslld xmm0, 0": {
@@ -1150,13 +1150,13 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ushr v2.2d, v2.2d, #63",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrlq mm0, 64": {
@@ -1164,13 +1164,13 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrlq xmm0, 0": {
@@ -1229,13 +1229,13 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"shl v2.2d, v2.2d, #63",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psllq mm0, 64": {
@@ -1243,13 +1243,13 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psllq xmm0, 0": {
@@ -1278,61 +1278,61 @@
"ExpectedInstructionCount": 68,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #1184]",
"ldrh w20, [x28, #1200]",
"strh w20, [x4]",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"lsl x20, x20, #11",
"ldrb w21, [x28, #1016]",
"ldrb w21, [x28, #1048]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #1017]",
"ldrb w21, [x28, #1049]",
"orr x20, x20, x21, lsl #9",
"ldrb w21, [x28, #1018]",
"ldrb w21, [x28, #1050]",
"orr x20, x20, x21, lsl #10",
"ldrb w21, [x28, #1022]",
"ldrb w21, [x28, #1054]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #1008]",
"ldrb w21, [x28, #1040]",
"orr x20, x20, x21",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1186]",
"ldrb w20, [x28, #1202]",
"strb w20, [x4, #4]",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #32]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #48]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #64]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #80]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #96]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #112]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #128]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #144]",
"stp q16, q17, [x4, #160]",
"stp q18, q19, [x4, #192]",
@@ -1342,7 +1342,7 @@
"stp q26, q27, [x4, #320]",
"stp q28, q29, [x4, #352]",
"stp q30, q31, [x4, #384]",
"ldr w20, [x28, #940]",
"ldr w20, [x28, #972]",
"and w20, w20, #0xffc0",
"mov w21, #0xffff",
"stp w20, w21, [x4, #24]"
@@ -1352,14 +1352,14 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr w4, [x28, #968]"
"ldr w4, [x28, #1000]"
]
},
"rdfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr x4, [x28, #968]"
"ldr x4, [x28, #1000]"
]
},
"fxrstor [rax]": {
@@ -1367,34 +1367,34 @@
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"strh w20, [x28, #1184]",
"strh w20, [x28, #1200]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #1019]",
"strb w21, [x28, #1051]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w24, w20, #14, #1",
"ubfx w20, w20, #0, #1",
"strb w21, [x28, #1016]",
"strb w22, [x28, #1017]",
"strb w23, [x28, #1018]",
"strb w24, [x28, #1022]",
"strb w20, [x28, #1008]",
"strb w21, [x28, #1048]",
"strb w22, [x28, #1049]",
"strb w23, [x28, #1050]",
"strb w24, [x28, #1054]",
"strb w20, [x28, #1040]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1186]",
"strb w20, [x28, #1202]",
"ldp q2, q3, [x4, #32]",
"str q2, [x28, #1040]",
"str q3, [x28, #1056]",
"str q2, [x28, #1056]",
"str q3, [x28, #1072]",
"ldp q2, q3, [x4, #64]",
"str q2, [x28, #1072]",
"str q3, [x28, #1088]",
"str q2, [x28, #1088]",
"str q3, [x28, #1104]",
"ldp q2, q3, [x4, #96]",
"str q2, [x28, #1104]",
"str q3, [x28, #1120]",
"str q2, [x28, #1120]",
"str q3, [x28, #1136]",
"ldp q2, q3, [x4, #128]",
"str q2, [x28, #1136]",
"str q3, [x28, #1152]",
"str q2, [x28, #1152]",
"str q3, [x28, #1168]",
"ldp q16, q17, [x4, #160]",
"ldp q18, q19, [x4, #192]",
"ldp q20, q21, [x4, #224]",
@@ -1405,7 +1405,7 @@
"ldp q30, q31, [x4, #384]",
"ldr w20, [x4, #24]",
"and w20, w20, #0xffc0",
"str w20, [x28, #940]",
"str w20, [x28, #972]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
@@ -1420,14 +1420,14 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr w4, [x28, #960]"
"ldr w4, [x28, #992]"
]
},
"rdgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr x4, [x28, #960]"
"ldr x4, [x28, #992]"
]
},
"ldmxcsr [rax]": {
@@ -1436,7 +1436,7 @@
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"and w20, w20, #0xffc0",
"str w20, [x28, #940]",
"str w20, [x28, #972]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
@@ -1452,21 +1452,21 @@
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #968]"
"str x20, [x28, #1000]"
]
},
"wrfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"str x4, [x28, #968]"
"str x4, [x28, #1000]"
]
},
"stmxcsr [rax]": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"ldr w20, [x28, #940]",
"ldr w20, [x28, #972]",
"and w20, w20, #0xffc0",
"str w20, [x4]"
]
@@ -1476,14 +1476,14 @@
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #960]"
"str x20, [x28, #992]"
]
},
"wrgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"str x4, [x28, #960]"
"str x4, [x28, #992]"
]
},
"xsave [rax]": {
@@ -1493,61 +1493,61 @@
"ubfx x20, x4, #0, #1",
"cbnz x20, #+0x8",
"b #+0xe4",
"ldrh w20, [x28, #1184]",
"ldrh w20, [x28, #1200]",
"strh w20, [x4]",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"lsl x20, x20, #11",
"ldrb w21, [x28, #1016]",
"ldrb w21, [x28, #1048]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #1017]",
"ldrb w21, [x28, #1049]",
"orr x20, x20, x21, lsl #9",
"ldrb w21, [x28, #1018]",
"ldrb w21, [x28, #1050]",
"orr x20, x20, x21, lsl #10",
"ldrb w21, [x28, #1022]",
"ldrb w21, [x28, #1054]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #1008]",
"ldrb w21, [x28, #1040]",
"orr x20, x20, x21",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1186]",
"ldrb w20, [x28, #1202]",
"strb w20, [x4, #4]",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #32]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #48]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #64]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #80]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #96]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #112]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #128]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #144]",
"ubfx x20, x4, #1, #1",
"cbnz x20, #+0x8",
@@ -1582,7 +1582,7 @@
"ubfx x20, x4, #1, #2",
"cbnz x20, #+0x8",
"b #+0x14",
"ldr w20, [x28, #940]",
"ldr w20, [x28, #972]",
"and w20, w20, #0xffc0",
"mov w21, #0xffff",
"stp w20, w21, [x4, #24]",
@@ -1597,61 +1597,61 @@
"ubfx x20, x4, #0, #1",
"cbnz x20, #+0x8",
"b #+0xe4",
"ldrh w20, [x28, #1184]",
"ldrh w20, [x28, #1200]",
"strh w20, [x4]",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"lsl x20, x20, #11",
"ldrb w21, [x28, #1016]",
"ldrb w21, [x28, #1048]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #1017]",
"ldrb w21, [x28, #1049]",
"orr x20, x20, x21, lsl #9",
"ldrb w21, [x28, #1018]",
"ldrb w21, [x28, #1050]",
"orr x20, x20, x21, lsl #10",
"ldrb w21, [x28, #1022]",
"ldrb w21, [x28, #1054]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #1008]",
"ldrb w21, [x28, #1040]",
"orr x20, x20, x21",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1186]",
"ldrb w20, [x28, #1202]",
"strb w20, [x4, #4]",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #32]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #48]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #64]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #80]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #96]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #112]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #128]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #144]",
"ubfx x20, x4, #1, #1",
"cbnz x20, #+0x8",
@@ -1686,7 +1686,7 @@
"ubfx x20, x4, #1, #2",
"cbnz x20, #+0x8",
"b #+0x14",
"ldr w20, [x28, #940]",
"ldr w20, [x28, #972]",
"and w20, w20, #0xffc0",
"mov w21, #0xffff",
"stp w20, w21, [x4, #24]",
@@ -1711,46 +1711,45 @@
"cbnz x20, #+0x8",
"b #+0x7c",
"ldrh w20, [x4]",
"strh w20, [x28, #1184]",
"strh w20, [x28, #1200]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #1019]",
"strb w21, [x28, #1051]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w24, w20, #14, #1",
"ubfx w20, w20, #0, #1",
"strb w21, [x28, #1016]",
"strb w22, [x28, #1017]",
"strb w23, [x28, #1018]",
"strb w24, [x28, #1022]",
"strb w20, [x28, #1008]",
"strb w21, [x28, #1048]",
"strb w22, [x28, #1049]",
"strb w23, [x28, #1050]",
"strb w24, [x28, #1054]",
"strb w20, [x28, #1040]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1186]",
"strb w20, [x28, #1202]",
"ldp q2, q3, [x4, #32]",
"str q2, [x28, #1040]",
"str q3, [x28, #1056]",
"str q2, [x28, #1056]",
"str q3, [x28, #1072]",
"ldp q2, q3, [x4, #64]",
"str q2, [x28, #1072]",
"str q3, [x28, #1088]",
"str q2, [x28, #1088]",
"str q3, [x28, #1104]",
"ldp q2, q3, [x4, #96]",
"str q2, [x28, #1104]",
"str q3, [x28, #1120]",
"str q2, [x28, #1120]",
"str q3, [x28, #1136]",
"ldp q2, q3, [x4, #128]",
"str q2, [x28, #1136]",
"str q3, [x28, #1152]",
"str q2, [x28, #1152]",
"str q3, [x28, #1168]",
"b #+0x4c",
"mov w20, #0x37f",
"strh w20, [x28, #1184]",
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1186]",
"strb wzr, [x28, #1016]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1018]",
"strb wzr, [x28, #1022]",
"strb wzr, [x28, #1008]",
"strh w20, [x28, #1200]",
"strb wzr, [x28, #1051]",
"strb wzr, [x28, #1202]",
"strb wzr, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb wzr, [x28, #1050]",
"strb wzr, [x28, #1054]",
"strb wzr, [x28, #1040]",
"movi v2.2d, #0x0",
"str q2, [x28, #1040]",
"str q2, [x28, #1056]",
"str q2, [x28, #1072]",
"str q2, [x28, #1088]",
@@ -1758,6 +1757,7 @@
"str q2, [x28, #1120]",
"str q2, [x28, #1136]",
"str q2, [x28, #1152]",
"str q2, [x28, #1168]",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #1",
"cbnz x20, #+0x8",
@@ -1827,7 +1827,7 @@
"b #+0x34",
"ldr w20, [x4, #24]",
"and w20, w20, #0xffc0",
"str w20, [x28, #940]",
"str w20, [x28, #972]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
unittests/InstructionCountCI/FlagM/SecondaryModRM.json
+8 -8
View File
@@ -25,8 +25,8 @@
"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x3], #64",
"stp x18, x30, [x3], #16",
"mrs x3, nzcv",
"str w3, [x28, #1000]",
"str x25, [x28, #1024]",
"str w3, [x28, #1032]",
"str x25, [x28, #432]",
"stp x4, x7, [x28, #288]",
"stp x5, x6, [x28, #304]",
"stp x8, x9, [x28, #320]",
@@ -36,19 +36,19 @@
"stp x16, x17, [x28, #384]",
"stp x19, x29, [x28, #400]",
"stp w26, w27, [x28, #16]",
"add x3, x28, #0x1a0 (416)",
"add x3, x28, #0x1c0 (448)",
"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x3], #64",
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x3], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64",
"mov w1, w7",
"ldr x0, [x28, #1512]",
"ldr x2, [x28, #1528]",
"ldr x0, [x28, #1528]",
"ldr x2, [x28, #1544]",
"blr x2",
"ldr x25, [x28, #1024]",
"ldr w4, [x28, #1000]",
"ldr x25, [x28, #432]",
"ldr w4, [x28, #1032]",
"msr nzcv, x4",
"add x4, x28, #0x1a0 (416)",
"add x4, x28, #0x1c0 (448)",
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
unittests/InstructionCountCI/FlagM/VEX_map1.json
+1 -1
View File
@@ -83,7 +83,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2440]",
"ldr x0, [x28, #2456]",
"ld1b {z2.b}, p7/z, [x0]",
"mrs x0, nzcv",
"mov z0.d, #0",
unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json
+2706 -2706
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87-HalfLife.json
+561 -561
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87-Oblivion.json
+6874 -6874
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
+7088 -7088
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87.json
+2801 -2801
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json
+12 -12
View File
@@ -1682,7 +1682,7 @@
"ldr s3, [x9, #16]",
"fcvt d3, s3",
"fmul d2, d2, d3",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s2, d2",
"stur s2, [x9, #-244]",
"ldur s2, [x9, #-120]",
@@ -1700,7 +1700,7 @@
"ldr s4, [x9, x20, sxtx]",
"fcvt d4, s4",
"fmul d2, d2, d4",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s2, d2",
"stur s2, [x9, #-248]",
"ldur s2, [x9, #-100]",
@@ -1899,7 +1899,7 @@
"fcvt d5, s5",
"fsub d2, d2, d5",
"fmul d2, d3, d2",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s2, d2",
"stur s2, [x9, #-132]",
"ldur s2, [x9, #-12]",
@@ -1934,7 +1934,7 @@
"ldr s3, [x9, #16]",
"fcvt d3, s3",
"fmul d2, d2, d3",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s2, d2",
"stur s2, [x9, #-124]",
"ldur s2, [x9, #-244]",
@@ -2182,7 +2182,7 @@
"ldur s5, [x9, #-36]",
"fcvt d5, s5",
"fadd d4, d4, d5",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s4, d4",
"stur s4, [x9, #-40]",
"ldur s4, [x9, #-48]",
@@ -2271,7 +2271,7 @@
"fcvt d6, s6",
"fsub d4, d4, d6",
"fmul d3, d3, d4",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s3, d3",
"stur s3, [x9, #-4]",
"ldur s3, [x9, #-8]",
@@ -2279,7 +2279,7 @@
"ldur s4, [x9, #-4]",
"fcvt d4, s4",
"fadd d3, d3, d4",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s3, d3",
"stur s3, [x9, #-8]",
"ldur s3, [x9, #-16]",
@@ -2380,7 +2380,7 @@
"stur s3, [x9, #-84]",
"ldur s3, [x9, #-84]",
"str s3, [x7, #640]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s2, d2",
"str s2, [x7, #896]",
"ldur s2, [x9, #-32]",
@@ -2527,21 +2527,21 @@
"fcvt s2, d2",
"str s2, [x7, #704]",
"fadd d2, d5, d4",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s2, d2",
"str s2, [x7, #832]",
"fcvt s2, d4",
"str s2, [x7, #960]",
"mov x8, x9",
"ldp w9, w20, [x8], #8",
"ldrb w21, [x28, #1019]",
"ldrb w22, [x28, #1186]",
"ldrb w21, [x28, #1051]",
"ldrb w22, [x28, #1202]",
"mov w23, #0x8",
"sub w21, w23, w21",
"mov w23, #0xf8f8",
"lsr w21, w23, w21",
"bic w21, w22, w21",
"strb w21, [x28, #1186]"
"strb w21, [x28, #1202]"
],
"x86InstructionCount": 809,
"ExpectedInstructionCount": 1714
unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json
+96 -96
View File
@@ -120,25 +120,25 @@
"fcvt d9, s9",
"fsub d2, d9, d2",
"mov w20, #0x0",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s2, d2",
"str s2, [x8, #24]",
"ldr s2, [x4, #4]",
"fcvt d2, s2",
"fsub d5, d2, d5",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s5, d5",
"str s5, [x8, #28]",
"ldr s5, [x4, #8]",
"fcvt d5, s5",
"fsub d7, d5, d7",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d3, d3, d9",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d2, d6, d2",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d5, d8, d5",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d4, d4, d4",
"fmov d6, x20",
"fadd d4, d4, d6",
@@ -159,38 +159,38 @@
"fcvt d8, s8",
"fmul d8, d8, d8",
"fadd d6, d6, d8",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d7, d7, d7",
"fadd d6, d6, d7",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d3, d3, d3",
"fmov d7, x20",
"fadd d3, d3, d7",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d2, d2, d2",
"fadd d2, d3, d2",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d3, d5, d5",
"fadd d2, d2, d3",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcmp d4, d6",
"cset x26, vc",
"axflag",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str d4, [x21, #1040]",
"str d4, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"str d6, [x21, #1040]",
"str d6, [x21, #1056]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"str d2, [x21, #1040]",
"ldrb w21, [x28, #1186]",
"str d2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x707",
@@ -199,7 +199,7 @@
"mov w22, #0xf8f8",
"lsr w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
},
"Block2": {
@@ -255,7 +255,7 @@
"ldr s3, [x4]",
"fcvt d3, s3",
"fabs d3, d3",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcmp d2, d3",
"axflag",
"csetm x20, ls",
@@ -267,7 +267,7 @@
"ldr s3, [x4, #4]",
"fcvt d3, s3",
"fabs d3, d3",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcmp d2, d3",
"axflag",
"csetm x20, ls",
@@ -279,14 +279,14 @@
"ldr s3, [x4, #8]",
"fcvt d3, s3",
"fabs d3, d3",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcmp d2, d3",
"axflag",
"csetm x20, ls",
"dup v6.2d, x20",
"bsl v6.16b, v3.16b, v2.16b",
"fmul d2, d4, d4",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d3, d5, d5",
"fadd d2, d2, d3",
"fmul d3, d6, d6",
@@ -295,17 +295,17 @@
"fcmp d3, d3",
"cset x26, vc",
"axflag",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str d3, [x21, #1040]",
"str d3, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"str d2, [x21, #1040]",
"ldrb w21, [x28, #1186]",
"str d2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x303",
@@ -314,7 +314,7 @@
"mov w22, #0xc0c0",
"lsr w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
},
"Block3": {
@@ -373,21 +373,21 @@
"ldr s8, [x4, #8]",
"fcvt d8, s8",
"fmul d7, d7, d8",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"ldr s8, [x8]",
"fcvt d8, s8",
"fmul d5, d5, d8",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d2, d2, d6",
"fsub d2, d5, d2",
"ldr s5, [x4, #4]",
"fcvt d5, s5",
"fmul d2, d2, d5",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fadd d2, d7, d2",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d4, d4, d6",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"ldr s5, [x8]",
"fcvt d5, s5",
"fmul d3, d3, d5",
@@ -398,23 +398,23 @@
"fcvt d4, s4",
"fmul d3, d3, d4",
"fadd d2, d2, d3",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr d3, [x22, #1040]",
"ldr d3, [x22, #1056]",
"add x20, x28, x20, lsl #4",
"fdiv d3, d2, d3",
"fcvt s4, d3",
"str s4, [x10]",
"add w21, w21, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1019]",
"str d2, [x20, #1040]",
"str d3, [x22, #1040]",
"strb wzr, [x28, #1186]"
"strb w21, [x28, #1051]",
"str d2, [x20, #1056]",
"str d3, [x22, #1056]",
"strb wzr, [x28, #1202]"
]
},
"Block4": {
@@ -505,14 +505,14 @@
"mov w20, #0x44",
"movk w20, #0x1, lsl #16",
"str w20, [x8, #-4]!",
"ldrb w21, [x28, #1019]",
"ldrb w22, [x28, #1186]",
"ldrb w21, [x28, #1051]",
"ldrb w22, [x28, #1202]",
"mov w23, #0x1",
"add w21, w21, #0x7 (7)",
"and w21, w21, #0x7",
"lsl w21, w23, w21",
"bic w21, w22, w21",
"strb w21, [x28, #1186]"
"strb w21, [x28, #1202]"
]
},
"Block5": {
@@ -585,7 +585,7 @@
"fcvt d3, s3",
"fmul d2, d2, d3",
"mov w20, #0x0",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"ldr s4, [x8, #124]",
"fcvt d4, s4",
"fadd d2, d2, d4",
@@ -634,7 +634,7 @@
"fmov d2, x20",
"ldr s3, [x8, #40]",
"fcvt d3, s3",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcmp d2, d3",
"cset x26, vc",
"axflag",
@@ -650,14 +650,14 @@
"mov w20, #0xb2",
"movk w20, #0x1, lsl #16",
"str w20, [x8, #-4]!",
"ldrb w21, [x28, #1019]",
"ldrb w22, [x28, #1186]",
"ldrb w21, [x28, #1051]",
"ldrb w22, [x28, #1202]",
"mov w23, #0x8",
"sub w21, w23, w21",
"mov w23, #0xe0e0",
"lsr w21, w23, w21",
"bic w21, w22, w21",
"strb w21, [x28, #1186]"
"strb w21, [x28, #1202]"
]
},
"Block6": {
@@ -763,29 +763,29 @@
"fadd d5, d5, d6",
"mov w20, #0x0",
"fmov d6, x20",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcmp d5, d6",
"cset x26, vc",
"axflag",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str d5, [x21, #1040]",
"str d5, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"str d4, [x21, #1040]",
"str d4, [x21, #1056]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"str d3, [x21, #1040]",
"str d3, [x21, #1056]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"str d2, [x21, #1040]",
"ldrb w21, [x28, #1186]",
"str d2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w22, w22, w20",
"mov w23, #0xf0f",
@@ -796,7 +796,7 @@
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
},
"Block7": {
@@ -846,7 +846,7 @@
"ldr s6, [x4, #8]",
"fcvt d6, s6",
"fmul d5, d5, d6",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"ldr s6, [x5, #8]",
"fcvt d6, s6",
"fmul d3, d3, d6",
@@ -861,36 +861,36 @@
"ldr s5, [x5, #4]",
"fcvt d5, s5",
"fmul d4, d4, d5",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"ldr s5, [x5, #8]",
"fcvt d5, s5",
"fmul d2, d2, d5",
"fsub d2, d4, d2",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"ldr s4, [x4]",
"fcvt d4, s4",
"fmul d2, d2, d4",
"fadd d2, d3, d2",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr d3, [x22, #1040]",
"ldr d3, [x22, #1056]",
"add x20, x28, x20, lsl #4",
"fdiv d2, d2, d3",
"fcvt s3, d2",
"str s3, [x11]",
"strb w21, [x28, #1019]",
"str d2, [x20, #1040]",
"ldrb w20, [x28, #1186]",
"strb w21, [x28, #1051]",
"str d2, [x20, #1056]",
"ldrb w20, [x28, #1202]",
"mov w22, #0x8",
"sub w21, w22, w21",
"mov w22, #0xf8f8",
"lsr w21, w22, w21",
"bic w20, w20, w21",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
},
"Block8": {
@@ -924,39 +924,39 @@
"fxch"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1040]",
"ldr d2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr d3, [x21, #1040]",
"ldr d3, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr d4, [x22, #1040]",
"strb wzr, [x28, #1017]",
"ldr d4, [x22, #1056]",
"strb wzr, [x28, #1049]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x23, x28, x20, lsl #4",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s5, d3",
"str s5, [x8, #56]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s5, d4",
"str s5, [x8, #44]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x12, x28, x20, lsl #4",
"ldr d5, [x12, #1040]",
"strb wzr, [x28, #1017]",
"ldr d5, [x12, #1056]",
"strb wzr, [x28, #1049]",
"fcvt s6, d5",
"str s6, [x8, #40]",
"str d2, [x8]",
@@ -965,12 +965,12 @@
"mov w13, #0x24",
"movk w13, #0x1, lsl #16",
"str w13, [x8, #-4]!",
"strb w20, [x28, #1019]",
"str d3, [x21, #1040]",
"str d4, [x22, #1040]",
"str d5, [x23, #1040]",
"str d2, [x12, #1040]",
"strb wzr, [x28, #1186]"
"strb w20, [x28, #1051]",
"str d3, [x21, #1056]",
"str d4, [x22, #1056]",
"str d5, [x23, #1056]",
"str d2, [x12, #1056]",
"strb wzr, [x28, #1202]"
]
},
"Block9": {
@@ -1004,39 +1004,39 @@
"fxch"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1040]",
"ldr d2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr d3, [x21, #1040]",
"ldr d3, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr d4, [x22, #1040]",
"strb wzr, [x28, #1017]",
"ldr d4, [x22, #1056]",
"strb wzr, [x28, #1049]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x23, x28, x20, lsl #4",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s5, d3",
"str s5, [x8, #56]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s5, d4",
"str s5, [x8, #44]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x12, x28, x20, lsl #4",
"ldr d5, [x12, #1040]",
"strb wzr, [x28, #1017]",
"ldr d5, [x12, #1056]",
"strb wzr, [x28, #1049]",
"fcvt s6, d5",
"str s6, [x8, #40]",
"str d2, [x8]",
@@ -1045,12 +1045,12 @@
"mov w13, #0x24",
"movk w13, #0x1, lsl #16",
"str w13, [x8, #-4]!",
"strb w20, [x28, #1019]",
"str d3, [x21, #1040]",
"str d4, [x22, #1040]",
"str d5, [x23, #1040]",
"str d2, [x12, #1040]",
"strb wzr, [x28, #1186]"
"strb w20, [x28, #1051]",
"str d3, [x21, #1056]",
"str d4, [x22, #1056]",
"str d5, [x23, #1056]",
"str d2, [x12, #1056]",
"strb wzr, [x28, #1202]"
]
},
"Block10": {
@@ -1188,7 +1188,7 @@
"sub w8, w8, #0xa4 (164)",
"ldr w6, [x8, #176]",
"add w10, w8, #0x18 (24)",
"ldr w20, [x28, #960]",
"ldr w20, [x28, #992]",
"ldr w4, [x20, #20]",
"str w4, [x8, #156]",
"subs w26, w4, w4",
unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json
+193 -193
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json
+106 -106
View File
@@ -606,7 +606,7 @@
"fadd d9, d9, d8",
"fcvt s9, d9",
"str s9, [x8, #120]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"ldr s9, [x8, #4]",
"fcvt d9, s9",
"fsub d7, d7, d9",
@@ -731,7 +731,7 @@
"ldr s9, [x8, #16]",
"fcvt d9, s9",
"fmul d8, d8, d9",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"ldr s9, [x8, #20]",
"fcvt d9, s9",
"fmul d7, d7, d9",
@@ -820,7 +820,7 @@
"ldr s8, [x8]",
"fcvt d8, s8",
"fmul d8, d8, d3",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d7, d7, d4",
"fsub d7, d8, d7",
"fcvt s7, d7",
@@ -901,7 +901,7 @@
"ldr s8, [x8]",
"fcvt d8, s8",
"fmul d8, d8, d6",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d7, d7, d5",
"fadd d7, d8, d7",
"fcvt s7, d7",
@@ -956,7 +956,7 @@
"ldr s8, [x8]",
"fcvt d8, s8",
"fmul d8, d8, d6",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d7, d7, d5",
"fadd d7, d8, d7",
"fcvt s7, d7",
@@ -1034,11 +1034,11 @@
"fsub d7, d7, d8",
"fcvt s7, d7",
"str s7, [x8, #12]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"ldr s7, [x8, #16]",
"fcvt d7, s7",
"fmul d5, d5, d7",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"ldr s7, [x8, #20]",
"fcvt d7, s7",
"fmul d6, d6, d7",
@@ -1059,7 +1059,7 @@
"fcvt s8, d8",
"str s8, [x8, #4]",
"fmul d7, d7, d4",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d6, d6, d3",
"fadd d6, d7, d6",
"fcvt s6, d6",
@@ -1104,7 +1104,7 @@
"fcvt s7, d7",
"str s7, [x8, #12]",
"fmul d4, d6, d4",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d3, d5, d3",
"fsub d3, d4, d3",
"ldr s4, [x4, #124]",
@@ -1129,7 +1129,7 @@
"ldr s6, [x8, #16]",
"fcvt d6, s6",
"fmul d5, d5, d6",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"ldr s6, [x8, #20]",
"fcvt d6, s6",
"fmul d4, d4, d6",
@@ -1182,7 +1182,7 @@
"fadd d7, d7, d5",
"fcvt s7, d7",
"str s7, [x4, #4]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d4, d4, d6",
"fcvt s4, d4",
"str s4, [x4, #8]",
@@ -1220,7 +1220,7 @@
"fadd d4, d7, d4",
"fcvt s4, d4",
"str s4, [x4, #24]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d4, d5, d6",
"fcvt s4, d4",
"str s4, [x4, #28]",
@@ -1258,7 +1258,7 @@
"fadd d7, d6, d5",
"fcvt s7, d7",
"str s7, [x4, #36]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"ldr s7, [x8, #4]",
"fcvt d7, s7",
"fsub d4, d4, d7",
@@ -1339,7 +1339,7 @@
"fadd d7, d7, d5",
"fcvt s7, d7",
"str s7, [x4, #68]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d4, d4, d6",
"fcvt s4, d4",
"str s4, [x4, #72]",
@@ -1377,7 +1377,7 @@
"fadd d4, d7, d4",
"fcvt s4, d4",
"str s4, [x4, #88]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d4, d5, d6",
"fcvt s4, d4",
"str s4, [x4, #92]",
@@ -1413,7 +1413,7 @@
"fadd d7, d6, d5",
"fcvt s7, d7",
"str s7, [x4, #100]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"ldr s7, [x8, #4]",
"fcvt d7, s7",
"fsub d4, d4, d7",
@@ -1478,7 +1478,7 @@
"cfinv",
"mov x27, x8",
"mov x8, x26",
"strb wzr, [x28, #1186]"
"strb wzr, [x28, #1202]"
]
},
"Block2": {
@@ -1988,7 +1988,7 @@
"fadd d8, d8, d6",
"fcvt s8, d8",
"str s8, [x8, #100]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d5, d5, d7",
"fcvt s5, d5",
"str s5, [x8, #60]",
@@ -2083,7 +2083,7 @@
"fadd d8, d8, d6",
"fcvt s8, d8",
"str s8, [x8, #132]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d5, d5, d7",
"fcvt s5, d5",
"str s5, [x8, #32]",
@@ -2108,7 +2108,7 @@
"fcvt s7, d7",
"str s7, [x8, #104]",
"fmul d6, d6, d4",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d5, d5, d3",
"fadd d5, d6, d5",
"fcvt s5, d5",
@@ -2128,9 +2128,9 @@
"fsub d7, d7, d8",
"fcvt s7, d7",
"str s7, [x8, #128]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d5, d5, d4",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d6, d6, d3",
"fadd d5, d5, d6",
"fcvt s5, d5",
@@ -2193,7 +2193,7 @@
"fadd d8, d8, d6",
"fcvt s8, d8",
"str s8, [x8, #108]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d5, d5, d7",
"fcvt s5, d5",
"str s5, [x8, #76]",
@@ -2296,7 +2296,7 @@
"fadd d8, d8, d6",
"fcvt s8, d8",
"str s8, [x8, #140]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d5, d5, d7",
"fcvt s5, d5",
"str s5, [x8, #44]",
@@ -2320,9 +2320,9 @@
"fsub d7, d7, d8",
"fcvt s7, d7",
"str s7, [x8, #28]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d5, d5, d4",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d6, d6, d3",
"fadd d5, d5, d6",
"fcvt s5, d5",
@@ -2343,7 +2343,7 @@
"fcvt s7, d7",
"str s7, [x8]",
"fmul d4, d6, d4",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d3, d5, d3",
"fadd d3, d4, d3",
"ldr s4, [x8, #80]",
@@ -2389,13 +2389,13 @@
"fadd d6, d6, d7",
"fcvt s6, d6",
"str s6, [x8]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"ldr s6, [x8, #48]",
"fcvt d6, s6",
"fadd d3, d3, d6",
"fcvt s3, d3",
"str s3, [x8, #12]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fadd d3, d5, d4",
"fcvt s3, d3",
"str s3, [x4, #96]",
@@ -2406,7 +2406,7 @@
"fadd d3, d3, d6",
"fcvt s3, d3",
"str s3, [x4, #100]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d3, d4, d5",
"fcvt s3, d3",
"str s3, [x4, #104]",
@@ -2503,7 +2503,7 @@
"fadd d6, d6, d4",
"fcvt s6, d6",
"str s6, [x4, #68]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d3, d3, d5",
"fcvt s3, d3",
"str s3, [x4, #72]",
@@ -2706,7 +2706,7 @@
"fadd d5, d5, d3",
"fcvt s5, d5",
"str s5, [x4, #4]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d2, d2, d4",
"fcvt s2, d2",
"str s2, [x4, #8]",
@@ -2747,14 +2747,14 @@
"adds w26, w8, #0x90 (144)",
"cfinv",
"mov x8, x26",
"ldrb w20, [x28, #1019]",
"ldrb w21, [x28, #1186]",
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0xfefe",
"lsr w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
},
"Block3": {
@@ -3919,9 +3919,9 @@
"ldr w9, [x8, #100]",
"ldr s2, [x9, #8]",
"fcvt d2, s2",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr d3, [x21, #1040]",
"ldr d3, [x21, #1056]",
"fadd d2, d3, d2",
"add w9, w9, #0x10 (16)",
"str w9, [x8, #100]",
@@ -4115,7 +4115,7 @@
"fsub d6, d6, d7",
"fcvt s6, d6",
"str s6, [x11, #4]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d3, d3, d5",
"fcvt s3, d3",
"stur s3, [x10, #-8]",
@@ -4392,7 +4392,7 @@
"fcvt s6, d6",
"str s6, [x9, #4]",
"ldr w9, [x8, #112]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d3, d3, d5",
"fcvt s3, d3",
"str s3, [x9, #8]",
@@ -4544,13 +4544,13 @@
"fsub d5, d5, d6",
"fcvt s7, d5",
"str s7, [x6, #20]",
"strb w20, [x28, #1019]",
"str d2, [x21, #1040]",
"str d6, [x22, #1040]",
"str d5, [x13, #1040]",
"str d4, [x12, #1040]",
"str d3, [x23, #1040]",
"ldrb w21, [x28, #1186]",
"strb w20, [x28, #1051]",
"str d2, [x21, #1056]",
"str d6, [x22, #1056]",
"str d5, [x13, #1056]",
"str d4, [x12, #1056]",
"str d3, [x23, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w22, w22, w20",
"orr w21, w21, w22",
@@ -4559,7 +4559,7 @@
"mov w22, #0xf0f0",
"lsr w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
},
"Block5": {
@@ -4917,9 +4917,9 @@
"ldr w9, [x8, #100]",
"ldr s2, [x9, #8]",
"fcvt d2, s2",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr d3, [x21, #1040]",
"ldr d3, [x21, #1056]",
"fadd d2, d3, d2",
"add w9, w9, #0x10 (16)",
"str w9, [x8, #100]",
@@ -5111,7 +5111,7 @@
"fadd d6, d6, d7",
"fcvt s6, d6",
"str s6, [x11, #4]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d3, d3, d5",
"fcvt s3, d3",
"stur s3, [x10, #-8]",
@@ -5389,7 +5389,7 @@
"fcvt s6, d6",
"str s6, [x9, #4]",
"ldr w9, [x8, #112]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d3, d3, d5",
"fcvt s3, d3",
"str s3, [x9, #8]",
@@ -5541,13 +5541,13 @@
"fsub d5, d5, d6",
"fcvt s7, d5",
"str s7, [x6, #20]",
"strb w20, [x28, #1019]",
"str d2, [x21, #1040]",
"str d6, [x22, #1040]",
"str d5, [x13, #1040]",
"str d4, [x12, #1040]",
"str d3, [x23, #1040]",
"ldrb w21, [x28, #1186]",
"strb w20, [x28, #1051]",
"str d2, [x21, #1056]",
"str d6, [x22, #1056]",
"str d5, [x13, #1056]",
"str d4, [x12, #1056]",
"str d3, [x23, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w22, w22, w20",
"orr w21, w21, w22",
@@ -5556,7 +5556,7 @@
"mov w22, #0xf0f0",
"lsr w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
},
"Block6": {
@@ -6510,13 +6510,13 @@
"str s8, [x8, #32]",
"ldur s8, [x9, #-12]",
"str s8, [x8, #28]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s2, d2",
"str s2, [x8, #24]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s2, d3",
"str s2, [x8, #20]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s2, d4",
"str s2, [x8, #16]",
"fcvt s2, d5",
@@ -6529,7 +6529,7 @@
"mov w20, #0x462",
"movk w20, #0x1, lsl #16",
"str w20, [x8, #-4]!",
"strb wzr, [x28, #1186]"
"strb wzr, [x28, #1202]"
]
},
"Block7": {
@@ -7499,13 +7499,13 @@
"str s8, [x8, #32]",
"ldur s8, [x9, #-12]",
"str s8, [x8, #28]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s2, d2",
"str s2, [x8, #24]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s2, d3",
"str s2, [x8, #20]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fcvt s2, d4",
"str s2, [x8, #16]",
"fcvt s2, d5",
@@ -7518,7 +7518,7 @@
"mov w20, #0x46f",
"movk w20, #0x1, lsl #16",
"str w20, [x8, #-4]!",
"strb wzr, [x28, #1186]"
"strb wzr, [x28, #1202]"
]
},
"Block8": {
@@ -7760,9 +7760,9 @@
"ExpectedArm64ASM": [
"ldr s2, [x8, #64]",
"fcvt d2, s2",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr d3, [x21, #1040]",
"ldr d3, [x21, #1056]",
"fadd d2, d3, d2",
"add w5, w7, w7, lsl #1",
"add w10, w5, w7, lsl #1",
@@ -7891,7 +7891,7 @@
"add w15, w4, w7, lsl #2",
"fcvt s7, d7",
"stur s7, [x15, #-4]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d4, d4, d6",
"add w15, w4, w5, lsl #2",
"fcvt s4, d4",
@@ -8031,7 +8031,7 @@
"add w15, w4, w7, lsl #2",
"fcvt s7, d7",
"str s7, [x15, #4]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d4, d4, d6",
"add w15, w4, w5, lsl #2",
"fcvt s4, d4",
@@ -8084,7 +8084,7 @@
"add w15, w4, w11, lsl #2",
"fcvt s7, d7",
"str s7, [x15]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d4, d5, d4",
"fmul d4, d4, d6",
"add w15, w4, w11, lsl #2",
@@ -8167,7 +8167,7 @@
"add w15, w4, w7, lsl #2",
"fcvt s7, d7",
"str s7, [x15, #12]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d4, d4, d6",
"add w15, w4, w5, lsl #2",
"fcvt s4, d4",
@@ -8194,12 +8194,12 @@
"add w15, w4, w10, lsl #2",
"fcvt s8, d6",
"str s8, [x15, #8]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d3, d3, d5",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d2, d2, d4",
"fadd d2, d3, d2",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"add w15, w4, w10, lsl #2",
"fcvt s2, d2",
"str s2, [x15, #12]",
@@ -8241,20 +8241,20 @@
"adds w26, w8, #0x74 (116)",
"cfinv",
"mov x8, x26",
"strb w20, [x28, #1019]",
"str d7, [x22, #1040]",
"str d6, [x14, #1040]",
"str d5, [x13, #1040]",
"str d4, [x12, #1040]",
"str d3, [x23, #1040]",
"str d2, [x21, #1040]",
"ldrb w21, [x28, #1186]",
"strb w20, [x28, #1051]",
"str d7, [x22, #1056]",
"str d6, [x14, #1056]",
"str d5, [x13, #1056]",
"str d4, [x12, #1056]",
"str d3, [x23, #1056]",
"str d2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0xfcfc",
"lsr w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
},
"Block9": {
@@ -8487,9 +8487,9 @@
"ExpectedArm64ASM": [
"ldr s2, [x8, #64]",
"fcvt d2, s2",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr d3, [x21, #1040]",
"ldr d3, [x21, #1056]",
"fadd d2, d3, d2",
"add w5, w7, w7, lsl #1",
"add w10, w5, w7, lsl #1",
@@ -8617,7 +8617,7 @@
"add w15, w4, w7, lsl #2",
"fcvt s7, d7",
"stur s7, [x15, #-4]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d4, d4, d6",
"add w15, w4, w5, lsl #2",
"fcvt s4, d4",
@@ -8756,7 +8756,7 @@
"add w15, w4, w7, lsl #2",
"fcvt s7, d7",
"str s7, [x15, #4]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d4, d4, d6",
"add w15, w4, w5, lsl #2",
"fcvt s4, d4",
@@ -8809,7 +8809,7 @@
"add w15, w4, w11, lsl #2",
"fcvt s7, d7",
"str s7, [x15]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d4, d5, d4",
"fmul d4, d4, d6",
"add w15, w4, w11, lsl #2",
@@ -8891,7 +8891,7 @@
"add w15, w4, w7, lsl #2",
"fcvt s7, d7",
"str s7, [x15, #12]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fsub d4, d4, d6",
"add w15, w4, w5, lsl #2",
"fcvt s4, d4",
@@ -8918,12 +8918,12 @@
"add w15, w4, w10, lsl #2",
"fcvt s8, d6",
"str s8, [x15, #8]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d3, d3, d5",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"fmul d2, d2, d4",
"fadd d2, d3, d2",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1049]",
"add w15, w4, w10, lsl #2",
"fcvt s2, d2",
"str s2, [x15, #12]",
@@ -8965,20 +8965,20 @@
"adds w26, w8, #0x74 (116)",
"cfinv",
"mov x8, x26",
"strb w20, [x28, #1019]",
"str d7, [x22, #1040]",
"str d6, [x14, #1040]",
"str d5, [x13, #1040]",
"str d4, [x12, #1040]",
"str d3, [x23, #1040]",
"str d2, [x21, #1040]",
"ldrb w21, [x28, #1186]",
"strb w20, [x28, #1051]",
"str d7, [x22, #1056]",
"str d6, [x14, #1056]",
"str d5, [x13, #1056]",
"str d4, [x12, #1056]",
"str d3, [x23, #1056]",
"str d2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0xfcfc",
"lsr w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
},
"Block10": {
@@ -9993,14 +9993,14 @@
"movk w20, #0x1, lsl #16",
"str w20, [x8, #-4]!",
"cfinv",
"ldrb w21, [x28, #1019]",
"ldrb w22, [x28, #1186]",
"ldrb w21, [x28, #1051]",
"ldrb w22, [x28, #1202]",
"mov w23, #0x8",
"sub w21, w23, w21",
"mov w23, #0xe0e0",
"lsr w21, w23, w21",
"bic w21, w22, w21",
"strb w21, [x28, #1186]"
"strb w21, [x28, #1202]"
]
}
}
unittests/InstructionCountCI/FlagM/x87_f64.json
+2085 -2085
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/H0F38.json
+87 -87
View File
@@ -18,16 +18,16 @@
"NP 0x0f 0x38 0x00"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"movi v4.16b, #0x87",
"and v3.8b, v3.8b, v4.8b",
"tbl v2.8b, {v2.16b}, v3.8b",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pshufb xmm0, xmm1": {
@@ -47,14 +47,14 @@
"NP 0x0f 0x38 0x01"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"addp v2.4h, v3.4h, v2.4h",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"phaddw xmm0, xmm1": {
@@ -72,14 +72,14 @@
"NP 0x0f 0x38 0x02"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"addp v2.2s, v3.2s, v2.2s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"phaddd xmm0, xmm1": {
@@ -97,16 +97,16 @@
"NP 0x0f 0x38 0x03"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sqadd v2.8h, v4.8h, v2.8h",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"phaddsw xmm0, xmm1": {
@@ -126,19 +126,19 @@
"NP 0x0f 0x38 0x04"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"uxtl v2.8h, v2.8b",
"sxtl v3.8h, v3.8b",
"smull v4.4s, v2.4h, v3.4h",
"smull2 v2.4s, v2.8h, v3.8h",
"addp v2.4s, v4.4s, v2.4s",
"sqxtn v2.4h, v2.4s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pmaddubsw xmm0, xmm1": {
@@ -168,16 +168,16 @@
"NP 0x0f 0x38 0x05"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sub v2.8h, v4.8h, v2.8h",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"phsubw xmm0, xmm1": {
@@ -197,16 +197,16 @@
"NP 0x0f 0x38 0x06"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"uzp1 v4.2s, v2.2s, v3.2s",
"uzp2 v2.2s, v2.2s, v3.2s",
"sub v2.4s, v4.4s, v2.4s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"phsubd xmm0, xmm1": {
@@ -226,16 +226,16 @@
"NP 0x0f 0x38 0x07"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sqsub v2.8h, v4.8h, v2.8h",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"phsubsw xmm0, xmm1": {
@@ -255,16 +255,16 @@
"NP 0x0f 0x38 0x08"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"sqshl v2.8b, v2.8b, #7",
"srshr v2.8b, v2.8b, #7",
"mul v2.16b, v3.16b, v2.16b",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psignb xmm0, xmm1": {
@@ -284,16 +284,16 @@
"NP 0x0f 0x38 0x09"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"sqshl v2.4h, v2.4h, #15",
"srshr v2.4h, v2.4h, #15",
"mul v2.8h, v3.8h, v2.8h",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psignw xmm0, xmm1": {
@@ -313,16 +313,16 @@
"NP 0x0f 0x38 0x0a"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"sqshl v2.2s, v2.2s, #31",
"srshr v2.2s, v2.2s, #31",
"mul v2.4s, v3.4s, v2.4s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psignd xmm0, xmm1": {
@@ -343,18 +343,18 @@
"NP 0x0f 0x38 0x0b"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"smull v2.4s, v2.4h, v3.4h",
"sshr v2.4s, v2.4s, #14",
"movi v3.4s, #0x1, lsl #0",
"add v2.4s, v2.4s, v3.4s",
"shrn v2.4h, v2.4s, #1",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pmulhrsw xmm0, xmm1": {
@@ -465,13 +465,13 @@
"NP 0x0f 0x38 0x1c"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"abs v2.16b, v2.16b",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pabsb xmm0, xmm1": {
@@ -489,13 +489,13 @@
"NP 0x0f 0x38 0x1d"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"abs v2.8h, v2.8h",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pabsw xmm0, xmm1": {
@@ -513,13 +513,13 @@
"NP 0x0f 0x38 0x1e"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"abs v2.4s, v2.4s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pabsd xmm0, xmm1": {
unittests/InstructionCountCI/H0F3A.json
+16 -16
View File
@@ -20,12 +20,12 @@
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"palignr mm0, mm1, 1": {
@@ -34,14 +34,14 @@
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"ldr d3, [x28, #1056]",
"ext v2.8b, v2.8b, v3.8b, #1",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"palignr mm0, mm1, 255": {
@@ -50,12 +50,12 @@
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"strb w20, [x28, #1202]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"roundps xmm0, xmm1, 00000000b": {
@@ -474,7 +474,7 @@
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2656]",
"ldr x0, [x28, #2672]",
"ldr q2, [x0, #3440]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
unittests/InstructionCountCI/Primary.json
+111 -111
View File
@@ -2150,7 +2150,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #930]",
"ldrh w20, [x28, #962]",
"bfxil x4, x20, #0, #16"
]
},
@@ -2158,21 +2158,21 @@
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #930]"
"ldrh w4, [x28, #962]"
]
},
"mov rax, cs": {
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #930]"
"ldrh w4, [x28, #962]"
]
},
"mov ax, es": {
"ExpectedInstructionCount": 2,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #928]",
"ldrh w20, [x28, #960]",
"bfxil x4, x20, #0, #16"
]
},
@@ -2180,21 +2180,21 @@
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #928]"
"ldrh w4, [x28, #960]"
]
},
"mov rax, es": {
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #928]"
"ldrh w4, [x28, #960]"
]
},
"mov ax, ss": {
"ExpectedInstructionCount": 2,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #932]",
"ldrh w20, [x28, #964]",
"bfxil x4, x20, #0, #16"
]
},
@@ -2202,21 +2202,21 @@
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #932]"
"ldrh w4, [x28, #964]"
]
},
"mov rax, ss": {
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #932]"
"ldrh w4, [x28, #964]"
]
},
"mov ax, ds": {
"ExpectedInstructionCount": 2,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #934]",
"ldrh w20, [x28, #966]",
"bfxil x4, x20, #0, #16"
]
},
@@ -2224,14 +2224,14 @@
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #934]"
"ldrh w4, [x28, #966]"
]
},
"mov rax, ds": {
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #934]"
"ldrh w4, [x28, #966]"
]
},
"mov ax, gs": {
@@ -2478,17 +2478,17 @@
"Comment": "0x8e",
"ExpectedArm64ASM": [
"uxth w20, w4",
"strh w20, [x28, #928]",
"strh w20, [x28, #960]",
"ubfx w21, w20, #2, #1",
"and w20, w20, #0xfff8",
"add x0, x28, x21, lsl #3",
"ldr x21, [x0, #1168]",
"ldr x21, [x0, #1184]",
"ldr x20, [x21, w20, uxtw]",
"lsr x21, x20, #32",
"and w22, w21, #0xff000000",
"orr w20, w22, w20, lsr #16",
"bfi w20, w21, #16, #8",
"str w20, [x28, #944]"
"str w20, [x28, #976]"
]
},
"mov ss, ax": {
@@ -2496,17 +2496,17 @@
"Comment": "0x8e",
"ExpectedArm64ASM": [
"uxth w20, w4",
"strh w20, [x28, #932]",
"strh w20, [x28, #964]",
"ubfx w21, w20, #2, #1",
"and w20, w20, #0xfff8",
"add x0, x28, x21, lsl #3",
"ldr x21, [x0, #1168]",
"ldr x21, [x0, #1184]",
"ldr x20, [x21, w20, uxtw]",
"lsr x21, x20, #32",
"and w22, w21, #0xff000000",
"orr w20, w22, w20, lsr #16",
"bfi w20, w21, #16, #8",
"str w20, [x28, #952]"
"str w20, [x28, #984]"
]
},
"mov ds, ax": {
@@ -2514,17 +2514,17 @@
"Comment": "0x8e",
"ExpectedArm64ASM": [
"uxth w20, w4",
"strh w20, [x28, #934]",
"strh w20, [x28, #966]",
"ubfx w21, w20, #2, #1",
"and w20, w20, #0xfff8",
"add x0, x28, x21, lsl #3",
"ldr x21, [x0, #1168]",
"ldr x21, [x0, #1184]",
"ldr x20, [x21, w20, uxtw]",
"lsr x21, x20, #32",
"and w22, w21, #0xff000000",
"orr w20, w22, w20, lsr #16",
"bfi w20, w21, #16, #8",
"str w20, [x28, #956]"
"str w20, [x28, #988]"
]
},
"mov gs, ax": {
@@ -2650,30 +2650,30 @@
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
"ldrb w21, [x28, #984]",
"ldrb w21, [x28, #1016]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #985]",
"ldrb w21, [x28, #1017]",
"orr x20, x20, x21, lsl #9",
"ldrsb x21, [x28, #986]",
"ldrsb x21, [x28, #1018]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset x21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #988]",
"ldrb w21, [x28, #1020]",
"orr x20, x20, x21, lsl #12",
"ldrb w21, [x28, #990]",
"ldrb w21, [x28, #1022]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #992]",
"ldrb w21, [x28, #1024]",
"orr x20, x20, x21, lsl #16",
"ldrb w21, [x28, #993]",
"ldrb w21, [x28, #1025]",
"orr x20, x20, x21, lsl #17",
"ldrb w21, [x28, #994]",
"ldrb w21, [x28, #1026]",
"orr x20, x20, x21, lsl #18",
"ldrb w21, [x28, #995]",
"ldrb w21, [x28, #1027]",
"orr x20, x20, x21, lsl #19",
"ldrb w21, [x28, #996]",
"ldrb w21, [x28, #1028]",
"orr x20, x20, x21, lsl #20",
"ldrb w21, [x28, #997]",
"ldrb w21, [x28, #1029]",
"orr x20, x20, x21, lsl #21",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
@@ -2695,30 +2695,30 @@
"eor x21, x27, x26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
"ldrb w21, [x28, #984]",
"ldrb w21, [x28, #1016]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #985]",
"ldrb w21, [x28, #1017]",
"orr x20, x20, x21, lsl #9",
"ldrsb x21, [x28, #986]",
"ldrsb x21, [x28, #1018]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset x21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #988]",
"ldrb w21, [x28, #1020]",
"orr x20, x20, x21, lsl #12",
"ldrb w21, [x28, #990]",
"ldrb w21, [x28, #1022]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #992]",
"ldrb w21, [x28, #1024]",
"orr x20, x20, x21, lsl #16",
"ldrb w21, [x28, #993]",
"ldrb w21, [x28, #1025]",
"orr x20, x20, x21, lsl #17",
"ldrb w21, [x28, #994]",
"ldrb w21, [x28, #1026]",
"orr x20, x20, x21, lsl #18",
"ldrb w21, [x28, #995]",
"ldrb w21, [x28, #1027]",
"orr x20, x20, x21, lsl #19",
"ldrb w21, [x28, #996]",
"ldrb w21, [x28, #1028]",
"orr x20, x20, x21, lsl #20",
"ldrb w21, [x28, #997]",
"ldrb w21, [x28, #1029]",
"orr x20, x20, x21, lsl #21",
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
@@ -2749,37 +2749,37 @@
"ubfx x20, x27, #7, #1",
"bfi w22, w20, #31, #1",
"ubfx w20, w27, #8, #1",
"ldrb w21, [x28, #984]",
"ldrb w21, [x28, #1016]",
"and w21, w21, #0xfffffffe",
"mov w23, #0x1",
"cmp x20, #0x0 (0)",
"csel x20, x21, x23, eq",
"strb w20, [x28, #984]",
"strb w20, [x28, #1016]",
"ubfx w20, w27, #9, #1",
"strb w20, [x28, #985]",
"strb w20, [x28, #1017]",
"ubfx w20, w27, #10, #1",
"sub x20, x23, x20, lsl #1",
"ubfx x21, x27, #11, #1",
"bfi w22, w21, #28, #1",
"ubfx w21, w27, #12, #1",
"strb w21, [x28, #988]",
"strb w21, [x28, #1020]",
"ubfx w21, w27, #14, #1",
"strb w21, [x28, #990]",
"strb w21, [x28, #1022]",
"ubfx w21, w27, #16, #1",
"strb w21, [x28, #992]",
"strb w21, [x28, #1024]",
"ubfx w21, w27, #17, #1",
"strb w21, [x28, #993]",
"strb w21, [x28, #1025]",
"ubfx w21, w27, #18, #1",
"strb w21, [x28, #994]",
"strb w21, [x28, #1026]",
"ubfx w21, w27, #19, #1",
"strb w21, [x28, #995]",
"strb w21, [x28, #1027]",
"ubfx w21, w27, #20, #1",
"strb w21, [x28, #996]",
"strb w21, [x28, #1028]",
"ubfx w21, w27, #21, #1",
"strb w21, [x28, #997]",
"strb w21, [x28, #1029]",
"mov w21, #0x10001",
"msr nzcv, x22",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"sahf": {
@@ -2872,7 +2872,7 @@
"ExpectedArm64ASM": [
"ldrb w20, [x10]",
"strb w20, [x11]",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x10, x10, x20",
"add x11, x11, x20"
]
@@ -2885,7 +2885,7 @@
"ExpectedArm64ASM": [
"ldrh w20, [x10]",
"strh w20, [x11]",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #1",
"add x10, x10, x20",
"add x11, x11, x20"
@@ -2899,7 +2899,7 @@
"ExpectedArm64ASM": [
"ldr w20, [x10]",
"str w20, [x11]",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #2",
"add x10, x10, x20",
"add x11, x11, x20"
@@ -2913,7 +2913,7 @@
"ExpectedArm64ASM": [
"ldr x20, [x10]",
"str x20, [x11]",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #3",
"add x10, x10, x20",
"add x11, x11, x20"
@@ -2923,7 +2923,7 @@
"ExpectedInstructionCount": 83,
"Comment": "0xa4",
"ExpectedArm64ASM": [
"ldrsb x22, [x28, #986]",
"ldrsb x22, [x28, #1018]",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
@@ -3012,7 +3012,7 @@
"ExpectedInstructionCount": 83,
"Comment": "0xa5",
"ExpectedArm64ASM": [
"ldrsb x22, [x28, #986]",
"ldrsb x22, [x28, #1018]",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
@@ -3101,7 +3101,7 @@
"ExpectedInstructionCount": 83,
"Comment": "0xa5",
"ExpectedArm64ASM": [
"ldrsb x22, [x28, #986]",
"ldrsb x22, [x28, #1018]",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
@@ -3190,7 +3190,7 @@
"ExpectedInstructionCount": 83,
"Comment": "0xa5",
"ExpectedArm64ASM": [
"ldrsb x22, [x28, #986]",
"ldrsb x22, [x28, #1018]",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
@@ -3287,7 +3287,7 @@
"lsl w0, w21, #24",
"cmp w0, w20, lsl #24",
"sub w26, w21, w20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x11, x11, x20",
"add x10, x10, x20"
]
@@ -3304,7 +3304,7 @@
"lsl w0, w21, #16",
"cmp w0, w20, lsl #16",
"sub w26, w21, w20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #1",
"add x11, x11, x20",
"add x10, x10, x20"
@@ -3320,7 +3320,7 @@
"ldr w21, [x10]",
"eor x27, x21, x20",
"subs w26, w21, w20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #2",
"add x11, x11, x20",
"add x10, x10, x20"
@@ -3336,7 +3336,7 @@
"ldr x21, [x10]",
"eor x27, x21, x20",
"subs x26, x21, x20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsl x20, x20, #3",
"add x11, x11, x20",
"add x10, x10, x20"
@@ -3347,7 +3347,7 @@
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x7, #+0x64",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -3378,7 +3378,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x7, #+0x64",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -3409,7 +3409,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x7, #+0x5c",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -3438,7 +3438,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x7, #+0x5c",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -3467,7 +3467,7 @@
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x7, #+0x64",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -3498,7 +3498,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x7, #+0x64",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -3529,7 +3529,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x7, #+0x5c",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -3558,7 +3558,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x7, #+0x5c",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -3659,7 +3659,7 @@
"Comment": "0xaa",
"ExpectedArm64ASM": [
"strb w4, [x11]",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x11, x11, x20"
]
},
@@ -3668,7 +3668,7 @@
"Comment": "0xab",
"ExpectedArm64ASM": [
"strh w4, [x11]",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x11, x11, x20, lsl #1"
]
},
@@ -3677,7 +3677,7 @@
"Comment": "0xab",
"ExpectedArm64ASM": [
"str w4, [x11]",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x11, x11, x20, lsl #2"
]
},
@@ -3686,7 +3686,7 @@
"Comment": "0xab",
"ExpectedArm64ASM": [
"str x4, [x11]",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x11, x11, x20, lsl #3"
]
},
@@ -3695,7 +3695,7 @@
"Comment": "0xaa",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"ldrsb x21, [x28, #986]",
"ldrsb x21, [x28, #1018]",
"mov x0, x7",
"mov x1, x11",
"tbnz w21, #1, #+0x64",
@@ -3756,7 +3756,7 @@
"Comment": "0xab",
"ExpectedArm64ASM": [
"uxth w20, w4",
"ldrsb x21, [x28, #986]",
"ldrsb x21, [x28, #1018]",
"mov x0, x7",
"mov x1, x11",
"tbnz w21, #1, #+0x64",
@@ -3817,7 +3817,7 @@
"Comment": "0xab",
"ExpectedArm64ASM": [
"mov w20, w4",
"ldrsb x21, [x28, #986]",
"ldrsb x21, [x28, #1018]",
"mov x0, x7",
"mov x1, x11",
"tbnz w21, #1, #+0x64",
@@ -3881,7 +3881,7 @@
"0xab"
],
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"mov x0, x7",
"mov x1, x11",
"tbnz w20, #1, #+0x64",
@@ -3943,7 +3943,7 @@
"ExpectedArm64ASM": [
"ldrb w20, [x10]",
"bfxil x4, x20, #0, #8",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x10, x10, x20"
]
},
@@ -3953,7 +3953,7 @@
"ExpectedArm64ASM": [
"ldrh w20, [x10]",
"bfxil x4, x20, #0, #16",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x10, x10, x20, lsl #1"
]
},
@@ -3962,7 +3962,7 @@
"Comment": "0xad",
"ExpectedArm64ASM": [
"ldr w4, [x10]",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x10, x10, x20, lsl #2"
]
},
@@ -3971,7 +3971,7 @@
"Comment": "0xad",
"ExpectedArm64ASM": [
"ldr x4, [x10]",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x10, x10, x20, lsl #3"
]
},
@@ -3979,7 +3979,7 @@
"ExpectedInstructionCount": 17,
"Comment": "0xac",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x20",
@@ -4002,7 +4002,7 @@
"ExpectedInstructionCount": 17,
"Comment": "0xad",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x20",
@@ -4025,7 +4025,7 @@
"ExpectedInstructionCount": 15,
"Comment": "0xad",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x1c",
@@ -4046,7 +4046,7 @@
"ExpectedInstructionCount": 15,
"Comment": "0xad",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x1c",
@@ -4072,7 +4072,7 @@
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, w20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x11, x11, x20"
]
},
@@ -4085,7 +4085,7 @@
"lsl w0, w4, #16",
"cmp w0, w20, lsl #16",
"sub w26, w4, w20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x11, x11, x20, lsl #1"
]
},
@@ -4096,7 +4096,7 @@
"ldr w20, [x11]",
"eor x27, x4, x20",
"subs w26, w4, w20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x11, x11, x20, lsl #2"
]
},
@@ -4107,7 +4107,7 @@
"ldr x20, [x11]",
"eor x27, x4, x20",
"subs x26, x4, x20",
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"add x11, x11, x20, lsl #3"
]
},
@@ -4115,7 +4115,7 @@
"ExpectedInstructionCount": 23,
"Comment": "0xae",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x2c",
@@ -4144,7 +4144,7 @@
"ExpectedInstructionCount": 23,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x2c",
@@ -4173,7 +4173,7 @@
"ExpectedInstructionCount": 19,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -4198,7 +4198,7 @@
"ExpectedInstructionCount": 19,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -4223,7 +4223,7 @@
"ExpectedInstructionCount": 23,
"Comment": "0xae",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x2c",
@@ -4252,7 +4252,7 @@
"ExpectedInstructionCount": 23,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x2c",
@@ -4281,7 +4281,7 @@
"ExpectedInstructionCount": 19,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -4306,7 +4306,7 @@
"ExpectedInstructionCount": 19,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #986]",
"ldrsb x20, [x28, #1018]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@@ -4482,17 +4482,17 @@
"ldp w21, w22, [x20], #8",
"mov w23, #0x1234",
"add x8, x20, x23",
"strh w22, [x28, #930]",
"strh w22, [x28, #962]",
"ubfx w20, w22, #2, #1",
"and w22, w22, #0xfff8",
"add x0, x28, x20, lsl #3",
"ldr x20, [x0, #1168]",
"ldr x20, [x0, #1184]",
"ldr x20, [x20, w22, uxtw]",
"lsr x22, x20, #32",
"and w23, w22, #0xff000000",
"orr w20, w23, w20, lsr #16",
"bfi w20, w22, #16, #8",
"str w20, [x28, #948]"
"str w20, [x28, #980]"
]
},
"retf": {
@@ -4500,17 +4500,17 @@
"Comment": "0xcb",
"ExpectedArm64ASM": [
"ldp w20, w21, [x8], #8",
"strh w21, [x28, #930]",
"strh w21, [x28, #962]",
"ubfx w22, w21, #2, #1",
"and w21, w21, #0xfff8",
"add x0, x28, x22, lsl #3",
"ldr x22, [x0, #1168]",
"ldr x22, [x0, #1184]",
"ldr x21, [x22, w21, uxtw]",
"lsr x22, x21, #32",
"and w23, w22, #0xff000000",
"orr w21, w23, w21, lsr #16",
"bfi w21, w22, #16, #8",
"str w21, [x28, #948]"
"str w21, [x28, #980]"
]
},
"cmc": {
@@ -4557,7 +4557,7 @@
"Comment": "0xfc",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
},
"std": {
@@ -4565,7 +4565,7 @@
"Comment": "0xfd",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]"
"strb w20, [x28, #1018]"
]
}
}
unittests/InstructionCountCI/PrimaryGroup.json
+7 -7
View File
@@ -2979,21 +2979,21 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"ldrh w21, [x8, #4]",
"ldrh w22, [x28, #930]",
"ldrh w22, [x28, #962]",
"mov w23, #0x4",
"movk w23, #0x1, lsl #16",
"stp x23, x22, [x8, #-16]!",
"strh w21, [x28, #930]",
"strh w21, [x28, #962]",
"ubfx w22, w21, #2, #1",
"and w21, w21, #0xfff8",
"add x0, x28, x22, lsl #3",
"ldr x22, [x0, #1168]",
"ldr x22, [x0, #1184]",
"ldr x21, [x22, w21, uxtw]",
"lsr x22, x21, #32",
"and w23, w22, #0xff000000",
"orr w21, w23, w21, lsr #16",
"bfi w21, w22, #16, #8",
"str w21, [x28, #948]"
"str w21, [x28, #980]"
]
},
"push rax": {
@@ -3009,17 +3009,17 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"ldrh w21, [x8, #4]",
"strh w21, [x28, #930]",
"strh w21, [x28, #962]",
"ubfx w22, w21, #2, #1",
"and w21, w21, #0xfff8",
"add x0, x28, x22, lsl #3",
"ldr x22, [x0, #1168]",
"ldr x22, [x0, #1184]",
"ldr x21, [x22, w21, uxtw]",
"lsr x22, x21, #32",
"and w23, w22, #0xff000000",
"orr w21, w23, w21, lsr #16",
"bfi w21, w22, #16, #8",
"str w21, [x28, #948]"
"str w21, [x28, #980]"
]
},
"mov byte [rax], 0": {
unittests/InstructionCountCI/Primary_32Bit.json
+16 -16
View File
@@ -15,7 +15,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x06",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #928]",
"ldrh w20, [x28, #960]",
"str w20, [x8, #-4]!"
]
},
@@ -24,24 +24,24 @@
"Comment": "0x07",
"ExpectedArm64ASM": [
"ldr w20, [x8], #4",
"strh w20, [x28, #928]",
"strh w20, [x28, #960]",
"ubfx w21, w20, #2, #1",
"and w20, w20, #0xfff8",
"add x0, x28, x21, lsl #3",
"ldr x21, [x0, #1168]",
"ldr x21, [x0, #1184]",
"ldr x20, [x21, w20, uxtw]",
"lsr x21, x20, #32",
"and w22, w21, #0xff000000",
"orr w20, w22, w20, lsr #16",
"bfi w20, w21, #16, #8",
"str w20, [x28, #944]"
"str w20, [x28, #976]"
]
},
"push cs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0e",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #930]",
"ldrh w20, [x28, #962]",
"str w20, [x8, #-4]!"
]
},
@@ -49,7 +49,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x16",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #932]",
"ldrh w20, [x28, #964]",
"str w20, [x8, #-4]!"
]
},
@@ -58,26 +58,26 @@
"Comment": "0x17",
"ExpectedArm64ASM": [
"ldr w20, [x8], #4",
"ldrb w21, [x28, #984]",
"ldrb w21, [x28, #1016]",
"mov w22, #0x1",
"and w21, w21, #0x1",
"ldrb w23, [x28, #984]",
"ldrb w23, [x28, #1016]",
"and w23, w23, #0xfffffffe",
"mrs x12, nzcv",
"cmp x21, #0x0 (0)",
"csel x21, x23, x22, eq",
"strb w21, [x28, #984]",
"strh w20, [x28, #932]",
"strb w21, [x28, #1016]",
"strh w20, [x28, #964]",
"ubfx w21, w20, #2, #1",
"and w20, w20, #0xfff8",
"add x0, x28, x21, lsl #3",
"ldr x21, [x0, #1168]",
"ldr x21, [x0, #1184]",
"ldr x20, [x21, w20, uxtw]",
"lsr x21, x20, #32",
"and w22, w21, #0xff000000",
"orr w20, w22, w20, lsr #16",
"bfi w20, w21, #16, #8",
"str w20, [x28, #952]",
"str w20, [x28, #984]",
"msr nzcv, x12"
]
},
@@ -85,7 +85,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x1e",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #934]",
"ldrh w20, [x28, #966]",
"str w20, [x8, #-4]!"
]
},
@@ -94,17 +94,17 @@
"Comment": "0x1f",
"ExpectedArm64ASM": [
"ldr w20, [x8], #4",
"strh w20, [x28, #934]",
"strh w20, [x28, #966]",
"ubfx w21, w20, #2, #1",
"and w20, w20, #0xfff8",
"add x0, x28, x21, lsl #3",
"ldr x21, [x0, #1168]",
"ldr x21, [x0, #1184]",
"ldr x20, [x21, w20, uxtw]",
"lsr x21, x20, #32",
"and w22, w21, #0xff000000",
"orr w20, w22, w20, lsr #16",
"bfi w20, w21, #16, #8",
"str w20, [x28, #956]"
"str w20, [x28, #988]"
]
},
"daa": {
unittests/InstructionCountCI/RPRES/DDD.json
+20 -20
View File
@@ -17,15 +17,15 @@
"0x0f 0x0f 0x86"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"frecpe v0.2s, v2.2s",
"frecps v1.2s, v0.2s, v2.2s",
"fmul v2.2s, v0.2s, v1.2s",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrsqrtv mm0, mm1": {
@@ -34,10 +34,10 @@
"0x0f 0x0f 0x87"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"fabs v3.4s, v2.4s",
"frsqrte v0.2s, v3.2s",
"fmul v1.2s, v0.2s, v0.2s",
@@ -45,8 +45,8 @@
"fmul v3.2s, v0.2s, v1.2s",
"movi v0.2s, #0x80, lsl #24",
"bit v3.8b, v2.8b, v0.8b",
"str d3, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d3, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrcp mm0, mm1": {
@@ -55,16 +55,16 @@
"0x0f 0x0f 0x96"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"frecpe s0, s2",
"frecps s1, s0, s2",
"fmul s2, s0, s1",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pfrsqrt mm0, mm1": {
@@ -73,10 +73,10 @@
"0x0f 0x0f 0x97"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1072]",
"fabs v3.4s, v2.4s",
"frsqrte v0.2s, v3.2s",
"fmul v1.2s, v0.2s, v0.2s",
@@ -85,8 +85,8 @@
"movi v0.2s, #0x80, lsl #24",
"bit v3.8b, v2.8b, v0.8b",
"dup v2.2s, v3.s[0]",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
}
}
unittests/InstructionCountCI/SSE42_Strings.json
+8 -8
View File
@@ -41,8 +41,8 @@
"0x66 0x0f 0x3A 0x60"
],
"ExpectedArm64ASM": [
"ldr x3, [x28, #2264]",
"ldr x0, [x28, #2272]",
"ldr x3, [x28, #2280]",
"ldr x0, [x28, #2288]",
"stp x0, x30, [sp, #-16]!",
"mov x0, x4",
"mov x1, x5",
@@ -66,8 +66,8 @@
"0x66 0x0f 0x3A 0x61"
],
"ExpectedArm64ASM": [
"ldr x3, [x28, #2264]",
"ldr x0, [x28, #2272]",
"ldr x3, [x28, #2280]",
"ldr x0, [x28, #2288]",
"stp x0, x30, [sp, #-16]!",
"mov x0, x4",
"mov x1, x5",
@@ -99,8 +99,8 @@
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w0, #0x0",
"ldr x1, [x28, #2280]",
"ldr x3, [x28, #2288]",
"ldr x1, [x28, #2296]",
"ldr x3, [x28, #2304]",
"blr x1",
"ldr x30, [sp], #16",
"mov w20, w0",
@@ -122,8 +122,8 @@
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w0, #0x0",
"ldr x1, [x28, #2280]",
"ldr x3, [x28, #2288]",
"ldr x1, [x28, #2296]",
"ldr x3, [x28, #2304]",
"blr x1",
"ldr x30, [sp], #16",
"mov w20, w0",
unittests/InstructionCountCI/Secondary.json
+540 -540
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/SecondaryGroup.json
+181 -181
View File
@@ -1028,11 +1028,11 @@
"Comment": "GROUP9 0xF3 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"str x25, [x28, #1024]",
"str w0, [x28, #1032]",
"str x25, [x28, #432]",
"str x8, [x28, #320]",
"mov w0, #0x100",
"str x0, [x28, #1456]",
"str x0, [x28, #1472]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
@@ -1040,11 +1040,11 @@
"svc #0x0",
"ldp w0, w1, [sp]",
"sub sp, sp, #0x10 (16)",
"ldr x25, [x28, #1024]",
"ldr w8, [x28, #1000]",
"ldr x25, [x28, #432]",
"ldr w8, [x28, #1032]",
"msr nzcv, x8",
"ldr x8, [x28, #320]",
"str xzr, [x28, #1456]",
"str xzr, [x28, #1472]",
"orr x20, x0, x1, lsl #12",
"mov w4, w20"
]
@@ -1054,11 +1054,11 @@
"Comment": "GROUP9 0xF3 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"str x25, [x28, #1024]",
"str w0, [x28, #1032]",
"str x25, [x28, #432]",
"str x8, [x28, #320]",
"mov w0, #0x100",
"str x0, [x28, #1456]",
"str x0, [x28, #1472]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
@@ -1066,11 +1066,11 @@
"svc #0x0",
"ldp w0, w1, [sp]",
"sub sp, sp, #0x10 (16)",
"ldr x25, [x28, #1024]",
"ldr w8, [x28, #1000]",
"ldr x25, [x28, #432]",
"ldr w8, [x28, #1032]",
"msr nzcv, x8",
"ldr x8, [x28, #320]",
"str xzr, [x28, #1456]",
"str xzr, [x28, #1472]",
"orr x20, x0, x1, lsl #12",
"mov w4, w20"
]
@@ -1086,13 +1086,13 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ushr v2.8h, v2.8h, #15",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrlw mm0, 16": {
@@ -1100,13 +1100,13 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrlw xmm0, 0": {
@@ -1142,13 +1142,13 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psraw mm0, 16": {
@@ -1156,13 +1156,13 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psraw xmm0, 0": {
@@ -1198,13 +1198,13 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"shl v2.8h, v2.8h, #15",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psllw mm0, 16": {
@@ -1212,13 +1212,13 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psllw xmm0, 0": {
@@ -1254,13 +1254,13 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ushr v2.4s, v2.4s, #31",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrld mm0, 32": {
@@ -1268,13 +1268,13 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrld xmm0, 0": {
@@ -1310,13 +1310,13 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrad mm0, 32": {
@@ -1324,13 +1324,13 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrad xmm0, 0": {
@@ -1366,13 +1366,13 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"shl v2.4s, v2.4s, #31",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pslld mm0, 32": {
@@ -1380,13 +1380,13 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pslld xmm0, 0": {
@@ -1422,13 +1422,13 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ushr v2.2d, v2.2d, #63",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrlq mm0, 64": {
@@ -1436,13 +1436,13 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrlq xmm0, 0": {
@@ -1501,13 +1501,13 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"shl v2.2d, v2.2d, #63",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psllq mm0, 64": {
@@ -1515,13 +1515,13 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psllq xmm0, 0": {
@@ -1550,61 +1550,61 @@
"ExpectedInstructionCount": 68,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #1184]",
"ldrh w20, [x28, #1200]",
"strh w20, [x4]",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"lsl x20, x20, #11",
"ldrb w21, [x28, #1016]",
"ldrb w21, [x28, #1048]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #1017]",
"ldrb w21, [x28, #1049]",
"orr x20, x20, x21, lsl #9",
"ldrb w21, [x28, #1018]",
"ldrb w21, [x28, #1050]",
"orr x20, x20, x21, lsl #10",
"ldrb w21, [x28, #1022]",
"ldrb w21, [x28, #1054]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #1008]",
"ldrb w21, [x28, #1040]",
"orr x20, x20, x21",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1186]",
"ldrb w20, [x28, #1202]",
"strb w20, [x4, #4]",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #32]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #48]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #64]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #80]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #96]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #112]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #128]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #144]",
"stp q16, q17, [x4, #160]",
"stp q18, q19, [x4, #192]",
@@ -1614,7 +1614,7 @@
"stp q26, q27, [x4, #320]",
"stp q28, q29, [x4, #352]",
"stp q30, q31, [x4, #384]",
"ldr w20, [x28, #940]",
"ldr w20, [x28, #972]",
"and w20, w20, #0xffc0",
"mov w21, #0xffff",
"stp w20, w21, [x4, #24]"
@@ -1624,14 +1624,14 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr w4, [x28, #968]"
"ldr w4, [x28, #1000]"
]
},
"rdfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr x4, [x28, #968]"
"ldr x4, [x28, #1000]"
]
},
"fxrstor [rax]": {
@@ -1639,34 +1639,34 @@
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"strh w20, [x28, #1184]",
"strh w20, [x28, #1200]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #1019]",
"strb w21, [x28, #1051]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w24, w20, #14, #1",
"ubfx w20, w20, #0, #1",
"strb w21, [x28, #1016]",
"strb w22, [x28, #1017]",
"strb w23, [x28, #1018]",
"strb w24, [x28, #1022]",
"strb w20, [x28, #1008]",
"strb w21, [x28, #1048]",
"strb w22, [x28, #1049]",
"strb w23, [x28, #1050]",
"strb w24, [x28, #1054]",
"strb w20, [x28, #1040]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1186]",
"strb w20, [x28, #1202]",
"ldp q2, q3, [x4, #32]",
"str q2, [x28, #1040]",
"str q3, [x28, #1056]",
"str q2, [x28, #1056]",
"str q3, [x28, #1072]",
"ldp q2, q3, [x4, #64]",
"str q2, [x28, #1072]",
"str q3, [x28, #1088]",
"str q2, [x28, #1088]",
"str q3, [x28, #1104]",
"ldp q2, q3, [x4, #96]",
"str q2, [x28, #1104]",
"str q3, [x28, #1120]",
"str q2, [x28, #1120]",
"str q3, [x28, #1136]",
"ldp q2, q3, [x4, #128]",
"str q2, [x28, #1136]",
"str q3, [x28, #1152]",
"str q2, [x28, #1152]",
"str q3, [x28, #1168]",
"ldp q16, q17, [x4, #160]",
"ldp q18, q19, [x4, #192]",
"ldp q20, q21, [x4, #224]",
@@ -1677,7 +1677,7 @@
"ldp q30, q31, [x4, #384]",
"ldr w20, [x4, #24]",
"and w20, w20, #0xffc0",
"str w20, [x28, #940]",
"str w20, [x28, #972]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
@@ -1692,14 +1692,14 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr w4, [x28, #960]"
"ldr w4, [x28, #992]"
]
},
"rdgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr x4, [x28, #960]"
"ldr x4, [x28, #992]"
]
},
"ldmxcsr [rax]": {
@@ -1708,7 +1708,7 @@
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"and w20, w20, #0xffc0",
"str w20, [x28, #940]",
"str w20, [x28, #972]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
@@ -1724,21 +1724,21 @@
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #968]"
"str x20, [x28, #1000]"
]
},
"wrfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"str x4, [x28, #968]"
"str x4, [x28, #1000]"
]
},
"stmxcsr [rax]": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"ldr w20, [x28, #940]",
"ldr w20, [x28, #972]",
"and w20, w20, #0xffc0",
"str w20, [x4]"
]
@@ -1748,14 +1748,14 @@
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #960]"
"str x20, [x28, #992]"
]
},
"wrgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"str x4, [x28, #960]"
"str x4, [x28, #992]"
]
},
"xsave [rax]": {
@@ -1765,61 +1765,61 @@
"ubfx x20, x4, #0, #1",
"cbnz x20, #+0x8",
"b #+0xe4",
"ldrh w20, [x28, #1184]",
"ldrh w20, [x28, #1200]",
"strh w20, [x4]",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"lsl x20, x20, #11",
"ldrb w21, [x28, #1016]",
"ldrb w21, [x28, #1048]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #1017]",
"ldrb w21, [x28, #1049]",
"orr x20, x20, x21, lsl #9",
"ldrb w21, [x28, #1018]",
"ldrb w21, [x28, #1050]",
"orr x20, x20, x21, lsl #10",
"ldrb w21, [x28, #1022]",
"ldrb w21, [x28, #1054]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #1008]",
"ldrb w21, [x28, #1040]",
"orr x20, x20, x21",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1186]",
"ldrb w20, [x28, #1202]",
"strb w20, [x4, #4]",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #32]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #48]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #64]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #80]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #96]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #112]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #128]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ldr q2, [x0, #1056]",
"str q2, [x4, #144]",
"ubfx x20, x4, #1, #1",
"cbnz x20, #+0x8",
@@ -1854,7 +1854,7 @@
"ubfx x20, x4, #1, #2",
"cbnz x20, #+0x8",
"b #+0x14",
"ldr w20, [x28, #940]",
"ldr w20, [x28, #972]",
"and w20, w20, #0xffc0",
"mov w21, #0xffff",
"stp w20, w21, [x4, #24]",
@@ -1879,46 +1879,45 @@
"cbnz x20, #+0x8",
"b #+0x7c",
"ldrh w20, [x4]",
"strh w20, [x28, #1184]",
"strh w20, [x28, #1200]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #1019]",
"strb w21, [x28, #1051]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w24, w20, #14, #1",
"ubfx w20, w20, #0, #1",
"strb w21, [x28, #1016]",
"strb w22, [x28, #1017]",
"strb w23, [x28, #1018]",
"strb w24, [x28, #1022]",
"strb w20, [x28, #1008]",
"strb w21, [x28, #1048]",
"strb w22, [x28, #1049]",
"strb w23, [x28, #1050]",
"strb w24, [x28, #1054]",
"strb w20, [x28, #1040]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1186]",
"strb w20, [x28, #1202]",
"ldp q2, q3, [x4, #32]",
"str q2, [x28, #1040]",
"str q3, [x28, #1056]",
"str q2, [x28, #1056]",
"str q3, [x28, #1072]",
"ldp q2, q3, [x4, #64]",
"str q2, [x28, #1072]",
"str q3, [x28, #1088]",
"str q2, [x28, #1088]",
"str q3, [x28, #1104]",
"ldp q2, q3, [x4, #96]",
"str q2, [x28, #1104]",
"str q3, [x28, #1120]",
"str q2, [x28, #1120]",
"str q3, [x28, #1136]",
"ldp q2, q3, [x4, #128]",
"str q2, [x28, #1136]",
"str q3, [x28, #1152]",
"str q2, [x28, #1152]",
"str q3, [x28, #1168]",
"b #+0x4c",
"mov w20, #0x37f",
"strh w20, [x28, #1184]",
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1186]",
"strb wzr, [x28, #1016]",
"strb wzr, [x28, #1017]",
"strb wzr, [x28, #1018]",
"strb wzr, [x28, #1022]",
"strb wzr, [x28, #1008]",
"strh w20, [x28, #1200]",
"strb wzr, [x28, #1051]",
"strb wzr, [x28, #1202]",
"strb wzr, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb wzr, [x28, #1050]",
"strb wzr, [x28, #1054]",
"strb wzr, [x28, #1040]",
"movi v2.2d, #0x0",
"str q2, [x28, #1040]",
"str q2, [x28, #1056]",
"str q2, [x28, #1072]",
"str q2, [x28, #1088]",
@@ -1926,6 +1925,7 @@
"str q2, [x28, #1120]",
"str q2, [x28, #1136]",
"str q2, [x28, #1152]",
"str q2, [x28, #1168]",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #1",
"cbnz x20, #+0x8",
@@ -1995,7 +1995,7 @@
"b #+0x34",
"ldr w20, [x4, #24]",
"and w20, w20, #0xffc0",
"str w20, [x28, #940]",
"str w20, [x28, #972]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
unittests/InstructionCountCI/SecondaryModRM.json
+8 -8
View File
@@ -25,8 +25,8 @@
"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x3], #64",
"stp x18, x30, [x3], #16",
"mrs x3, nzcv",
"str w3, [x28, #1000]",
"str x25, [x28, #1024]",
"str w3, [x28, #1032]",
"str x25, [x28, #432]",
"stp x4, x7, [x28, #288]",
"stp x5, x6, [x28, #304]",
"stp x8, x9, [x28, #320]",
@@ -36,19 +36,19 @@
"stp x16, x17, [x28, #384]",
"stp x19, x29, [x28, #400]",
"stp w26, w27, [x28, #16]",
"add x3, x28, #0x1a0 (416)",
"add x3, x28, #0x1c0 (448)",
"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x3], #64",
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x3], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64",
"mov w1, w7",
"ldr x0, [x28, #1512]",
"ldr x2, [x28, #1528]",
"ldr x0, [x28, #1528]",
"ldr x2, [x28, #1544]",
"blr x2",
"ldr x25, [x28, #1024]",
"ldr w4, [x28, #1000]",
"ldr x25, [x28, #432]",
"ldr w4, [x28, #1032]",
"msr nzcv, x4",
"add x4, x28, #0x1a0 (416)",
"add x4, x28, #0x1c0 (448)",
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
unittests/InstructionCountCI/Secondary_32Bit.json
+8 -8
View File
@@ -13,7 +13,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #938]",
"ldrh w20, [x28, #970]",
"str w20, [x8, #-4]!"
]
},
@@ -22,24 +22,24 @@
"Comment": "0x0f 0xa1",
"ExpectedArm64ASM": [
"ldr w20, [x8], #4",
"strh w20, [x28, #938]",
"strh w20, [x28, #970]",
"ubfx w21, w20, #2, #1",
"and w20, w20, #0xfff8",
"add x0, x28, x21, lsl #3",
"ldr x21, [x0, #1168]",
"ldr x21, [x0, #1184]",
"ldr x20, [x21, w20, uxtw]",
"lsr x21, x20, #32",
"and w22, w21, #0xff000000",
"orr w20, w22, w20, lsr #16",
"bfi w20, w21, #16, #8",
"str w20, [x28, #968]"
"str w20, [x28, #1000]"
]
},
"push gs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa8",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #936]",
"ldrh w20, [x28, #968]",
"str w20, [x8, #-4]!"
]
},
@@ -48,17 +48,17 @@
"Comment": "0x0f 0xa9",
"ExpectedArm64ASM": [
"ldr w20, [x8], #4",
"strh w20, [x28, #936]",
"strh w20, [x28, #968]",
"ubfx w21, w20, #2, #1",
"and w20, w20, #0xfff8",
"add x0, x28, x21, lsl #3",
"ldr x21, [x0, #1168]",
"ldr x21, [x0, #1184]",
"ldr x20, [x21, w20, uxtw]",
"lsr x21, x20, #32",
"and w22, w21, #0xff000000",
"orr w20, w22, w20, lsr #16",
"bfi w20, w21, #16, #8",
"str w20, [x28, #960]"
"str w20, [x28, #992]"
]
}
}
unittests/InstructionCountCI/Secondary_OpSize.json
+14 -14
View File
@@ -112,10 +112,10 @@
"ExpectedInstructionCount": 6,
"Comment": "0x66 0x0f 0x2a",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"sxtl v2.2d, v2.2s",
"scvtf v16.2d, v2.2d"
]
@@ -131,28 +131,28 @@
"ExpectedInstructionCount": 8,
"Comment": "0x66 0x0f 0x2c",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"strb w20, [x28, #1202]",
"frint32z v2.2d, v16.2d",
"fcvtzs v2.2d, v2.2d",
"xtn v2.2s, v2.2d",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"cvtpd2pi mm0, xmm0": {
"ExpectedInstructionCount": 8,
"Comment": "0x66 0x0f 0x2d",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"strb w20, [x28, #1202]",
"frint32x v2.2d, v16.2d",
"fcvtzs v2.2d, v2.2d",
"xtn v2.2s, v2.2d",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"ucomisd xmm0, xmm1": {
@@ -525,7 +525,7 @@
"0x66 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2624]",
"ldr x0, [x28, #2640]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -539,7 +539,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #2624]",
"ldr x0, [x28, #2640]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v2.16b}, v3.16b"
]
@@ -677,7 +677,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #2624]",
"ldr x0, [x28, #2640]",
"ldr q3, [x0, #2480]",
"tbl v16.16b, {v2.16b}, v3.16b"
]
unittests/InstructionCountCI/Secondary_REP.json
+5 -5
View File
@@ -397,7 +397,7 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2616]",
"ldr x0, [x28, #2632]",
"ldr q2, [x0, #1280]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -410,7 +410,7 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2616]",
"ldr x0, [x28, #2632]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -673,10 +673,10 @@
"ExpectedInstructionCount": 4,
"Comment": "0xf3 0x0f 0xd6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d16, [x28, #1040]"
"strb w20, [x28, #1202]",
"ldr d16, [x28, #1056]"
]
},
"cvtdq2pd xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REPNE.json
+6 -6
View File
@@ -290,7 +290,7 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2608]",
"ldr x0, [x28, #2624]",
"ldr q2, [x0, #1280]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -303,7 +303,7 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2608]",
"ldr x0, [x28, #2624]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -512,11 +512,11 @@
"ExpectedInstructionCount": 5,
"Comment": "0xf2 0x0f 0xd6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"str d16, [x28, #1040]",
"strh w20, [x28, #1048]"
"strb w20, [x28, #1202]",
"str d16, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"cvtpd2dq xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_SVE128.json
+48 -48
View File
@@ -36,112 +36,112 @@
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xd1",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"lsr z2.h, p6/m, z2.h, z3.d",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrld mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xd2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"lsr z2.s, p6/m, z2.s, z3.d",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrlq mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xd3",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"lsr z2.d, p6/m, z2.d, z3.d",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psraw mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xe1",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"asr z2.h, p6/m, z2.h, z3.d",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrad mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xe2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"asr z2.s, p6/m, z2.s, z3.d",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psllw mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xf1",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"lsl z2.h, p6/m, z2.h, z3.d",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pslld mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xf2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"lsl z2.s, p6/m, z2.s, z3.d",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psllq mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xf3",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1019]",
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1186]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1072]",
"lsl z2.d, p6/m, z2.d, z3.d",
"str d2, [x28, #1040]",
"strh w20, [x28, #1048]"
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
}
}
unittests/InstructionCountCI/VEX_map1.json
+12 -12
View File
@@ -2788,7 +2788,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2632]",
"ldr x0, [x28, #2648]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -2857,7 +2857,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2632]",
"ldr x0, [x28, #2648]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -2926,7 +2926,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2632]",
"ldr x0, [x28, #2648]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -3658,9 +3658,9 @@
],
"ExpectedArm64ASM": [
"frinti z2.s, p7/m, z17.s",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2568]",
"ld1b {z3.b}, p7/z, [x0]",
"ldr x0, [x28, #2504]",
"ldr x0, [x28, #2520]",
"ld1b {z4.b}, p7/z, [x0]",
"fcvtzs z5.s, p7/m, z2.s",
"fcmgt p0.s, p7/z, z4.s, z2.s",
@@ -3692,9 +3692,9 @@
"Map 1 0b10 0x5b 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2568]",
"ld1b {z2.b}, p7/z, [x0]",
"ldr x0, [x28, #2504]",
"ldr x0, [x28, #2520]",
"ld1b {z3.b}, p7/z, [x0]",
"fcvtzs z4.s, p7/m, z17.s",
"fcmgt p0.s, p7/z, z3.s, z17.s",
@@ -4438,7 +4438,7 @@
"Map 1 0b01 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2328]",
"ldr x0, [x28, #2344]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"fadd z16.d, z17.d, z2.d"
@@ -4461,7 +4461,7 @@
"Map 1 0b11 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2312]",
"ldr x0, [x28, #2328]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"fadd z16.s, z17.s, z2.s"
@@ -4602,7 +4602,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2440]",
"ldr x0, [x28, #2456]",
"ld1b {z2.b}, p7/z, [x0]",
"mrs x0, nzcv",
"mov z0.d, #0",
@@ -4997,7 +4997,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3440]",
"ldr x0, [x28, #2528]",
"ldr x0, [x28, #2544]",
"ld1b {z3.b}, p7/z, [x0]",
"fcvtzs z4.s, p7/m, z17.d",
"uzp1 z4.s, z4.s, z4.s",
@@ -5059,7 +5059,7 @@
"ExpectedArm64ASM": [
"frinti z2.d, p7/m, z17.d",
"ldr q3, [x28, #3440]",
"ldr x0, [x28, #2528]",
"ldr x0, [x28, #2544]",
"ld1b {z4.b}, p7/z, [x0]",
"fcvtzs z5.s, p7/m, z2.d",
"uzp1 z5.s, z5.s, z5.s",
unittests/InstructionCountCI/VEX_map1_FRINTTS.json
+6 -6
View File
@@ -112,9 +112,9 @@
],
"ExpectedArm64ASM": [
"frinti z2.s, p7/m, z17.s",
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2568]",
"ld1b {z3.b}, p7/z, [x0]",
"ldr x0, [x28, #2504]",
"ldr x0, [x28, #2520]",
"ld1b {z4.b}, p7/z, [x0]",
"fcvtzs z5.s, p7/m, z2.s",
"fcmgt p0.s, p7/z, z4.s, z2.s",
@@ -142,9 +142,9 @@
"Map 1 0b10 0x5b 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2552]",
"ldr x0, [x28, #2568]",
"ld1b {z2.b}, p7/z, [x0]",
"ldr x0, [x28, #2504]",
"ldr x0, [x28, #2520]",
"ld1b {z3.b}, p7/z, [x0]",
"fcvtzs z4.s, p7/m, z17.s",
"fcmgt p0.s, p7/z, z3.s, z17.s",
@@ -174,7 +174,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3440]",
"ldr x0, [x28, #2528]",
"ldr x0, [x28, #2544]",
"ld1b {z3.b}, p7/z, [x0]",
"fcvtzs z4.s, p7/m, z17.d",
"uzp1 z4.s, z4.s, z4.s",
@@ -209,7 +209,7 @@
"ExpectedArm64ASM": [
"frinti z2.d, p7/m, z17.d",
"ldr q3, [x28, #3440]",
"ldr x0, [x28, #2528]",
"ldr x0, [x28, #2544]",
"ld1b {z4.b}, p7/z, [x0]",
"fcvtzs z5.s, p7/m, z2.d",
"uzp1 z5.s, z5.s, z5.s",
unittests/InstructionCountCI/VEX_map2.json
+12 -12
View File
@@ -3669,7 +3669,7 @@
"Map 2 0b01 0x96 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2312]",
"ldr x0, [x28, #2328]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z17.d, z2.d",
"mov z0.d, z2.d",
@@ -3695,7 +3695,7 @@
"Map 2 0b01 0x96 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2328]",
"ldr x0, [x28, #2344]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z17.d, z2.d",
"mov z0.d, z2.d",
@@ -3721,7 +3721,7 @@
"Map 2 0b01 0x97 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2344]",
"ldr x0, [x28, #2360]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z17.d, z2.d",
"mov z0.d, z2.d",
@@ -3747,7 +3747,7 @@
"Map 2 0b01 0x97 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2360]",
"ldr x0, [x28, #2376]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z17.d, z2.d",
"mov z0.d, z2.d",
@@ -4621,7 +4621,7 @@
"Map 2 0b01 0xa6 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2312]",
"ldr x0, [x28, #2328]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"mov z0.d, z2.d",
@@ -4647,7 +4647,7 @@
"Map 2 0b01 0xa6 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2328]",
"ldr x0, [x28, #2344]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"mov z0.d, z2.d",
@@ -4673,7 +4673,7 @@
"Map 2 0b01 0xa7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2344]",
"ldr x0, [x28, #2360]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"mov z0.d, z2.d",
@@ -4699,7 +4699,7 @@
"Map 2 0b01 0xa7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2360]",
"ldr x0, [x28, #2376]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"mov z0.d, z2.d",
@@ -4725,7 +4725,7 @@
"Map 2 0b01 0xb6 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2312]",
"ldr x0, [x28, #2328]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z16.d, z2.d",
"mov z16.d, z2.d",
@@ -4750,7 +4750,7 @@
"Map 2 0b01 0xb6 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2328]",
"ldr x0, [x28, #2344]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z16.d, z2.d",
"mov z16.d, z2.d",
@@ -4775,7 +4775,7 @@
"Map 2 0b01 0xb7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2344]",
"ldr x0, [x28, #2360]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z16.d, z2.d",
"mov z16.d, z2.d",
@@ -4800,7 +4800,7 @@
"Map 2 0b01 0xb7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2360]",
"ldr x0, [x28, #2376]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z16.d, z2.d",
"mov z16.d, z2.d",
unittests/InstructionCountCI/VEX_map_group.json
+2 -2
View File
@@ -585,7 +585,7 @@
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"and w20, w20, #0xffc0",
"str w20, [x28, #940]",
"str w20, [x28, #972]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
@@ -602,7 +602,7 @@
"Map group 15 0b011"
],
"ExpectedArm64ASM": [
"ldr w20, [x28, #940]",
"ldr w20, [x28, #972]",
"and w20, w20, #0xffc0",
"str w20, [x4]"
]
unittests/InstructionCountCI/X87ldst-SVE.json
+44 -44
View File
@@ -17,18 +17,18 @@
"ExpectedInstructionCount": 12,
"Comment": "Single 80-bit store.",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1040]",
"ldr q2, [x21, #1056]",
"st1h {z2.h}, p2, [x4]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1019]",
"ldrb w21, [x28, #1186]",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
},
"2-store 80bit": {
@@ -39,26 +39,26 @@
"fstp tword [rax+10]"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1040]",
"ldr q2, [x21, #1056]",
"st1h {z2.h}, p2, [x4]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1040]",
"ldr q2, [x21, #1056]",
"add x21, x4, #0xa (10)",
"st1h {z2.h}, p2, [x21]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w21, [x28, #1186]",
"strb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0xc0c0",
"lsr w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
},
"8-store 80bit": {
@@ -75,54 +75,54 @@
"fstp tword [rax+70]"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1040]",
"ldr q2, [x21, #1056]",
"st1h {z2.h}, p2, [x4]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q2, [x22, #1040]",
"ldr q2, [x22, #1056]",
"add x22, x4, #0xa (10)",
"st1h {z2.h}, p2, [x22]",
"add w21, w21, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q2, [x22, #1040]",
"ldr q2, [x22, #1056]",
"add x22, x4, #0x14 (20)",
"st1h {z2.h}, p2, [x22]",
"add w21, w21, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q2, [x22, #1040]",
"ldr q2, [x22, #1056]",
"add x22, x4, #0x1e (30)",
"st1h {z2.h}, p2, [x22]",
"add w21, w21, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q2, [x22, #1040]",
"ldr q2, [x22, #1056]",
"add x22, x4, #0x28 (40)",
"st1h {z2.h}, p2, [x22]",
"add w21, w21, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q2, [x22, #1040]",
"ldr q2, [x22, #1056]",
"add x22, x4, #0x32 (50)",
"st1h {z2.h}, p2, [x22]",
"add w21, w21, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q2, [x22, #1040]",
"ldr q2, [x22, #1056]",
"add x22, x4, #0x3c (60)",
"st1h {z2.h}, p2, [x22]",
"add w21, w21, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1040]",
"ldr q2, [x21, #1056]",
"add x21, x4, #0x46 (70)",
"st1h {z2.h}, p2, [x21]",
"strb w20, [x28, #1019]",
"strb wzr, [x28, #1186]"
"strb w20, [x28, #1051]",
"strb wzr, [x28, #1202]"
]
},
"fld tword [rax]": {
@@ -130,17 +130,17 @@
"Comment": "Single 80-bit store.",
"ExpectedArm64ASM": [
"ld1h {z2.h}, p2/z, [x4]",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1040]",
"ldrb w21, [x28, #1186]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
},
"2-load 80bit": {
@@ -154,23 +154,23 @@
"ld1h {z2.h}, p2/z, [x4]",
"add x20, x4, #0xa (10)",
"ld1h {z3.h}, p2/z, [x20]",
"ldrb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q3, [x21, #1040]",
"str q3, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"str q2, [x21, #1040]",
"ldrb w21, [x28, #1186]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x303",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
},
"8-load 80bit": {
@@ -202,40 +202,40 @@
"ld1h {z8.h}, p2/z, [x20]",
"add x20, x4, #0x46 (70)",
"ld1h {z9.h}, p2/z, [x20]",
"ldrb w20, [x28, #1019]",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1051]",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q9, [x21, #1040]",
"str q9, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"str q8, [x21, #1040]",
"str q8, [x21, #1056]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"str q7, [x21, #1040]",
"str q7, [x21, #1056]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"str q6, [x21, #1040]",
"str q6, [x21, #1056]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"str q5, [x21, #1040]",
"str q5, [x21, #1056]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"str q4, [x21, #1040]",
"str q4, [x21, #1056]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"str q3, [x21, #1040]",
"str q3, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"str q2, [x20, #1040]",
"str q2, [x20, #1056]",
"mov w20, #0xff",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
}
}
unittests/InstructionCountCI/x87.json
+2778 -2778
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/x87_32Bit.json
+3 -3
View File
@@ -27,14 +27,14 @@
"ldur s2, [x9, #-8]",
"mov w20, #0x3ff2",
"str s2, [x4, x20, sxtx]",
"ldrb w20, [x28, #1019]",
"ldrb w21, [x28, #1186]",
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
}
}
unittests/InstructionCountCI/x87_f64.json
+2088 -2088
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/x87_f64_32Bit.json
+5 -5
View File
@@ -23,19 +23,19 @@
"mov w20, #0x4a20",
"movk w20, #0x20, lsl #16",
"add w20, w20, w6, lsl #2",
"ldrb w21, [x28, #1019]",
"ldrb w21, [x28, #1051]",
"add x22, x28, x21, lsl #4",
"ldr d2, [x22, #1040]",
"ldr d2, [x22, #1056]",
"fcvt s2, d2",
"str s2, [x20]",
"add w20, w21, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1186]",
"strb w20, [x28, #1051]",
"ldrb w20, [x28, #1202]",
"mov w22, #0x1",
"lsl w21, w22, w21",
"bic w20, w20, w21",
"strb w20, [x28, #1186]"
"strb w20, [x28, #1202]"
]
}
}