steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-06 08:00:15 +02:00
Code Issues Packages Projects Releases 66 Wiki Activity
14,903 Commits 11 Branches 70 Tags
44f69f4dd74e89671e903f26022bcd4e9055012d
Commit Graph
2344 Commits
Author SHA1 Message Date
Paris Oplopoios 635befb4c8 FEXCore: Fix CF calculation for BLSMSK and BLSR for 32-bit operands 2026-08-22 15:47:50 +03:00
Paris Oplopoios a69daa2524 unittests/ASM: Test BLSR/BLSMSK CF flag 2026-08-22 15:34:13 +03:00
Ryan Houdek 492dac719f unittests: Disable siglongjmp_branch_invalid on 32-bit 
This test is trying to execute "invalid" code from the last two pages of
the address space to the first two pages of the address space. But
failed to noticed that the last two pages of the 32-bit x86 address
space are actually valid, usually containing VDSO things.
 2026-08-17 18:22:03 -07:00
Ryan Houdek 9377bac5e7 Merge pull request #5825 from javelina-pkwy/fix/siglongjmp-deadlock 
FEXCore: prevent deadlock when branching to MAX_UINT64
 2026-08-17 17:55:39 -07:00
Ryan Houdek a3d609ebb1 Merge pull request #5820 from javelina-pkwy/lea-reg-reg 
Decoder: fix illegal LEA encoding
 2026-08-17 09:58:47 -07:00
Justin Becker 6f29dfcbb8 Probe before taking lock in Compile*() 2026-08-13 16:53:05 -07:00
Justin Becker c156498c5c Add 16 bit and 32 bit variants 2026-08-11 16:19:49 -07:00
Paris Oplopoios f4e362c477 unittests/ASM: Ensure ffreep always has an operand 2026-08-09 16:46:13 +03:00
Simon Scherer 4844729e93 unittests/ASM: Test lossy precision non-SVE path in Vector_F64ToI32 2026-08-05 13:13:04 +02:00
Iaying 7629323548 Fix an XMM register bug in SpillSRA, along with adding a test that reproduces the bug 2026-08-03 15:15:41 -07:00
Justin Becker 34a87cc94c Decoder: fix illegal LEA encoding 2026-07-27 15:48:35 -07:00
Ryan Houdek 27315e33ab Merge pull request #5784 from FrontMage/fix/instruction-fetch-fault-priority 
Frontend: Prioritize instruction fetch faults
 2026-07-27 12:54:53 -07:00
FrontMage 151b4d4c2d Frontend: Prioritize instruction fetch faults 2026-07-25 09:01:21 +08:00
Paris Oplopoios 86c20d0519 Extend FIST tests to check for indefinite value 2026-07-24 17:04:10 +03:00
FrontMage fcf9fd77d7 FEXCore: Isolate multiblock error state per block 2026-07-23 16:52:19 +08:00
Ryan Houdek f73b93dbc2 InstcountCI: Update 2026-07-17 13:17:39 -07:00
Ryan Houdek f129ca0c61 unittests/vmovmskpd: Extend test to have different lower and upper results between 128-bit lanes. 2026-07-17 13:12:27 -07:00
moonfloww 7189e1e280 InstcountCI: Update 2026-07-16 14:44:04 +02:00
LC ba8b0afe7a VectorOps: Use unpredicated shifts where applicable for 256-bit scalar shifts 
Lets us trim some output
 2026-07-15 09:10:57 -04:00
LC 98d45a6a9b VectorOps: Make use of unpredicated immediate shifts 
Same behavior, just without introducing a predicate register dependency.
 2026-07-15 08:00:58 -04:00
LC 4afa49824e StringUtils: Handle strings entirely composed of whitespace in trims 
Previously this wouldn't handle fully whitespaced strings.
 2026-07-13 17:37:09 -04:00
LC 842e22915c VectorOps: Simplify SVE 256-bit VOrn with BSL2N 
Lets us shave off an instruction and also avoid using a temporary
register in some cases. We can also tweak our worst case that requires a
predicate to eliminate the temporary as well.

We can also expand our cmpps cases, so that we can reflect the
BSL2N usages in instcountci.
 2026-07-13 12:27:54 -04:00
LC 9d3c388664 Crypto: Make use of XAR in SHA1NEXTE when available 
Lets us shave an instruction off on hardware that supports XAR.

Closes #5730
 2026-07-12 16:02:12 -04:00
LC 613e9ef701 MiscOps: Fix round mode clearing for RP/RM modes in PushRoundingMode 
Previously this had the potential to not clear rounding bits properly
depending on incoming FPCR state.
 2026-07-11 10:24:07 -04:00
LC b5660c8a92 MiscOps: Avoid stack misalignment in ProcessorID 
This needs to be an add.
 2026-07-10 05:41:54 -04:00
Ryan Houdek 3370d9af15 Merge pull request #5670 from simon902/MOVDoverride 
Fix movd when prefixed with 0x66
 2026-07-09 13:02:08 -07:00
Ryan Houdek 9306de79ad Merge pull request #5667 from simon902/CVTTSS2SIOverride 
Fix cvttss2si when prefixed with 0x66
 2026-07-09 12:52:00 -07:00
Ryan Houdek ff7a54add8 Merge pull request #5668 from OFFTKP/inf 
Fix element getting overwritten in 66_5B test
 2026-07-09 12:26:46 -07:00
Ryan Houdek c3d1157696 Merge pull request #5669 from OFFTKP/lzcnt 
Fix LZCNT tests reading out of bounds
 2026-07-09 12:24:43 -07:00
LC 9b7c9f0fb6 Vector: Trim one instruction off insertq 
We can fold a bitwise not and and pair into a bic
 2026-07-09 14:58:04 -04:00
Simon Scherer c06468025c unittests/ASM: Test movd prefixed with 0x66 2026-07-09 11:46:10 +02:00
Paris Oplopoios 148e539025 Fix LZCNT tests reading out of bounds 2026-07-09 12:36:18 +03:00
Paris Oplopoios 92b96ff30d Fix element getting overwritten in 66_5B test 2026-07-09 11:54:38 +03:00
Simon Scherer 778df0c93b unittests/ASM: Test cvttss2si prefixed with 0x66 2026-07-09 09:24:59 +02:00
Ryan Houdek 5f2455c502 Merge pull request #5665 from lioncash/blendop 
[SVE256] Handle 256-bit blend operations much more efficiently
 2026-07-08 16:43:20 -07:00
LC 6bc67609a3 [SVE256] Handle 256-bit blend operations much more efficiently 
We can massage a given selector into a valid predicate register bitmask
and then simply perform a merging move, which eliminates most busywork
around optimizing 256-bit blends.

In the future, once we drop SVE2.1 support in, we can use PMOV to
eliminate the load from memory and related constant management.
 2026-07-08 17:35:12 -04:00
LC 8a8827c980 Merge pull request #5664 from simon902/CMPXCHGZeroing 
OpcodeDispatcher: Fix 32bit cmpxchg zero extension with eax as first operand
 2026-07-08 15:14:12 -04:00
Simon Scherer 84fab84b3f InstcountCI: Update 2026-07-08 15:00:18 +02:00
Simon Scherer 59097bab20 unittests/ASM: Test cmpxchg with eax as destination 2026-07-08 14:52:19 +02:00
Simon Scherer 4cbacd9261 InstcountCI: Update 2026-07-08 10:10:30 +02:00
Simon Scherer f718f46545 unittests/ASM: Test overlapping operands for pdep 2026-07-08 09:47:12 +02:00
LC ba9f7fb1b5 unittests: Add stress tests for VBLEND{PD, PS} 
Forgot about these two
 2026-07-07 13:49:09 -04:00
LC 95bfff20a4 unittests: Add stress tests for VSHUF{PD, PS} 
Covers the remaining shuffle paths
 2026-07-06 18:01:52 -04:00
LC e7727c39f3 unittests: Add stress tests for VPERMIL{PD, PS} 
While unlikely to be used in practice over other kind of
shuffling and blending, these should also have stress tests
to make sure they do the right thing.
 2026-07-04 15:00:30 -04:00
LC 7fd9b897c2 [SVE256] Handle 256-bit AES operations 
Currently we split these into two 128-bit operations since VIXL doesn't
have support for the unified SVE operations yet.

Now we fully support VAES on SVE256.
 2026-07-03 21:52:59 -04:00
LC 5145324806 [SVE256] EncryptionOps: Handle 256-bit VPCLMULQDQ 
Since vixl now handles this, we can drop this support right in.
 2026-07-03 21:22:05 -04:00
Ryan Houdek 4233fb6270 Merge pull request #5648 from lioncash/aes 
[SVE256] Ensure SSE insertion behavior for AES/SHA/PCLMUL operations
 2026-07-03 17:33:19 -07:00
LC d11b19fd2b [SVE256] Ensure insertion behavior for PCLMUL SSE operations 
Also includes accompanying test to ensure it never breaks.
 2026-07-03 20:15:34 -04:00
LC 684c568033 [SVE256] Ensure insertion behavior for SHA SSE operations 
These slipped through, so now we can add tests for them to prevent that
from happening again.
 2026-07-03 20:09:50 -04:00
LC ab4fb7b3ad [SVE256] Ensure insertion behavior for AES operations on SSE 
These slipped through, so now we can add tests for them to prevent that
from happening again.
 2026-07-03 19:35:31 -04:00