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https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 09:00:17 +02:00
[SVE256] Handle 256-bit AES operations
Currently we split these into two 128-bit operations since VIXL doesn't have support for the unified SVE operations yet. Now we fully support VAES on SVE256.
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@@ -208,14 +208,25 @@ void OpDispatchBuilder::AESEncOp(OpcodeArgs) {
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void OpDispatchBuilder::VAESEncOp(OpcodeArgs) {
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const auto DstSize = OpSizeFromDst(Op);
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const auto Is128Bit = DstSize == OpSize::i128Bit;
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// TODO: Handle 256-bit VAESENC.
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LOGMAN_THROW_A_FMT(Is128Bit, "256-bit VAESENC unimplemented");
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const auto Is256Bit = DstSize == OpSize::i256Bit;
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Ref State = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
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Ref Key = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
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Ref Result = _VAESEnc(DstSize, State, Key, LoadZeroVector(DstSize));
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Ref ZeroVec = LoadZeroVector(DstSize);
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Ref Result {};
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if (Is256Bit) {
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// TODO: Handle as one operation once vixl supports it.
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auto UpperState = _VDupElement(DstSize, OpSize::i128Bit, State, 1);
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auto UpperKey = _VDupElement(DstSize, OpSize::i128Bit, Key, 1);
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auto Lower = _VAESEnc(OpSize::i128Bit, State, Key, ZeroVec);
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auto Upper = _VAESEnc(OpSize::i128Bit, UpperState, UpperKey, ZeroVec);
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Result = _VInsElement(DstSize, OpSize::i128Bit, 1, 0, Lower, Upper);
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} else {
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Result = _VAESEnc(DstSize, State, Key, ZeroVec);
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}
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StoreResultFPR(Op, Result);
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}
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@@ -233,14 +244,25 @@ void OpDispatchBuilder::AESEncLastOp(OpcodeArgs) {
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void OpDispatchBuilder::VAESEncLastOp(OpcodeArgs) {
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const auto DstSize = OpSizeFromDst(Op);
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const auto Is128Bit = DstSize == OpSize::i128Bit;
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// TODO: Handle 256-bit VAESENCLAST.
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LOGMAN_THROW_A_FMT(Is128Bit, "256-bit VAESENCLAST unimplemented");
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const auto Is256Bit = DstSize == OpSize::i256Bit;
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Ref State = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
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Ref Key = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
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Ref Result = _VAESEncLast(DstSize, State, Key, LoadZeroVector(DstSize));
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Ref ZeroVec = LoadZeroVector(DstSize);
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Ref Result {};
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if (Is256Bit) {
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// TODO: Handle as one operation once vixl supports it.
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auto UpperState = _VDupElement(DstSize, OpSize::i128Bit, State, 1);
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auto UpperKey = _VDupElement(DstSize, OpSize::i128Bit, Key, 1);
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auto Lower = _VAESEncLast(OpSize::i128Bit, State, Key, ZeroVec);
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auto Upper = _VAESEncLast(OpSize::i128Bit, UpperState, UpperKey, ZeroVec);
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Result = _VInsElement(DstSize, OpSize::i128Bit, 1, 0, Lower, Upper);
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} else {
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Result = _VAESEncLast(DstSize, State, Key, ZeroVec);
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}
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StoreResultFPR(Op, Result);
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}
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@@ -258,14 +280,25 @@ void OpDispatchBuilder::AESDecOp(OpcodeArgs) {
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void OpDispatchBuilder::VAESDecOp(OpcodeArgs) {
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const auto DstSize = OpSizeFromDst(Op);
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const auto Is128Bit = DstSize == OpSize::i128Bit;
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// TODO: Handle 256-bit VAESDEC.
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LOGMAN_THROW_A_FMT(Is128Bit, "256-bit VAESDEC unimplemented");
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const auto Is256Bit = DstSize == OpSize::i256Bit;
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Ref State = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
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Ref Key = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
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Ref Result = _VAESDec(DstSize, State, Key, LoadZeroVector(DstSize));
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Ref ZeroVec = LoadZeroVector(DstSize);
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Ref Result {};
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if (Is256Bit) {
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// TODO: Handle as one operation once vixl supports it.
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auto UpperState = _VDupElement(DstSize, OpSize::i128Bit, State, 1);
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auto UpperKey = _VDupElement(DstSize, OpSize::i128Bit, Key, 1);
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auto Lower = _VAESDec(OpSize::i128Bit, State, Key, ZeroVec);
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auto Upper = _VAESDec(OpSize::i128Bit, UpperState, UpperKey, ZeroVec);
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Result = _VInsElement(DstSize, OpSize::i128Bit, 1, 0, Lower, Upper);
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} else {
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Result = _VAESDec(DstSize, State, Key, ZeroVec);
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}
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StoreResultFPR(Op, Result);
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}
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@@ -283,14 +316,25 @@ void OpDispatchBuilder::AESDecLastOp(OpcodeArgs) {
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void OpDispatchBuilder::VAESDecLastOp(OpcodeArgs) {
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const auto DstSize = OpSizeFromDst(Op);
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const auto Is128Bit = DstSize == OpSize::i128Bit;
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// TODO: Handle 256-bit VAESDECLAST.
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LOGMAN_THROW_A_FMT(Is128Bit, "256-bit VAESDECLAST unimplemented");
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const auto Is256Bit = DstSize == OpSize::i256Bit;
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Ref State = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
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Ref Key = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
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Ref Result = _VAESDecLast(DstSize, State, Key, LoadZeroVector(DstSize));
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Ref ZeroVec = LoadZeroVector(DstSize);
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Ref Result {};
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if (Is256Bit) {
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// TODO: Handle as one operation once vixl supports it.
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auto UpperState = _VDupElement(DstSize, OpSize::i128Bit, State, 1);
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auto UpperKey = _VDupElement(DstSize, OpSize::i128Bit, Key, 1);
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auto Lower = _VAESDecLast(OpSize::i128Bit, State, Key, ZeroVec);
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auto Upper = _VAESDecLast(OpSize::i128Bit, UpperState, UpperKey, ZeroVec);
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Result = _VInsElement(DstSize, OpSize::i128Bit, 1, 0, Lower, Upper);
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} else {
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Result = _VAESDecLast(DstSize, State, Key, ZeroVec);
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}
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StoreResultFPR(Op, Result);
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}
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@@ -1,11 +1,3 @@
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# AES unsupported in 256-bit SVE currently
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Test_VEX/vaesdec.asm
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Test_VEX/vaesdeclast.asm
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Test_VEX/vaesdec256.asm
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Test_VEX/vaesdeclast256.asm
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Test_VEX/vaesenc256.asm
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Test_VEX/vaesenclast256.asm
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# Simulator can't handle self-modifying code
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Test_SelfModifyingCode/Delinking.asm
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Test_SelfModifyingCode/DifferentBlock.asm
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@@ -4751,10 +4751,26 @@
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]
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},
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"vaesenc ymm0, ymm1, ymm2": {
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"ExpectedInstructionCount": -1,
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"Skip": "Yes",
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"ExpectedInstructionCount": 15,
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"Comment": [
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"Map 2 0b01 0xdc 256-bit"
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],
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"ExpectedArm64ASM": [
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"movi v2.2d, #0x0",
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"mov z3.q, z17.q[1]",
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"mov z4.q, z18.q[1]",
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"mov v0.16b, v17.16b",
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"aese v0.16b, v2.16b",
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"aesmc v0.16b, v0.16b",
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"eor v5.16b, v0.16b, v18.16b",
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"mov v0.16b, v3.16b",
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"aese v0.16b, v2.16b",
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"aesmc v0.16b, v0.16b",
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"eor v2.16b, v0.16b, v4.16b",
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"mov z1.q, q2",
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"mov z16.d, z5.d",
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"not p0.b, p7/z, p6.b",
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"mov z16.b, p0/m, z1.b"
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]
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},
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"vaesenclast xmm0, xmm1, xmm2": {
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@@ -4770,10 +4786,24 @@
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]
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},
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"vaesenclast ymm0, ymm1, ymm2": {
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"ExpectedInstructionCount": -1,
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"Skip": "Yes",
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"ExpectedInstructionCount": 13,
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"Comment": [
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"Map 2 0b01 0xdd 256-bit"
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],
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"ExpectedArm64ASM": [
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"movi v2.2d, #0x0",
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"mov z3.q, z17.q[1]",
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"mov z4.q, z18.q[1]",
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"mov v0.16b, v17.16b",
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"aese v0.16b, v2.16b",
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"eor v5.16b, v0.16b, v18.16b",
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"mov v0.16b, v3.16b",
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"aese v0.16b, v2.16b",
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"eor v2.16b, v0.16b, v4.16b",
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"mov z1.q, q2",
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"mov z16.d, z5.d",
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"not p0.b, p7/z, p6.b",
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"mov z16.b, p0/m, z1.b"
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]
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},
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"vaesdec xmm0, xmm1, xmm2": {
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@@ -4790,10 +4820,26 @@
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]
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},
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"vaesdec ymm0, ymm1, ymm2": {
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"ExpectedInstructionCount": -1,
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"Skip": "Yes",
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"ExpectedInstructionCount": 15,
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"Comment": [
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"Map 2 0b01 0xde 256-bit"
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],
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"ExpectedArm64ASM": [
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"movi v2.2d, #0x0",
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"mov z3.q, z17.q[1]",
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"mov z4.q, z18.q[1]",
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"mov v0.16b, v17.16b",
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"aesd v0.16b, v2.16b",
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"aesimc v0.16b, v0.16b",
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"eor v5.16b, v0.16b, v18.16b",
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"mov v0.16b, v3.16b",
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"aesd v0.16b, v2.16b",
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"aesimc v0.16b, v0.16b",
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"eor v2.16b, v0.16b, v4.16b",
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"mov z1.q, q2",
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"mov z16.d, z5.d",
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"not p0.b, p7/z, p6.b",
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"mov z16.b, p0/m, z1.b"
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]
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},
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"vaesdeclast xmm0, xmm1, xmm2": {
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@@ -4809,10 +4855,24 @@
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]
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},
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"vaesdeclast ymm0, ymm1, ymm2": {
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"ExpectedInstructionCount": -1,
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"Skip": "Yes",
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"ExpectedInstructionCount": 13,
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"Comment": [
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"Map 2 0b01 0xdf 256-bit"
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],
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"ExpectedArm64ASM": [
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"movi v2.2d, #0x0",
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"mov z3.q, z17.q[1]",
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"mov z4.q, z18.q[1]",
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"mov v0.16b, v17.16b",
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"aesd v0.16b, v2.16b",
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"eor v5.16b, v0.16b, v18.16b",
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"mov v0.16b, v3.16b",
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"aesd v0.16b, v2.16b",
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"eor v2.16b, v0.16b, v4.16b",
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"mov z1.q, q2",
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"mov z16.d, z5.d",
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"not p0.b, p7/z, p6.b",
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"mov z16.b, p0/m, z1.b"
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]
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},
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"andn eax, ebx, ecx": {
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