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Merge pull request #5919 from simon902/fst_tag_word

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Mark tag word valid for FST ST(0) self-store
This commit is contained in:
LC authored and GitHub committed 2026-09-04 06:34:08 -04:00
2 parents a454845ffd 040d3115d2
commit 7052f91495
106 files changed
+413 -330
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FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp
+1 -3
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@@ -139,9 +139,7 @@ void OpDispatchBuilder::FST(OpcodeArgs, IR::OpSize Width) {
void OpDispatchBuilder::FSTToStack(OpcodeArgs) {
const uint8_t Offset = Op->OP & 7;
if (Offset != 0) {
_StoreStackToStack(Offset);
}
_StoreStackToStack(Offset);
if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) {
_PopStackDestroy();
FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp
+6 -8
View File
@@ -1041,15 +1041,13 @@ void X87StackOptimization::Run(IREmitter* Emit) {
const auto* Op = IROp->C<IROp_StoreStackToStack>();
auto Offset = Op->StackLocation;
if (Offset != 0) {
auto Value = MigrateToSlowPath_IfInvalid();
auto Value = MigrateToSlowPath_IfInvalid();
// Need to store st0 to stack location - basically a copy.
if (SlowPath) {
StoreStackValueAtOffset_Slow(LoadStackValueAtOffset_Slow(), Offset);
} else {
StackData.setTop(*Value, Offset);
}
// Need to store st0 to stack location - basically a copy.
if (SlowPath) {
StoreStackValueAtOffset_Slow(LoadStackValueAtOffset_Slow(), Offset);
} else {
StackData.setTop(*Value, Offset);
}
break;
}
FEXCore/include/FEXCore/Core/DiskCache.h
+1 -1
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@@ -210,7 +210,7 @@ namespace DiskCache {
// TODO: This header is in global installed header path, but uses internal headers.
// Migrate this once that is fixed.
static constexpr uint16_t FormatVersion = 13;
static constexpr uint16_t FormatVersion = 14;
FEX_DEFAULT_VISIBILITY uint16_t GetFormatVersion();
} // namespace DiskCache
unittests/ASM/FEX_bugs/fst_st0_tag_word.asm
+27
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@@ -0,0 +1,27 @@
%ifdef CONFIG
{
"RegData": {
"RAX": "0x1"
}
}
%endif
fxrstor [rel .fxsave_data]
fst st0
fxsave [rel .save]
movzx eax, byte [rel .save + 4]
hlt
align 16
.fxsave_data:
dw 0x037f ; FCW
dw 0x0000 ; FSW
dw 0x0000 ; FTW
times 506 db 0
align 16
.save:
times 64 dq 0
unittests/InstructionCountCI/AFP/H0F3A.json
+1 -1
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@@ -8,7 +8,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"roundss xmm0, xmm1, 00000000b": {
unittests/InstructionCountCI/AFP/SVE256/Secondary.json
+1 -1
View File
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"cvtpi2ps xmm0, [rax]": {
unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json
+1 -1
View File
@@ -9,7 +9,7 @@
"DisabledHostFeatures": [
"RPRES"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"cvtsi2ss xmm0, eax": {
unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json
+1 -1
View File
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"cvtsi2sd xmm0, eax": {
unittests/InstructionCountCI/AFP/Secondary.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"cvtpi2ps xmm0, [rax]": {
unittests/InstructionCountCI/AFP/Secondary_REP.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"RPRES"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"cvtsi2ss xmm0, eax": {
unittests/InstructionCountCI/AFP/Secondary_REPNE.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"cvtsi2sd xmm0, eax": {
unittests/InstructionCountCI/AFP/VEX_map1.json
+1 -1
View File
@@ -9,7 +9,7 @@
"DisabledHostFeatures": [
"RPRES"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vsqrtss xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AFP/VEX_map3.json
+1 -1
View File
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vroundss xmm0, xmm1, 00000000b": {
unittests/InstructionCountCI/AVX128/FMA4.json
+1 -1
View File
@@ -7,7 +7,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vfmaddsubps xmm0, xmm1, xmm2, xmm3": {
unittests/InstructionCountCI/AVX128/VEX_map1.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vmovups xmm0, xmm0": {
unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vaddsubpd xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FLAGM2",
"SVE256"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vmovntps [rax], xmm0": {
unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vucomiss xmm0, xmm1": {
unittests/InstructionCountCI/AVX128/VEX_map2.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vpshufb xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vfmadd132ss xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FLAGM2",
"SVE256"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vmovntdqa xmm0, [rax]": {
unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
+1 -1
View File
@@ -11,7 +11,7 @@
"SVE256",
"SVEBITPERM"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vtestps xmm0, xmm1": {
unittests/InstructionCountCI/AVX128/VEX_map3.json
+1 -1
View File
@@ -7,7 +7,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vpermq ymm0, ymm1, 1": {
unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json
+1 -1
View File
@@ -8,7 +8,7 @@
"AFP",
"SVE256"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vblendvps xmm0, xmm1, xmm2, xmm3": {
unittests/InstructionCountCI/AVX128/VEX_map_group.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vpsrlw xmm0, xmm1, 0": {
unittests/InstructionCountCI/Atomics.json
+1 -1
View File
@@ -9,7 +9,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"lock add byte [rax], cl": {
unittests/InstructionCountCI/Crypto/H0F38.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"sha1nexte xmm0, xmm1": {
unittests/InstructionCountCI/Crypto/H0F38_SVE128.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"sha1nexte xmm0, xmm1": {
unittests/InstructionCountCI/Crypto/H0F3A.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"pclmulqdq xmm0, xmm1, 00000b": {
unittests/InstructionCountCI/DDD.json
+1 -1
View File
@@ -10,7 +10,7 @@
"AFP",
"RPRES"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Comment": [
"These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers",
unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
+1 -1
View File
@@ -8,7 +8,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Comment": [
"Instructions that explicitly push against the limits of ARM's loadstore instructions"
unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json
+1 -1
View File
@@ -8,7 +8,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Comment": [
"Instructions that explicitly push against the limits of ARM's loadstore instructions"
unittests/InstructionCountCI/FEXOpt/MultiInst.json
+1 -1
View File
@@ -13,7 +13,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json
+1 -1
View File
@@ -11,7 +11,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"RPRES"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json
+1 -1
View File
@@ -14,7 +14,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json
+1 -1
View File
@@ -14,7 +14,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/libnss.json
+1 -1
View File
@@ -12,7 +12,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Comment": [],
"Instructions": {
unittests/InstructionCountCI/FlagM/Atomics.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"lock add byte [rax], cl": {
unittests/InstructionCountCI/FlagM/FlagOpts.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"Chained add": {
unittests/InstructionCountCI/FlagM/H0F38.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"ptest xmm0, xmm1": {
unittests/InstructionCountCI/FlagM/HotBlocks.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"The Witcher 3": {
unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"Sonic Mania movie player": {
unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"FMOD scalar loop": {
unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"The Sims 1 hot block": {
unittests/InstructionCountCI/FlagM/Primary.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"add bl, cl": {
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"add al, 1": {
unittests/InstructionCountCI/FlagM/Primary_32Bit.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"push es": {
unittests/InstructionCountCI/FlagM/Secondary.json
+1 -1
View File
@@ -11,7 +11,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"ucomiss xmm0, xmm1": {
unittests/InstructionCountCI/FlagM/SecondaryGroup.json
+1 -1
View File
@@ -11,7 +11,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"sgdt [rax]": {
unittests/InstructionCountCI/FlagM/SecondaryModRM.json
+1 -1
View File
@@ -11,7 +11,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"xgetbv": {
unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
+1 -1
View File
@@ -11,7 +11,7 @@
"AFP",
"FCMA"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"ucomisd xmm0, xmm1": {
unittests/InstructionCountCI/FlagM/Secondary_REP.json
+1 -1
View File
@@ -12,7 +12,7 @@
"AFP",
"CSSC"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"popcnt ax, bx": {
unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json
+1 -1
View File
@@ -12,7 +12,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"popcnt ax, bx": {
unittests/InstructionCountCI/FlagM/VEX_map1.json
+1 -1
View File
@@ -12,7 +12,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vucomiss xmm0, xmm1": {
unittests/InstructionCountCI/FlagM/VEX_map2.json
+1 -1
View File
@@ -10,7 +10,7 @@
"AFP",
"SVEBITPERM"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vtestps xmm0, xmm1": {
unittests/InstructionCountCI/FlagM/VEX_map_group.json
+1 -1
View File
@@ -9,7 +9,7 @@
"DisabledHostFeatures": [
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"blsr eax, ebx": {
unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87-HalfLife.json
+115 -107
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"Block1": {
@@ -2167,7 +2167,7 @@
},
"Block8": {
"x86InstructionCount": 25,
"ExpectedInstructionCount": 72,
"ExpectedInstructionCount": 76,
"x86Insts": [
"fstp st0",
"fstp st3",
@@ -2197,49 +2197,31 @@
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr q3, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q4, [x22, #1056]",
"strb wzr, [x28, #1049]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x23, x28, x20, lsl #4",
"strb wzr, [x28, #1049]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"ldr x0, [x28, #1672]",
"ldr x3, [x28, #1680]",
"blr x0",
"ldr x30, [sp], #16",
"fmov s5, s0",
"str s5, [x8, #56]",
"strb wzr, [x28, #1049]",
"str x30, [sp, #-16]!",
"mov v0.16b, v4.16b",
"ldr x0, [x28, #1672]",
"ldr x3, [x28, #1680]",
"blr x0",
"ldr x30, [sp], #16",
"fmov s5, s0",
"str s5, [x8, #44]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x12, x28, x20, lsl #4",
"add x23, x28, x22, lsl #4",
"ldr q3, [x23, #1056]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x23, x28, x22, lsl #4",
"ldr q4, [x23, #1056]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x12, x28, x22, lsl #4",
"ldr q5, [x12, #1056]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x12, x28, x22, lsl #4",
"add w13, w22, #0x1 (1)",
"and w13, w13, #0x7",
"add x13, x28, x13, lsl #4",
"ldr q6, [x13, #1056]",
"strb wzr, [x28, #1049]",
"add w22, w22, #0x2 (2)",
"and w22, w22, #0x7",
"add x14, x28, x22, lsl #4",
"strb wzr, [x28, #1049]",
"str x30, [sp, #-16]!",
"mov v0.16b, v5.16b",
@@ -2247,32 +2229,54 @@
"ldr x3, [x28, #1680]",
"blr x0",
"ldr x30, [sp], #16",
"fmov s6, s0",
"str s6, [x8, #40]",
"fmov s7, s0",
"str s7, [x8, #56]",
"strb wzr, [x28, #1049]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v0.16b, v6.16b",
"ldr x0, [x28, #1672]",
"ldr x3, [x28, #1680]",
"blr x0",
"ldr x30, [sp], #16",
"fmov s7, s0",
"str s7, [x8, #44]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q7, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str x30, [sp, #-16]!",
"mov v0.16b, v7.16b",
"ldr x0, [x28, #1672]",
"ldr x3, [x28, #1680]",
"blr x0",
"ldr x30, [sp], #16",
"fmov s8, s0",
"str s8, [x8, #40]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"ldr x0, [x28, #1688]",
"ldr x3, [x28, #1696]",
"blr x0",
"ldr x30, [sp], #16",
"fmov d6, d0",
"str d6, [x8]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"mov w13, #0x24",
"movk w13, #0x1, lsl #16",
"str w13, [x8, #-4]!",
"fmov d8, d0",
"str d8, [x8]",
"mov w15, #0x24",
"movk w15, #0x1, lsl #16",
"str w15, [x8, #-4]!",
"strb w20, [x28, #1051]",
"str q3, [x21, #1056]",
"str q4, [x22, #1056]",
"str q5, [x23, #1056]",
"str q2, [x12, #1056]",
"str q2, [x21, #1056]",
"str q4, [x23, #1056]",
"str q5, [x12, #1056]",
"str q6, [x13, #1056]",
"str q7, [x14, #1056]",
"str q3, [x22, #1056]",
"strb wzr, [x28, #1202]"
]
},
"Block9": {
"x86InstructionCount": 25,
"ExpectedInstructionCount": 72,
"ExpectedInstructionCount": 76,
"x86Insts": [
"fstp st0",
"fstp st3",
@@ -2302,49 +2306,31 @@
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr q3, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q4, [x22, #1056]",
"strb wzr, [x28, #1049]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x23, x28, x20, lsl #4",
"strb wzr, [x28, #1049]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"ldr x0, [x28, #1672]",
"ldr x3, [x28, #1680]",
"blr x0",
"ldr x30, [sp], #16",
"fmov s5, s0",
"str s5, [x8, #56]",
"strb wzr, [x28, #1049]",
"str x30, [sp, #-16]!",
"mov v0.16b, v4.16b",
"ldr x0, [x28, #1672]",
"ldr x3, [x28, #1680]",
"blr x0",
"ldr x30, [sp], #16",
"fmov s5, s0",
"str s5, [x8, #44]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x12, x28, x20, lsl #4",
"add x23, x28, x22, lsl #4",
"ldr q3, [x23, #1056]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x23, x28, x22, lsl #4",
"ldr q4, [x23, #1056]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x12, x28, x22, lsl #4",
"ldr q5, [x12, #1056]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x12, x28, x22, lsl #4",
"add w13, w22, #0x1 (1)",
"and w13, w13, #0x7",
"add x13, x28, x13, lsl #4",
"ldr q6, [x13, #1056]",
"strb wzr, [x28, #1049]",
"add w22, w22, #0x2 (2)",
"and w22, w22, #0x7",
"add x14, x28, x22, lsl #4",
"strb wzr, [x28, #1049]",
"str x30, [sp, #-16]!",
"mov v0.16b, v5.16b",
@@ -2352,26 +2338,48 @@
"ldr x3, [x28, #1680]",
"blr x0",
"ldr x30, [sp], #16",
"fmov s6, s0",
"str s6, [x8, #40]",
"fmov s7, s0",
"str s7, [x8, #56]",
"strb wzr, [x28, #1049]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v0.16b, v6.16b",
"ldr x0, [x28, #1672]",
"ldr x3, [x28, #1680]",
"blr x0",
"ldr x30, [sp], #16",
"fmov s7, s0",
"str s7, [x8, #44]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q7, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str x30, [sp, #-16]!",
"mov v0.16b, v7.16b",
"ldr x0, [x28, #1672]",
"ldr x3, [x28, #1680]",
"blr x0",
"ldr x30, [sp], #16",
"fmov s8, s0",
"str s8, [x8, #40]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"ldr x0, [x28, #1688]",
"ldr x3, [x28, #1696]",
"blr x0",
"ldr x30, [sp], #16",
"fmov d6, d0",
"str d6, [x8]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"mov w13, #0x24",
"movk w13, #0x1, lsl #16",
"str w13, [x8, #-4]!",
"fmov d8, d0",
"str d8, [x8]",
"mov w15, #0x24",
"movk w15, #0x1, lsl #16",
"str w15, [x8, #-4]!",
"strb w20, [x28, #1051]",
"str q3, [x21, #1056]",
"str q4, [x22, #1056]",
"str q5, [x23, #1056]",
"str q2, [x12, #1056]",
"str q2, [x21, #1056]",
"str q4, [x23, #1056]",
"str q5, [x12, #1056]",
"str q6, [x13, #1056]",
"str q7, [x14, #1056]",
"str q3, [x22, #1056]",
"strb wzr, [x28, #1202]"
]
},
unittests/InstructionCountCI/FlagM/x87-Oblivion.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87.json
+20 -9
View File
@@ -11,7 +11,7 @@
"CSSC",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"fadd dword [rax]": {
@@ -7381,11 +7381,21 @@
]
},
"fst st0": {
"ExpectedInstructionCount": 0,
"ExpectedInstructionCount": 9,
"Comment": [
"0xdd 11b 0xd0 /2"
],
"ExpectedArm64ASM": []
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fst st1": {
"ExpectedInstructionCount": 12,
@@ -7528,19 +7538,20 @@
]
},
"fstp st0": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdd 11b 0xd8 /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json
+87 -79
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"Block1": {
@@ -892,7 +892,7 @@
},
"Block8": {
"x86InstructionCount": 25,
"ExpectedInstructionCount": 47,
"ExpectedInstructionCount": 51,
"x86Insts": [
"fstp st0",
"fstp st3",
@@ -922,57 +922,61 @@
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr d3, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr d4, [x22, #1056]",
"strb wzr, [x28, #1049]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x23, x28, x20, lsl #4",
"strb wzr, [x28, #1049]",
"fcvt s5, d3",
"str s5, [x8, #56]",
"strb wzr, [x28, #1049]",
"fcvt s5, d4",
"str s5, [x8, #44]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x12, x28, x20, lsl #4",
"add x23, x28, x22, lsl #4",
"ldr d3, [x23, #1056]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x23, x28, x22, lsl #4",
"ldr d4, [x23, #1056]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x12, x28, x22, lsl #4",
"ldr d5, [x12, #1056]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x12, x28, x22, lsl #4",
"add w13, w22, #0x1 (1)",
"and w13, w13, #0x7",
"add x13, x28, x13, lsl #4",
"ldr d6, [x13, #1056]",
"strb wzr, [x28, #1049]",
"fcvt s6, d5",
"str s6, [x8, #40]",
"str d2, [x8]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"mov w13, #0x24",
"movk w13, #0x1, lsl #16",
"str w13, [x8, #-4]!",
"add w22, w22, #0x2 (2)",
"and w22, w22, #0x7",
"add x14, x28, x22, lsl #4",
"strb wzr, [x28, #1049]",
"fcvt s7, d5",
"str s7, [x8, #56]",
"strb wzr, [x28, #1049]",
"fcvt s7, d6",
"str s7, [x8, #44]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr d7, [x22, #1056]",
"strb wzr, [x28, #1049]",
"fcvt s8, d7",
"str s8, [x8, #40]",
"str d3, [x8]",
"mov w15, #0x24",
"movk w15, #0x1, lsl #16",
"str w15, [x8, #-4]!",
"strb w20, [x28, #1051]",
"str d3, [x21, #1056]",
"str d4, [x22, #1056]",
"str d5, [x23, #1056]",
"str d2, [x12, #1056]",
"str d2, [x21, #1056]",
"str d4, [x23, #1056]",
"str d5, [x12, #1056]",
"str d6, [x13, #1056]",
"str d7, [x14, #1056]",
"str d3, [x22, #1056]",
"strb wzr, [x28, #1202]"
]
},
"Block9": {
"x86InstructionCount": 25,
"ExpectedInstructionCount": 47,
"ExpectedInstructionCount": 51,
"x86Insts": [
"fstp st0",
"fstp st3",
@@ -1002,51 +1006,55 @@
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr d3, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr d4, [x22, #1056]",
"strb wzr, [x28, #1049]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x23, x28, x20, lsl #4",
"strb wzr, [x28, #1049]",
"fcvt s5, d3",
"str s5, [x8, #56]",
"strb wzr, [x28, #1049]",
"fcvt s5, d4",
"str s5, [x8, #44]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x12, x28, x20, lsl #4",
"add x23, x28, x22, lsl #4",
"ldr d3, [x23, #1056]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x23, x28, x22, lsl #4",
"ldr d4, [x23, #1056]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x12, x28, x22, lsl #4",
"ldr d5, [x12, #1056]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x12, x28, x22, lsl #4",
"add w13, w22, #0x1 (1)",
"and w13, w13, #0x7",
"add x13, x28, x13, lsl #4",
"ldr d6, [x13, #1056]",
"strb wzr, [x28, #1049]",
"fcvt s6, d5",
"str s6, [x8, #40]",
"str d2, [x8]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"mov w13, #0x24",
"movk w13, #0x1, lsl #16",
"str w13, [x8, #-4]!",
"add w22, w22, #0x2 (2)",
"and w22, w22, #0x7",
"add x14, x28, x22, lsl #4",
"strb wzr, [x28, #1049]",
"fcvt s7, d5",
"str s7, [x8, #56]",
"strb wzr, [x28, #1049]",
"fcvt s7, d6",
"str s7, [x8, #44]",
"add w22, w22, #0x1 (1)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr d7, [x22, #1056]",
"strb wzr, [x28, #1049]",
"fcvt s8, d7",
"str s8, [x8, #40]",
"str d3, [x8]",
"mov w15, #0x24",
"movk w15, #0x1, lsl #16",
"str w15, [x8, #-4]!",
"strb w20, [x28, #1051]",
"str d3, [x21, #1056]",
"str d4, [x22, #1056]",
"str d5, [x23, #1056]",
"str d2, [x12, #1056]",
"str d2, [x21, #1056]",
"str d4, [x23, #1056]",
"str d5, [x12, #1056]",
"str d6, [x13, #1056]",
"str d7, [x14, #1056]",
"str d3, [x22, #1056]",
"strb wzr, [x28, #1202]"
]
},
unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87_f64.json
+20 -9
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"fadd dword [rax]": {
@@ -5914,11 +5914,21 @@
]
},
"fst st0": {
"ExpectedInstructionCount": 0,
"ExpectedInstructionCount": 9,
"Comment": [
"0xdd 11b 0xd0 /2"
],
"ExpectedArm64ASM": []
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1056]",
"str d2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fst st1": {
"ExpectedInstructionCount": 12,
@@ -6061,19 +6071,20 @@
]
},
"fstp st0": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdd 11b 0xd8 /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr d2, [x21, #1056]",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str d2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
unittests/InstructionCountCI/H0F38.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FLAGM2",
"CRYPTO"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"pshufb mm0, mm1": {
unittests/InstructionCountCI/H0F3A.json
+1 -1
View File
@@ -8,7 +8,7 @@
"AFP",
"CRYPTO"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Comment": [
"SSE4.2 string instructions are skipped here.",
unittests/InstructionCountCI/H0F3A_SVE128.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"dpps xmm0, xmm1, 00000000b": {
unittests/InstructionCountCI/MOPS/Primary.json
+1 -1
View File
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"rep movsb": {
unittests/InstructionCountCI/Primary.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FLAGM2",
"MOPS"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"add bl, cl": {
unittests/InstructionCountCI/PrimaryGroup.json
+1 -1
View File
@@ -9,7 +9,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Comment": [
"Instructions in this table that are marked optimal don't have their flag calculation part of this assumption",
unittests/InstructionCountCI/Primary_32Bit.json
+1 -1
View File
@@ -9,7 +9,7 @@
"FlagM",
"FlagM2"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"push es": {
unittests/InstructionCountCI/RPRES/DDD.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"pfrcpv mm0, mm1": {
unittests/InstructionCountCI/RPRES/Secondary.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"rsqrtps xmm0, xmm1": {
unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"rsqrtss xmm0, xmm1": {
unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json
+1 -1
View File
@@ -8,7 +8,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vrsqrtps xmm0, xmm1": {
unittests/InstructionCountCI/Repeat.json
+1 -1
View File
@@ -6,7 +6,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {}
}
unittests/InstructionCountCI/SSE42_Strings.json
+1 -1
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@@ -33,7 +33,7 @@
" - 1b: ECX = MSB",
"[7] - Reserved"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"pcmpestrm xmm0, xmm1, 0_0_00_00_00b": {
unittests/InstructionCountCI/Secondary.json
+1 -1
View File
@@ -12,7 +12,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Comment": [
"MMX instructions are defined as optimal without SRA being used for these instructions.",
unittests/InstructionCountCI/SecondaryGroup.json
+1 -1
View File
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"sgdt [rax]": {
unittests/InstructionCountCI/SecondaryModRM.json
+1 -1
View File
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"xgetbv": {
unittests/InstructionCountCI/Secondary_32Bit.json
+1 -1
View File
@@ -7,7 +7,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"push fs": {
unittests/InstructionCountCI/Secondary_OpSize.json
+1 -1
View File
@@ -12,7 +12,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"movupd xmm0, xmm0": {
unittests/InstructionCountCI/Secondary_OpSize_FCMA.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"addsubpd xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_OpSize_SVE128.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"psrlw xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_OpSize_SVE256.json
+1 -1
View File
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"pmulhuw xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REP.json
+1 -1
View File
@@ -12,7 +12,7 @@
"FRINTTS",
"CSSC"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"movss xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REPNE.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FCMA",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"movsd xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REPNE_FCMA.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"addsubps xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REPNE_SVE128.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FCMA",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"cvtpd2dq xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REP_FRINTTS.json
+1 -1
View File
@@ -12,7 +12,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"cvttss2si eax, xmm0": {
unittests/InstructionCountCI/Secondary_SVE128.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"movmskps eax, xmm0": {
unittests/InstructionCountCI/VEX_map1.json
+1 -1
View File
@@ -13,7 +13,7 @@
"FLAGM2",
"FRINTTS"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vmovups xmm0, xmm0": {
unittests/InstructionCountCI/VEX_map1_FCMA.json
+1 -1
View File
@@ -8,7 +8,7 @@
"FCMA"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vaddsubpd xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/VEX_map1_FRINTTS.json
+1 -1
View File
@@ -13,7 +13,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vcvttss2si eax, xmm0": {
unittests/InstructionCountCI/VEX_map2.json
+1 -1
View File
@@ -11,7 +11,7 @@
"FLAGM2",
"SVEBITPERM"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vpshufb xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/VEX_map2_svebitperm.json
+1 -1
View File
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"pext eax, ebx, ecx": {
unittests/InstructionCountCI/VEX_map3.json
+1 -1
View File
@@ -8,7 +8,7 @@
"DisabledHostFeatures": [
"AFP"
],
"BinaryCacheVersion": 13
"BinaryCacheVersion": 14
},
"Instructions": {
"vpermq ymm0, ymm1, 1": {
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