From ed3fa2f1c6a0c046a82d22f9cc57e934da68e438 Mon Sep 17 00:00:00 2001 From: Simon Scherer Date: Fri, 4 Sep 2026 11:50:21 +0200 Subject: [PATCH 1/3] unittests/ASM: Test FST ST(0) tag word update --- unittests/ASM/FEX_bugs/fst_st0_tag_word.asm | 27 +++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 unittests/ASM/FEX_bugs/fst_st0_tag_word.asm diff --git a/unittests/ASM/FEX_bugs/fst_st0_tag_word.asm b/unittests/ASM/FEX_bugs/fst_st0_tag_word.asm new file mode 100644 index 000000000..1194a455b --- /dev/null +++ b/unittests/ASM/FEX_bugs/fst_st0_tag_word.asm @@ -0,0 +1,27 @@ +%ifdef CONFIG +{ + "RegData": { + "RAX": "0x1" + } +} +%endif + + +fxrstor [rel .fxsave_data] +fst st0 + +fxsave [rel .save] +movzx eax, byte [rel .save + 4] + +hlt + +align 16 +.fxsave_data: +dw 0x037f ; FCW +dw 0x0000 ; FSW +dw 0x0000 ; FTW +times 506 db 0 + +align 16 +.save: +times 64 dq 0 From 7236c2bf0a3aea132051b796a5730958a269ba09 Mon Sep 17 00:00:00 2001 From: Simon Scherer Date: Fri, 4 Sep 2026 11:50:25 +0200 Subject: [PATCH 2/3] Fix x87 tag word not updating on FST ST(0) self-store --- .../Source/Interface/Core/OpcodeDispatcher/X87.cpp | 4 +--- .../IR/Passes/x87StackOptimizationPass.cpp | 14 ++++++-------- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp index b0d0dfc14..b04f47e6f 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp @@ -139,9 +139,7 @@ void OpDispatchBuilder::FST(OpcodeArgs, IR::OpSize Width) { void OpDispatchBuilder::FSTToStack(OpcodeArgs) { const uint8_t Offset = Op->OP & 7; - if (Offset != 0) { - _StoreStackToStack(Offset); - } + _StoreStackToStack(Offset); if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { _PopStackDestroy(); diff --git a/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp b/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp index 8dcc220e3..f205097a1 100644 --- a/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp +++ b/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp @@ -1041,15 +1041,13 @@ void X87StackOptimization::Run(IREmitter* Emit) { const auto* Op = IROp->C(); auto Offset = Op->StackLocation; - if (Offset != 0) { - auto Value = MigrateToSlowPath_IfInvalid(); + auto Value = MigrateToSlowPath_IfInvalid(); - // Need to store st0 to stack location - basically a copy. - if (SlowPath) { - StoreStackValueAtOffset_Slow(LoadStackValueAtOffset_Slow(), Offset); - } else { - StackData.setTop(*Value, Offset); - } + // Need to store st0 to stack location - basically a copy. + if (SlowPath) { + StoreStackValueAtOffset_Slow(LoadStackValueAtOffset_Slow(), Offset); + } else { + StackData.setTop(*Value, Offset); } break; } From 040d3115d2d3ed5c6d0dce68e95c12e496c79243 Mon Sep 17 00:00:00 2001 From: Simon Scherer Date: Fri, 4 Sep 2026 11:53:13 +0200 Subject: [PATCH 3/3] InstcountCI: Update --- FEXCore/include/FEXCore/Core/DiskCache.h | 2 +- unittests/InstructionCountCI/AFP/H0F3A.json | 2 +- .../AFP/SVE256/Secondary.json | 2 +- .../AFP/SVE256/Secondary_REP.json | 2 +- .../AFP/SVE256/Secondary_REPNE.json | 2 +- .../InstructionCountCI/AFP/Secondary.json | 2 +- .../InstructionCountCI/AFP/Secondary_REP.json | 2 +- .../AFP/Secondary_REPNE.json | 2 +- .../InstructionCountCI/AFP/VEX_map1.json | 2 +- .../InstructionCountCI/AFP/VEX_map3.json | 2 +- unittests/InstructionCountCI/AVX128/FMA4.json | 2 +- .../InstructionCountCI/AVX128/VEX_map1.json | 2 +- .../AVX128/VEX_map1_FCMA.json | 2 +- .../AVX128/VEX_map1_SVE128.json | 2 +- .../AVX128/VEX_map1_flagm.json | 2 +- .../InstructionCountCI/AVX128/VEX_map2.json | 2 +- .../AVX128/VEX_map2_AFP.json | 2 +- .../AVX128/VEX_map2_SVE128.json | 2 +- .../AVX128/VEX_map2_flagm.json | 2 +- .../InstructionCountCI/AVX128/VEX_map3.json | 2 +- .../AVX128/VEX_map3_SVE128.json | 2 +- .../AVX128/VEX_map_group.json | 2 +- unittests/InstructionCountCI/Atomics.json | 2 +- .../InstructionCountCI/Crypto/H0F38.json | 2 +- .../Crypto/H0F38_SVE128.json | 2 +- .../InstructionCountCI/Crypto/H0F3A.json | 2 +- unittests/InstructionCountCI/DDD.json | 2 +- .../FEXOpt/AddressingLimitations.json | 2 +- .../FEXOpt/AddressingLimitations_32Bit.json | 2 +- .../InstructionCountCI/FEXOpt/MultiInst.json | 2 +- .../FEXOpt/MultiInst_32bit.json | 2 +- .../FEXOpt/MultiInst_AFP.json | 2 +- .../FEXOpt/MultiInst_TSO.json | 2 +- .../FEXOpt/MultiInst_TSO_32bit.json | 2 +- .../InstructionCountCI/FEXOpt/libnss.json | 2 +- .../InstructionCountCI/FlagM/Atomics.json | 2 +- .../InstructionCountCI/FlagM/FlagOpts.json | 2 +- unittests/InstructionCountCI/FlagM/H0F38.json | 2 +- .../InstructionCountCI/FlagM/HotBlocks.json | 2 +- .../FlagM/HotBlocks_32Bit.json | 2 +- .../FlagM/HotBlocks_AFP.json | 2 +- .../FlagM/HotBlocks_TSO_32Bit.json | 2 +- .../InstructionCountCI/FlagM/Primary.json | 2 +- .../FlagM/PrimaryGroup.json | 2 +- .../FlagM/Primary_32Bit.json | 2 +- .../InstructionCountCI/FlagM/Secondary.json | 2 +- .../FlagM/SecondaryGroup.json | 2 +- .../FlagM/SecondaryModRM.json | 2 +- .../FlagM/Secondary_OpSize.json | 2 +- .../FlagM/Secondary_REP.json | 2 +- .../FlagM/Secondary_REP_CSSC.json | 2 +- .../InstructionCountCI/FlagM/VEX_map1.json | 2 +- .../InstructionCountCI/FlagM/VEX_map2.json | 2 +- .../FlagM/VEX_map_group.json | 2 +- .../FlagM/x87-Crysis2Max-fmodel.json | 2 +- .../FlagM/x87-HalfLife.json | 222 +++++++++--------- .../FlagM/x87-Oblivion.json | 2 +- .../FlagM/x87-Psychonauts.json | 2 +- unittests/InstructionCountCI/FlagM/x87.json | 29 ++- .../FlagM/x87_f64-Crysis2Max-fmodel.json | 2 +- .../FlagM/x87_f64-HalfLife.json | 166 ++++++------- .../FlagM/x87_f64-Oblivion.json | 2 +- .../FlagM/x87_f64-Psychonauts.json | 2 +- .../InstructionCountCI/FlagM/x87_f64.json | 29 ++- unittests/InstructionCountCI/H0F38.json | 2 +- unittests/InstructionCountCI/H0F3A.json | 2 +- .../InstructionCountCI/H0F3A_SVE128.json | 2 +- .../InstructionCountCI/MOPS/Primary.json | 2 +- unittests/InstructionCountCI/Primary.json | 2 +- .../InstructionCountCI/PrimaryGroup.json | 2 +- .../InstructionCountCI/Primary_32Bit.json | 2 +- unittests/InstructionCountCI/RPRES/DDD.json | 2 +- .../InstructionCountCI/RPRES/Secondary.json | 2 +- .../RPRES/Secondary_REP_AFP.json | 2 +- .../RPRES/VEX_map1_AFP.json | 2 +- unittests/InstructionCountCI/Repeat.json | 2 +- .../InstructionCountCI/SSE42_Strings.json | 2 +- unittests/InstructionCountCI/Secondary.json | 2 +- .../InstructionCountCI/SecondaryGroup.json | 2 +- .../InstructionCountCI/SecondaryModRM.json | 2 +- .../InstructionCountCI/Secondary_32Bit.json | 2 +- .../InstructionCountCI/Secondary_OpSize.json | 2 +- .../Secondary_OpSize_FCMA.json | 2 +- .../Secondary_OpSize_SVE128.json | 2 +- .../Secondary_OpSize_SVE256.json | 2 +- .../InstructionCountCI/Secondary_REP.json | 2 +- .../InstructionCountCI/Secondary_REPNE.json | 2 +- .../Secondary_REPNE_FCMA.json | 2 +- .../Secondary_REPNE_SVE128.json | 2 +- .../Secondary_REP_FRINTTS.json | 2 +- .../InstructionCountCI/Secondary_SVE128.json | 2 +- unittests/InstructionCountCI/VEX_map1.json | 2 +- .../InstructionCountCI/VEX_map1_FCMA.json | 2 +- .../InstructionCountCI/VEX_map1_FRINTTS.json | 2 +- unittests/InstructionCountCI/VEX_map2.json | 2 +- .../VEX_map2_svebitperm.json | 2 +- unittests/InstructionCountCI/VEX_map3.json | 2 +- .../InstructionCountCI/VEX_map_group.json | 2 +- unittests/InstructionCountCI/X87ldst-SVE.json | 2 +- unittests/InstructionCountCI/x87.json | 29 ++- unittests/InstructionCountCI/x87_32Bit.json | 2 +- unittests/InstructionCountCI/x87_f64.json | 29 ++- .../InstructionCountCI/x87_f64_32Bit.json | 2 +- 103 files changed, 379 insertions(+), 319 deletions(-) diff --git a/FEXCore/include/FEXCore/Core/DiskCache.h b/FEXCore/include/FEXCore/Core/DiskCache.h index b81ad5302..5b2621d86 100644 --- a/FEXCore/include/FEXCore/Core/DiskCache.h +++ b/FEXCore/include/FEXCore/Core/DiskCache.h @@ -210,7 +210,7 @@ namespace DiskCache { // TODO: This header is in global installed header path, but uses internal headers. // Migrate this once that is fixed. - static constexpr uint16_t FormatVersion = 13; + static constexpr uint16_t FormatVersion = 14; FEX_DEFAULT_VISIBILITY uint16_t GetFormatVersion(); } // namespace DiskCache diff --git a/unittests/InstructionCountCI/AFP/H0F3A.json b/unittests/InstructionCountCI/AFP/H0F3A.json index 5b4612e17..4d09e5e52 100644 --- a/unittests/InstructionCountCI/AFP/H0F3A.json +++ b/unittests/InstructionCountCI/AFP/H0F3A.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "roundss xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json index 2c5d356f8..5ee585151 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "cvtpi2ps xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json index 8cbdbb996..2a916f760 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "RPRES" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "cvtsi2ss xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json index 0fb575dc3..57156b0f6 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "cvtsi2sd xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/Secondary.json b/unittests/InstructionCountCI/AFP/Secondary.json index 5c06da71e..12785789c 100644 --- a/unittests/InstructionCountCI/AFP/Secondary.json +++ b/unittests/InstructionCountCI/AFP/Secondary.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "cvtpi2ps xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/AFP/Secondary_REP.json b/unittests/InstructionCountCI/AFP/Secondary_REP.json index 5c7b89661..efbe92826 100644 --- a/unittests/InstructionCountCI/AFP/Secondary_REP.json +++ b/unittests/InstructionCountCI/AFP/Secondary_REP.json @@ -9,7 +9,7 @@ "SVE256", "RPRES" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "cvtsi2ss xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json index 3ff904827..3c2828940 100644 --- a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "cvtsi2sd xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/VEX_map1.json b/unittests/InstructionCountCI/AFP/VEX_map1.json index dfea0cfc4..40230d5df 100644 --- a/unittests/InstructionCountCI/AFP/VEX_map1.json +++ b/unittests/InstructionCountCI/AFP/VEX_map1.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "RPRES" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vsqrtss xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AFP/VEX_map3.json b/unittests/InstructionCountCI/AFP/VEX_map3.json index c93411f2c..a017caa7e 100644 --- a/unittests/InstructionCountCI/AFP/VEX_map3.json +++ b/unittests/InstructionCountCI/AFP/VEX_map3.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vroundss xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/AVX128/FMA4.json b/unittests/InstructionCountCI/AVX128/FMA4.json index b1a829a44..9d06127c3 100644 --- a/unittests/InstructionCountCI/AVX128/FMA4.json +++ b/unittests/InstructionCountCI/AVX128/FMA4.json @@ -7,7 +7,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vfmaddsubps xmm0, xmm1, xmm2, xmm3": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json index 3cb177e3e..48b5998db 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json @@ -13,7 +13,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vmovups xmm0, xmm0": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json b/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json index dfe385eeb..89132a78d 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vaddsubpd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json index 63715406c..fe0150588 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json @@ -10,7 +10,7 @@ "FLAGM2", "SVE256" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vmovntps [rax], xmm0": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json index 9601af5c3..a2e6f616d 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json @@ -10,7 +10,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vucomiss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json index 1188543eb..944bb5bf2 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vpshufb xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json b/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json index e95eff5d2..6932b259c 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json @@ -8,7 +8,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vfmadd132ss xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json index 2bc68bc09..ffa2f6a43 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json @@ -10,7 +10,7 @@ "FLAGM2", "SVE256" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vmovntdqa xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json index fbad602a6..2421ae018 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json @@ -11,7 +11,7 @@ "SVE256", "SVEBITPERM" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vtestps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3.json b/unittests/InstructionCountCI/AVX128/VEX_map3.json index fcf688cd6..7ec98f632 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map3.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map3.json @@ -7,7 +7,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vpermq ymm0, ymm1, 1": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json index 8f2725abd..c41a3fc57 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json @@ -8,7 +8,7 @@ "AFP", "SVE256" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vblendvps xmm0, xmm1, xmm2, xmm3": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map_group.json b/unittests/InstructionCountCI/AVX128/VEX_map_group.json index 6074a7931..6b8fb7c93 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map_group.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map_group.json @@ -9,7 +9,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vpsrlw xmm0, xmm1, 0": { diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json index 21c575457..4b493fd45 100644 --- a/unittests/InstructionCountCI/Atomics.json +++ b/unittests/InstructionCountCI/Atomics.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "lock add byte [rax], cl": { diff --git a/unittests/InstructionCountCI/Crypto/H0F38.json b/unittests/InstructionCountCI/Crypto/H0F38.json index e7ea937a2..8ad039923 100644 --- a/unittests/InstructionCountCI/Crypto/H0F38.json +++ b/unittests/InstructionCountCI/Crypto/H0F38.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "sha1nexte xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json b/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json index 8496071a2..f1f538359 100644 --- a/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json +++ b/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "sha1nexte xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json index 71325119d..55af9e846 100644 --- a/unittests/InstructionCountCI/Crypto/H0F3A.json +++ b/unittests/InstructionCountCI/Crypto/H0F3A.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "pclmulqdq xmm0, xmm1, 00000b": { diff --git a/unittests/InstructionCountCI/DDD.json b/unittests/InstructionCountCI/DDD.json index 626e73935..b47ad9c66 100644 --- a/unittests/InstructionCountCI/DDD.json +++ b/unittests/InstructionCountCI/DDD.json @@ -10,7 +10,7 @@ "AFP", "RPRES" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Comment": [ "These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers", diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json index 0461a99a9..5238d75ab 100644 --- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json +++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json @@ -8,7 +8,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Comment": [ "Instructions that explicitly push against the limits of ARM's loadstore instructions" diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json index d35af386b..4da21611f 100644 --- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json +++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json @@ -8,7 +8,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Comment": [ "Instructions that explicitly push against the limits of ARM's loadstore instructions" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst.json b/unittests/InstructionCountCI/FEXOpt/MultiInst.json index 39e99f0da..f773c15f7 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst.json @@ -13,7 +13,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json index d7d4737a8..c82831888 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json @@ -11,7 +11,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json index 4488e4bba..f135b98b0 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json @@ -9,7 +9,7 @@ "SVE256", "RPRES" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json index d6b2193b6..33047e62f 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json @@ -14,7 +14,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json index 4f8b863fe..5f8647aa9 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json @@ -14,7 +14,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/libnss.json b/unittests/InstructionCountCI/FEXOpt/libnss.json index ba3b4f90c..4a5be0bab 100644 --- a/unittests/InstructionCountCI/FEXOpt/libnss.json +++ b/unittests/InstructionCountCI/FEXOpt/libnss.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Comment": [], "Instructions": { diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json index 5d914c106..b88f087a5 100644 --- a/unittests/InstructionCountCI/FlagM/Atomics.json +++ b/unittests/InstructionCountCI/FlagM/Atomics.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "lock add byte [rax], cl": { diff --git a/unittests/InstructionCountCI/FlagM/FlagOpts.json b/unittests/InstructionCountCI/FlagM/FlagOpts.json index 5c6cab9e9..19259b0b5 100644 --- a/unittests/InstructionCountCI/FlagM/FlagOpts.json +++ b/unittests/InstructionCountCI/FlagM/FlagOpts.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "Chained add": { diff --git a/unittests/InstructionCountCI/FlagM/H0F38.json b/unittests/InstructionCountCI/FlagM/H0F38.json index e53f9d916..67a671643 100644 --- a/unittests/InstructionCountCI/FlagM/H0F38.json +++ b/unittests/InstructionCountCI/FlagM/H0F38.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "ptest xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json index 7ed6ccd86..535708d26 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "The Witcher 3": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json index 3f775d891..cbb424f20 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "Sonic Mania movie player": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json index 52fe76411..36212787b 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json @@ -10,7 +10,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "FMOD scalar loop": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json index 093f3a26b..5c7b8281e 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "The Sims 1 hot block": { diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index 7de9d6883..24760f847 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "add bl, cl": { diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index a9124f1d8..97f3530e6 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "add al, 1": { diff --git a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json index a34199c9b..20597a275 100644 --- a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "push es": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index 596006b5b..e012c05ae 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -11,7 +11,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "ucomiss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json index 2800d7a98..994999e16 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json @@ -11,7 +11,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "sgdt [rax]": { diff --git a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json index 7ccd5d525..51eec452b 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json @@ -11,7 +11,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "xgetbv": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json index ac46b5d58..32dd087c0 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json @@ -11,7 +11,7 @@ "AFP", "FCMA" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "ucomisd xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP.json b/unittests/InstructionCountCI/FlagM/Secondary_REP.json index fa0e12859..fd5c68519 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_REP.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_REP.json @@ -12,7 +12,7 @@ "AFP", "CSSC" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "popcnt ax, bx": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json b/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json index 9df1a39a7..77d0ed1ee 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "popcnt ax, bx": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json index 384f94f11..fb05d4d6c 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map1.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vucomiss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map2.json b/unittests/InstructionCountCI/FlagM/VEX_map2.json index 314b88026..dc6cc85cb 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map2.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map2.json @@ -10,7 +10,7 @@ "AFP", "SVEBITPERM" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vtestps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map_group.json b/unittests/InstructionCountCI/FlagM/VEX_map_group.json index 3de397905..56690312b 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map_group.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map_group.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "blsr eax, ebx": { diff --git a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json index 164932f4d..a8956b98d 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json +++ b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json index 044597c10..550cb996b 100644 --- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "Block1": { @@ -2167,7 +2167,7 @@ }, "Block8": { "x86InstructionCount": 25, - "ExpectedInstructionCount": 72, + "ExpectedInstructionCount": 76, "x86Insts": [ "fstp st0", "fstp st3", @@ -2197,49 +2197,31 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1051]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", "add x21, x28, x20, lsl #4", "ldr q2, [x21, #1056]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x21, x28, x20, lsl #4", - "ldr q3, [x21, #1056]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x21, x28, x20, lsl #4", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x22, x28, x22, lsl #4", - "ldr q4, [x22, #1056]", - "strb wzr, [x28, #1049]", - "add w20, w20, #0x2 (2)", - "and w20, w20, #0x7", - "add x23, x28, x20, lsl #4", - "strb wzr, [x28, #1049]", - "str x30, [sp, #-16]!", - "mov v0.16b, v3.16b", - "ldr x0, [x28, #1672]", - "ldr x3, [x28, #1680]", - "blr x0", - "ldr x30, [sp], #16", - "fmov s5, s0", - "str s5, [x8, #56]", - "strb wzr, [x28, #1049]", - "str x30, [sp, #-16]!", - "mov v0.16b, v4.16b", - "ldr x0, [x28, #1672]", - "ldr x3, [x28, #1680]", - "blr x0", - "ldr x30, [sp], #16", - "fmov s5, s0", - "str s5, [x8, #44]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x12, x28, x20, lsl #4", + "add x23, x28, x22, lsl #4", + "ldr q3, [x23, #1056]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x23, x28, x22, lsl #4", + "ldr q4, [x23, #1056]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x12, x28, x22, lsl #4", "ldr q5, [x12, #1056]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x12, x28, x22, lsl #4", + "add w13, w22, #0x1 (1)", + "and w13, w13, #0x7", + "add x13, x28, x13, lsl #4", + "ldr q6, [x13, #1056]", + "strb wzr, [x28, #1049]", + "add w22, w22, #0x2 (2)", + "and w22, w22, #0x7", + "add x14, x28, x22, lsl #4", "strb wzr, [x28, #1049]", "str x30, [sp, #-16]!", "mov v0.16b, v5.16b", @@ -2247,32 +2229,54 @@ "ldr x3, [x28, #1680]", "blr x0", "ldr x30, [sp], #16", - "fmov s6, s0", - "str s6, [x8, #40]", + "fmov s7, s0", + "str s7, [x8, #56]", + "strb wzr, [x28, #1049]", "str x30, [sp, #-16]!", - "mov v0.16b, v2.16b", + "mov v0.16b, v6.16b", + "ldr x0, [x28, #1672]", + "ldr x3, [x28, #1680]", + "blr x0", + "ldr x30, [sp], #16", + "fmov s7, s0", + "str s7, [x8, #44]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x22, x28, x22, lsl #4", + "ldr q7, [x22, #1056]", + "strb wzr, [x28, #1049]", + "str x30, [sp, #-16]!", + "mov v0.16b, v7.16b", + "ldr x0, [x28, #1672]", + "ldr x3, [x28, #1680]", + "blr x0", + "ldr x30, [sp], #16", + "fmov s8, s0", + "str s8, [x8, #40]", + "str x30, [sp, #-16]!", + "mov v0.16b, v3.16b", "ldr x0, [x28, #1688]", "ldr x3, [x28, #1696]", "blr x0", "ldr x30, [sp], #16", - "fmov d6, d0", - "str d6, [x8]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "mov w13, #0x24", - "movk w13, #0x1, lsl #16", - "str w13, [x8, #-4]!", + "fmov d8, d0", + "str d8, [x8]", + "mov w15, #0x24", + "movk w15, #0x1, lsl #16", + "str w15, [x8, #-4]!", "strb w20, [x28, #1051]", - "str q3, [x21, #1056]", - "str q4, [x22, #1056]", - "str q5, [x23, #1056]", - "str q2, [x12, #1056]", + "str q2, [x21, #1056]", + "str q4, [x23, #1056]", + "str q5, [x12, #1056]", + "str q6, [x13, #1056]", + "str q7, [x14, #1056]", + "str q3, [x22, #1056]", "strb wzr, [x28, #1202]" ] }, "Block9": { "x86InstructionCount": 25, - "ExpectedInstructionCount": 72, + "ExpectedInstructionCount": 76, "x86Insts": [ "fstp st0", "fstp st3", @@ -2302,49 +2306,31 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1051]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", "add x21, x28, x20, lsl #4", "ldr q2, [x21, #1056]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x21, x28, x20, lsl #4", - "ldr q3, [x21, #1056]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x21, x28, x20, lsl #4", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x22, x28, x22, lsl #4", - "ldr q4, [x22, #1056]", - "strb wzr, [x28, #1049]", - "add w20, w20, #0x2 (2)", - "and w20, w20, #0x7", - "add x23, x28, x20, lsl #4", - "strb wzr, [x28, #1049]", - "str x30, [sp, #-16]!", - "mov v0.16b, v3.16b", - "ldr x0, [x28, #1672]", - "ldr x3, [x28, #1680]", - "blr x0", - "ldr x30, [sp], #16", - "fmov s5, s0", - "str s5, [x8, #56]", - "strb wzr, [x28, #1049]", - "str x30, [sp, #-16]!", - "mov v0.16b, v4.16b", - "ldr x0, [x28, #1672]", - "ldr x3, [x28, #1680]", - "blr x0", - "ldr x30, [sp], #16", - "fmov s5, s0", - "str s5, [x8, #44]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x12, x28, x20, lsl #4", + "add x23, x28, x22, lsl #4", + "ldr q3, [x23, #1056]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x23, x28, x22, lsl #4", + "ldr q4, [x23, #1056]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x12, x28, x22, lsl #4", "ldr q5, [x12, #1056]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x12, x28, x22, lsl #4", + "add w13, w22, #0x1 (1)", + "and w13, w13, #0x7", + "add x13, x28, x13, lsl #4", + "ldr q6, [x13, #1056]", + "strb wzr, [x28, #1049]", + "add w22, w22, #0x2 (2)", + "and w22, w22, #0x7", + "add x14, x28, x22, lsl #4", "strb wzr, [x28, #1049]", "str x30, [sp, #-16]!", "mov v0.16b, v5.16b", @@ -2352,26 +2338,48 @@ "ldr x3, [x28, #1680]", "blr x0", "ldr x30, [sp], #16", - "fmov s6, s0", - "str s6, [x8, #40]", + "fmov s7, s0", + "str s7, [x8, #56]", + "strb wzr, [x28, #1049]", "str x30, [sp, #-16]!", - "mov v0.16b, v2.16b", + "mov v0.16b, v6.16b", + "ldr x0, [x28, #1672]", + "ldr x3, [x28, #1680]", + "blr x0", + "ldr x30, [sp], #16", + "fmov s7, s0", + "str s7, [x8, #44]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x22, x28, x22, lsl #4", + "ldr q7, [x22, #1056]", + "strb wzr, [x28, #1049]", + "str x30, [sp, #-16]!", + "mov v0.16b, v7.16b", + "ldr x0, [x28, #1672]", + "ldr x3, [x28, #1680]", + "blr x0", + "ldr x30, [sp], #16", + "fmov s8, s0", + "str s8, [x8, #40]", + "str x30, [sp, #-16]!", + "mov v0.16b, v3.16b", "ldr x0, [x28, #1688]", "ldr x3, [x28, #1696]", "blr x0", "ldr x30, [sp], #16", - "fmov d6, d0", - "str d6, [x8]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "mov w13, #0x24", - "movk w13, #0x1, lsl #16", - "str w13, [x8, #-4]!", + "fmov d8, d0", + "str d8, [x8]", + "mov w15, #0x24", + "movk w15, #0x1, lsl #16", + "str w15, [x8, #-4]!", "strb w20, [x28, #1051]", - "str q3, [x21, #1056]", - "str q4, [x22, #1056]", - "str q5, [x23, #1056]", - "str q2, [x12, #1056]", + "str q2, [x21, #1056]", + "str q4, [x23, #1056]", + "str q5, [x12, #1056]", + "str q6, [x13, #1056]", + "str q7, [x14, #1056]", + "str q3, [x22, #1056]", "strb wzr, [x28, #1202]" ] }, diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json index 482455235..9b86ea0eb 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json index cd8dd67b9..f4506c473 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index 5ccebb052..b8c424181 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -11,7 +11,7 @@ "CSSC", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "fadd dword [rax]": { @@ -7381,11 +7381,21 @@ ] }, "fst st0": { - "ExpectedInstructionCount": 0, + "ExpectedInstructionCount": 9, "Comment": [ "0xdd 11b 0xd0 /2" ], - "ExpectedArm64ASM": [] + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #1051]", + "add x21, x28, x20, lsl #4", + "ldr q2, [x21, #1056]", + "str q2, [x21, #1056]", + "ldrb w21, [x28, #1202]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", + "strb w20, [x28, #1202]" + ] }, "fst st1": { "ExpectedInstructionCount": 12, @@ -7528,19 +7538,20 @@ ] }, "fstp st0": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": [ "0xdd 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1051]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1051]", + "add x21, x28, x20, lsl #4", + "ldr q2, [x21, #1056]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1051]", + "str q2, [x21, #1056]", "ldrb w21, [x28, #1202]", "mov w22, #0x1", - "add w20, w20, #0x7 (7)", - "and w20, w20, #0x7", "lsl w20, w22, w20", "bic w20, w21, w20", "strb w20, [x28, #1202]" diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json index 1e651a012..56b4d3018 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json index da0e99ac3..e64244163 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "Block1": { @@ -892,7 +892,7 @@ }, "Block8": { "x86InstructionCount": 25, - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 51, "x86Insts": [ "fstp st0", "fstp st3", @@ -922,57 +922,61 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1051]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", "add x21, x28, x20, lsl #4", "ldr d2, [x21, #1056]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x21, x28, x20, lsl #4", - "ldr d3, [x21, #1056]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x21, x28, x20, lsl #4", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x22, x28, x22, lsl #4", - "ldr d4, [x22, #1056]", - "strb wzr, [x28, #1049]", - "add w20, w20, #0x2 (2)", - "and w20, w20, #0x7", - "add x23, x28, x20, lsl #4", - "strb wzr, [x28, #1049]", - "fcvt s5, d3", - "str s5, [x8, #56]", - "strb wzr, [x28, #1049]", - "fcvt s5, d4", - "str s5, [x8, #44]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x12, x28, x20, lsl #4", + "add x23, x28, x22, lsl #4", + "ldr d3, [x23, #1056]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x23, x28, x22, lsl #4", + "ldr d4, [x23, #1056]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x12, x28, x22, lsl #4", "ldr d5, [x12, #1056]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x12, x28, x22, lsl #4", + "add w13, w22, #0x1 (1)", + "and w13, w13, #0x7", + "add x13, x28, x13, lsl #4", + "ldr d6, [x13, #1056]", "strb wzr, [x28, #1049]", - "fcvt s6, d5", - "str s6, [x8, #40]", - "str d2, [x8]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "mov w13, #0x24", - "movk w13, #0x1, lsl #16", - "str w13, [x8, #-4]!", + "add w22, w22, #0x2 (2)", + "and w22, w22, #0x7", + "add x14, x28, x22, lsl #4", + "strb wzr, [x28, #1049]", + "fcvt s7, d5", + "str s7, [x8, #56]", + "strb wzr, [x28, #1049]", + "fcvt s7, d6", + "str s7, [x8, #44]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x22, x28, x22, lsl #4", + "ldr d7, [x22, #1056]", + "strb wzr, [x28, #1049]", + "fcvt s8, d7", + "str s8, [x8, #40]", + "str d3, [x8]", + "mov w15, #0x24", + "movk w15, #0x1, lsl #16", + "str w15, [x8, #-4]!", "strb w20, [x28, #1051]", - "str d3, [x21, #1056]", - "str d4, [x22, #1056]", - "str d5, [x23, #1056]", - "str d2, [x12, #1056]", + "str d2, [x21, #1056]", + "str d4, [x23, #1056]", + "str d5, [x12, #1056]", + "str d6, [x13, #1056]", + "str d7, [x14, #1056]", + "str d3, [x22, #1056]", "strb wzr, [x28, #1202]" ] }, "Block9": { "x86InstructionCount": 25, - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 51, "x86Insts": [ "fstp st0", "fstp st3", @@ -1002,51 +1006,55 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1051]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", "add x21, x28, x20, lsl #4", "ldr d2, [x21, #1056]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x21, x28, x20, lsl #4", - "ldr d3, [x21, #1056]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x21, x28, x20, lsl #4", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x22, x28, x22, lsl #4", - "ldr d4, [x22, #1056]", - "strb wzr, [x28, #1049]", - "add w20, w20, #0x2 (2)", - "and w20, w20, #0x7", - "add x23, x28, x20, lsl #4", - "strb wzr, [x28, #1049]", - "fcvt s5, d3", - "str s5, [x8, #56]", - "strb wzr, [x28, #1049]", - "fcvt s5, d4", - "str s5, [x8, #44]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x12, x28, x20, lsl #4", + "add x23, x28, x22, lsl #4", + "ldr d3, [x23, #1056]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x23, x28, x22, lsl #4", + "ldr d4, [x23, #1056]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x12, x28, x22, lsl #4", "ldr d5, [x12, #1056]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x12, x28, x22, lsl #4", + "add w13, w22, #0x1 (1)", + "and w13, w13, #0x7", + "add x13, x28, x13, lsl #4", + "ldr d6, [x13, #1056]", "strb wzr, [x28, #1049]", - "fcvt s6, d5", - "str s6, [x8, #40]", - "str d2, [x8]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "mov w13, #0x24", - "movk w13, #0x1, lsl #16", - "str w13, [x8, #-4]!", + "add w22, w22, #0x2 (2)", + "and w22, w22, #0x7", + "add x14, x28, x22, lsl #4", + "strb wzr, [x28, #1049]", + "fcvt s7, d5", + "str s7, [x8, #56]", + "strb wzr, [x28, #1049]", + "fcvt s7, d6", + "str s7, [x8, #44]", + "add w22, w22, #0x1 (1)", + "and w22, w22, #0x7", + "add x22, x28, x22, lsl #4", + "ldr d7, [x22, #1056]", + "strb wzr, [x28, #1049]", + "fcvt s8, d7", + "str s8, [x8, #40]", + "str d3, [x8]", + "mov w15, #0x24", + "movk w15, #0x1, lsl #16", + "str w15, [x8, #-4]!", "strb w20, [x28, #1051]", - "str d3, [x21, #1056]", - "str d4, [x22, #1056]", - "str d5, [x23, #1056]", - "str d2, [x12, #1056]", + "str d2, [x21, #1056]", + "str d4, [x23, #1056]", + "str d5, [x12, #1056]", + "str d6, [x13, #1056]", + "str d7, [x14, #1056]", + "str d3, [x22, #1056]", "strb wzr, [x28, #1202]" ] }, diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json index 9a8b449ec..3c30e8ebb 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json index 082e0fc17..ac7aace7c 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index 287491757..2994cd776 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "fadd dword [rax]": { @@ -5914,11 +5914,21 @@ ] }, "fst st0": { - "ExpectedInstructionCount": 0, + "ExpectedInstructionCount": 9, "Comment": [ "0xdd 11b 0xd0 /2" ], - "ExpectedArm64ASM": [] + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #1051]", + "add x21, x28, x20, lsl #4", + "ldr d2, [x21, #1056]", + "str d2, [x21, #1056]", + "ldrb w21, [x28, #1202]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", + "strb w20, [x28, #1202]" + ] }, "fst st1": { "ExpectedInstructionCount": 12, @@ -6061,19 +6071,20 @@ ] }, "fstp st0": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": [ "0xdd 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1051]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1051]", + "add x21, x28, x20, lsl #4", + "ldr d2, [x21, #1056]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1051]", + "str d2, [x21, #1056]", "ldrb w21, [x28, #1202]", "mov w22, #0x1", - "add w20, w20, #0x7 (7)", - "and w20, w20, #0x7", "lsl w20, w22, w20", "bic w20, w21, w20", "strb w20, [x28, #1202]" diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index bb0945f2a..4ba4ef2c4 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -10,7 +10,7 @@ "FLAGM2", "CRYPTO" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "pshufb mm0, mm1": { diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index 24e2af7cd..b7fff27ca 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -8,7 +8,7 @@ "AFP", "CRYPTO" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Comment": [ "SSE4.2 string instructions are skipped here.", diff --git a/unittests/InstructionCountCI/H0F3A_SVE128.json b/unittests/InstructionCountCI/H0F3A_SVE128.json index 33a4d4301..75923b667 100644 --- a/unittests/InstructionCountCI/H0F3A_SVE128.json +++ b/unittests/InstructionCountCI/H0F3A_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "dpps xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/MOPS/Primary.json b/unittests/InstructionCountCI/MOPS/Primary.json index 0eac8ae69..da529b492 100644 --- a/unittests/InstructionCountCI/MOPS/Primary.json +++ b/unittests/InstructionCountCI/MOPS/Primary.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "rep movsb": { diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 087ab4856..7147806a3 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -10,7 +10,7 @@ "FLAGM2", "MOPS" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "add bl, cl": { diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index bb425e50f..dd19baa54 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Comment": [ "Instructions in this table that are marked optimal don't have their flag calculation part of this assumption", diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index 68685683e..1add8ff41 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -9,7 +9,7 @@ "FlagM", "FlagM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "push es": { diff --git a/unittests/InstructionCountCI/RPRES/DDD.json b/unittests/InstructionCountCI/RPRES/DDD.json index b67d29dad..3fb7b0ffc 100644 --- a/unittests/InstructionCountCI/RPRES/DDD.json +++ b/unittests/InstructionCountCI/RPRES/DDD.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "pfrcpv mm0, mm1": { diff --git a/unittests/InstructionCountCI/RPRES/Secondary.json b/unittests/InstructionCountCI/RPRES/Secondary.json index daeebf430..8ffa199f4 100644 --- a/unittests/InstructionCountCI/RPRES/Secondary.json +++ b/unittests/InstructionCountCI/RPRES/Secondary.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "rsqrtps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json index 48e70bbe6..423a3c0b4 100644 --- a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json +++ b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "rsqrtss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json index d1836de15..ceb8c5400 100644 --- a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json +++ b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json @@ -8,7 +8,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vrsqrtps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Repeat.json b/unittests/InstructionCountCI/Repeat.json index 919b79ac5..da01c13f3 100644 --- a/unittests/InstructionCountCI/Repeat.json +++ b/unittests/InstructionCountCI/Repeat.json @@ -6,7 +6,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": {} } diff --git a/unittests/InstructionCountCI/SSE42_Strings.json b/unittests/InstructionCountCI/SSE42_Strings.json index ffcfaaa32..0a0c8a8a1 100644 --- a/unittests/InstructionCountCI/SSE42_Strings.json +++ b/unittests/InstructionCountCI/SSE42_Strings.json @@ -33,7 +33,7 @@ " - 1b: ECX = MSB", "[7] - Reserved" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "pcmpestrm xmm0, xmm1, 0_0_00_00_00b": { diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 9c2deda8b..46fdb804c 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Comment": [ "MMX instructions are defined as optimal without SRA being used for these instructions.", diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index da4339536..f556717b3 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "sgdt [rax]": { diff --git a/unittests/InstructionCountCI/SecondaryModRM.json b/unittests/InstructionCountCI/SecondaryModRM.json index aaaac72bd..d7c411ac9 100644 --- a/unittests/InstructionCountCI/SecondaryModRM.json +++ b/unittests/InstructionCountCI/SecondaryModRM.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "xgetbv": { diff --git a/unittests/InstructionCountCI/Secondary_32Bit.json b/unittests/InstructionCountCI/Secondary_32Bit.json index fdd30d309..803f15788 100644 --- a/unittests/InstructionCountCI/Secondary_32Bit.json +++ b/unittests/InstructionCountCI/Secondary_32Bit.json @@ -7,7 +7,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "push fs": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index 50b9786e6..a527fd9cd 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "movupd xmm0, xmm0": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json index 9ea47d593..8b6b2e60d 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "addsubpd xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json index d9788ad5a..4a329d75c 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "psrlw xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json index cd78de9b6..696c70217 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "pmulhuw xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index ae95c6160..c02480995 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -12,7 +12,7 @@ "FRINTTS", "CSSC" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "movss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index d2e4cc18c..396efb6bb 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -10,7 +10,7 @@ "FCMA", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "movsd xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json index 52e64fa38..9a43e1ca3 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json +++ b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "addsubps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json index ed6ed2315..79d4384c9 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json @@ -10,7 +10,7 @@ "FCMA", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "cvtpd2dq xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json b/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json index c2919a0e7..23274d3b9 100644 --- a/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json +++ b/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "cvttss2si eax, xmm0": { diff --git a/unittests/InstructionCountCI/Secondary_SVE128.json b/unittests/InstructionCountCI/Secondary_SVE128.json index 248025628..5922fb170 100644 --- a/unittests/InstructionCountCI/Secondary_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "movmskps eax, xmm0": { diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 03ffc7b86..9742d2b6e 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -13,7 +13,7 @@ "FLAGM2", "FRINTTS" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vmovups xmm0, xmm0": { diff --git a/unittests/InstructionCountCI/VEX_map1_FCMA.json b/unittests/InstructionCountCI/VEX_map1_FCMA.json index 5734a1155..2c5209302 100644 --- a/unittests/InstructionCountCI/VEX_map1_FCMA.json +++ b/unittests/InstructionCountCI/VEX_map1_FCMA.json @@ -8,7 +8,7 @@ "FCMA" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vaddsubpd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json index f1ebb77c0..5346f817f 100644 --- a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json +++ b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json @@ -13,7 +13,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vcvttss2si eax, xmm0": { diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index 8d93db926..e88cdf021 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -11,7 +11,7 @@ "FLAGM2", "SVEBITPERM" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vpshufb xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map2_svebitperm.json b/unittests/InstructionCountCI/VEX_map2_svebitperm.json index 3f06859d4..a898d0f5d 100644 --- a/unittests/InstructionCountCI/VEX_map2_svebitperm.json +++ b/unittests/InstructionCountCI/VEX_map2_svebitperm.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "pext eax, ebx, ecx": { diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 73cfa837a..6d16b23e9 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -8,7 +8,7 @@ "DisabledHostFeatures": [ "AFP" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vpermq ymm0, ymm1, 1": { diff --git a/unittests/InstructionCountCI/VEX_map_group.json b/unittests/InstructionCountCI/VEX_map_group.json index 4307dc624..b1ed37388 100644 --- a/unittests/InstructionCountCI/VEX_map_group.json +++ b/unittests/InstructionCountCI/VEX_map_group.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "vpsrlw xmm0, xmm1, 0": { diff --git a/unittests/InstructionCountCI/X87ldst-SVE.json b/unittests/InstructionCountCI/X87ldst-SVE.json index 4433fbff8..99ab7e554 100644 --- a/unittests/InstructionCountCI/X87ldst-SVE.json +++ b/unittests/InstructionCountCI/X87ldst-SVE.json @@ -11,7 +11,7 @@ "FLAGM2", "RPRES" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "fstp tword [rax]": { diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index db8b1b45b..f305c18a1 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -10,7 +10,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "fadd dword [rax]": { @@ -7316,11 +7316,21 @@ ] }, "fst st0": { - "ExpectedInstructionCount": 0, + "ExpectedInstructionCount": 9, "Comment": [ "0xdd 11b 0xd0 /2" ], - "ExpectedArm64ASM": [] + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #1051]", + "add x21, x28, x20, lsl #4", + "ldr q2, [x21, #1056]", + "str q2, [x21, #1056]", + "ldrb w21, [x28, #1202]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", + "strb w20, [x28, #1202]" + ] }, "fst st1": { "ExpectedInstructionCount": 12, @@ -7463,19 +7473,20 @@ ] }, "fstp st0": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": [ "0xdd 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1051]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1051]", + "add x21, x28, x20, lsl #4", + "ldr q2, [x21, #1056]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1051]", + "str q2, [x21, #1056]", "ldrb w21, [x28, #1202]", "mov w22, #0x1", - "add w20, w20, #0x7 (7)", - "and w20, w20, #0x7", "lsl w20, w22, w20", "bic w20, w21, w20", "strb w20, [x28, #1202]" diff --git a/unittests/InstructionCountCI/x87_32Bit.json b/unittests/InstructionCountCI/x87_32Bit.json index a43b01521..b728a0b34 100644 --- a/unittests/InstructionCountCI/x87_32Bit.json +++ b/unittests/InstructionCountCI/x87_32Bit.json @@ -10,7 +10,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "Multiple fld/fst": { diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index 90d218723..36bc51ab5 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "fadd dword [rax]": { @@ -5953,11 +5953,21 @@ ] }, "fst st0": { - "ExpectedInstructionCount": 0, + "ExpectedInstructionCount": 9, "Comment": [ "0xdd 11b 0xd0 /2" ], - "ExpectedArm64ASM": [] + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #1051]", + "add x21, x28, x20, lsl #4", + "ldr d2, [x21, #1056]", + "str d2, [x21, #1056]", + "ldrb w21, [x28, #1202]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", + "strb w20, [x28, #1202]" + ] }, "fst st1": { "ExpectedInstructionCount": 12, @@ -6100,19 +6110,20 @@ ] }, "fstp st0": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": [ "0xdd 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1051]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1051]", + "add x21, x28, x20, lsl #4", + "ldr d2, [x21, #1056]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1051]", + "str d2, [x21, #1056]", "ldrb w21, [x28, #1202]", "mov w22, #0x1", - "add w20, w20, #0x7 (7)", - "and w20, w20, #0x7", "lsl w20, w22, w20", "bic w20, w21, w20", "strb w20, [x28, #1202]" diff --git a/unittests/InstructionCountCI/x87_f64_32Bit.json b/unittests/InstructionCountCI/x87_f64_32Bit.json index 3b0d79966..316e38681 100644 --- a/unittests/InstructionCountCI/x87_f64_32Bit.json +++ b/unittests/InstructionCountCI/x87_f64_32Bit.json @@ -15,7 +15,7 @@ "SVE256", "CSSC" ], - "BinaryCacheVersion": 13 + "BinaryCacheVersion": 14 }, "Instructions": { "fstp dword [ebx*4+0x204a20]": {