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Code Issues Packages Projects Releases 67 Wiki Activity
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Commit Graph
1678 Commits
Author SHA1 Message Date
Ryan Houdek ef4c4f6e9b FEXCore: Disable vixl linking if vixl disasm or simulator is disabled 
This was mostly there, just needed to remove some extraneous headers and
only insert vixl in to the library list if the options were enabled.
 2024-08-16 07:29:41 -07:00
Ryan Houdek 2eb7a9ff28 OpcodeDispatcher: Remove old bad assumption in INC/DEC 
Somewhere there was an assumption made that INC and DEC supported the
repeat prefix. This isn't actually the case, while the prefix can be
encoded, it is a nop and should only expect to be used for padding.

Adds a unittest to ensure that behaviour is as expected.
 2024-08-15 10:22:31 -07:00
Ryan Houdek 933c65d805 Merge pull request #3956 from alyssarosenzweig/opt/pop-return 
small optimizations for returns
 2024-08-15 03:30:23 -07:00
Ryan Houdek df0ecad15b Merge pull request #3933 from bylaws/arm64-suspend 
Support cooperative suspend on ARM64EC
 2024-08-15 01:22:28 -07:00
Alyssa Rosenzweig 2dc92c122e BranchOps: micro-optimize ExitFunction 
this should be slightly faster on Firestorm and no worse on recent cortex

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 16:59:34 -04:00
Alyssa Rosenzweig 0db17bd58a OpcodeDispatcher: optimize IRET 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 16:59:34 -04:00
Alyssa Rosenzweig aac16493f1 OpcodeDispatcher: optimize RET 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 16:59:34 -04:00
Ryan Houdek aa5d2ff31c Merge pull request #3951 from alyssarosenzweig/opt/pops 
Add a hack for multiple destinations & make good use of it
 2024-08-14 12:03:00 -07:00
Alyssa Rosenzweig c70e44cf05 OpcodeDispatcher: extract Push helper 
Mirrors the Pop helper we added. This cleans up a bunch

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig ede13e37d9 OpcodeDispatcher: optimize Thunk 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig a7dada457a OpcodeDispatcher: optimize POPF 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 6367554d30 OpcodeDispatcher: optimize LEAVE 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 81969a684e OpcodeDispatcher: optimize pop segment 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig ee339b5960 OpcodeDispatcher: optimize POPA 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 881c940693 OpcodeDispatcher: optimize POP 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 900c62fa7b OpcodeDispatcher: add Pop helpers 
hide away the allocate dance

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 200c6c054f IR: introduce POP operation 
rmw on a source, kind of terrible.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig bc0927b7b1 JIT: optimize moves for cmpxchg 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 231c28395c RegisterAllocationPass: clean up after pair removal 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 64a45c0d29 IR: remove pairs 
They're now unused. And won't be missed.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig cab02be637 IR: remove unused pair create/extract 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 74f341bc0e IR: remove pair from cpuid 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig feaa1af1a8 IR: remove pair from XGetBV 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig d59d040b4e IR: add design doc breadcrumb 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig a9c26cbf71 IR: add coalescing heuristics for pair replacements 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig f4b5c4e69a OpcodeDispatcher: allow upper garbage for cmpxchg 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig b8cac9f7d5 JIT: avoid some moves with caspal 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig 13974df204 IR: drop CASPair pair result 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig fa6fe9bf06 IR: drop cmppairz pairs 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig 746be0824e IR: drop CASPair source pairs 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig 93120cabbb IR: drop pair from memcpy 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig 04ae05f4ce IR: add hack for multiple destinations 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig 83773dddc7 IR: fix size for cmppairz 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Billy Laws 890e5e1f0f FEXCore: Support disabling host cacheline clean/clear operations 2024-08-13 13:25:34 +00:00
Alyssa Rosenzweig 40812efaae OpcodeDispatcher: better handle SIB indexing 
if we have shift and a constant, we can save an instruction

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Alyssa Rosenzweig 3429321d59 OpcodeDispatcher: allow upper garbage for MOVGPR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Alyssa Rosenzweig 6cddd6cbe7 OpcodeDispatcher: allow upper garbage for a2/a3 
stores mask.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Alyssa Rosenzweig 23d07d7d0c OpcodeDispatcher: fix folding negative offsets for 32-bit 
I don't know what I was thinking when I wrote that code. Drop the silly logic
and let ConstProp inline the immediates. This fixes a lot of silly code
generated for 32-bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Alyssa Rosenzweig 91f4c54768 OpcodeDispatcher: optimize RDRAND on flagm 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 15:21:08 -04:00
Alyssa Rosenzweig d9c779289c OpcodeDispatcher: simplify RDRAND 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 15:18:00 -04:00
Alyssa Rosenzweig 5631ff4fd5 OpcodeDispatcher: optimize variable shifts 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig 34301319bf OpcodeDispatcher: optimize IncrementByCarry 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig 8eac3198b6 OpcodeDispatcher: use carry increment for ADC 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig 832edd4da3 OpcodeDispatcher: use carry increment for SBC 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig 5823e74bcd OpcodeDispatcher: use increment carry for atomics 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig a4545f493e OpcodeDispatcher: add IncrementByCarry helper 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig 3b8cd44ca4 IR: add NZCVSelectIncrement 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig f138d7d9b8 OpcodeDispatcher: optimize JA/JNA 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig 3bb9d44bf5 OpcodeDispatcher: optimize SetCFDirect 
generally same # of instructions, but potentially fewer cycles:

old:
        "rmif x4, #63, #nzCv",
        "cfinv"

new:
        "xor x20, x4, #1",
        "rmif x20, #63, #nzCv"

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig 06e6a1b19e OpcodeDispatcher: optimize logic ops 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00