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IR: drop cmppairz pairs

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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Alyssa Rosenzweig committed 2024-08-14 09:17:23 -04:00
1 parent 746be0824e
commit fa6fe9bf06
3 files changed
+5 -8
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FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
+2 -4
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@@ -232,10 +232,8 @@ DEF_OP(CmpPairZ) {
mrs(TMP1, ARMEmitter::SystemRegister::NZCV);
// Compare, setting Z and clobbering NzCV
const auto Src1 = GetRegPair(Op->Src1.ID());
const auto Src2 = GetRegPair(Op->Src2.ID());
cmp(EmitSize, Src1.first, Src2.first);
ccmp(EmitSize, Src1.second, Src2.second, ARMEmitter::StatusFlags::None, ARMEmitter::Condition::CC_EQ);
cmp(EmitSize, GetReg(Op->Src1Lo.ID()), GetReg(Op->Src2Lo.ID()));
ccmp(EmitSize, GetReg(Op->Src1Hi.ID()), GetReg(Op->Src2Hi.ID()), ARMEmitter::StatusFlags::None, ARMEmitter::Condition::CC_EQ);
// Restore NzCV
if (CTX->HostFeatures.SupportsFlagM) {
FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+2 -3
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@@ -3979,7 +3979,6 @@ void OpDispatchBuilder::CMPXCHGPairOp(OpcodeArgs) {
Ref Expected_Lower = LoadGPRRegister(X86State::REG_RAX, Size);
Ref Expected_Upper = LoadGPRRegister(X86State::REG_RDX, Size);
Ref Expected = _CreateElementPair(IR::SizeToOpSize(Size * 2), Expected_Lower, Expected_Upper);
Ref Desired_Lower = LoadGPRRegister(X86State::REG_RBX, Size);
Ref Desired_Upper = LoadGPRRegister(X86State::REG_RCX, Size);
@@ -3994,9 +3993,10 @@ void OpDispatchBuilder::CMPXCHGPairOp(OpcodeArgs) {
// Third operand must be a calculated guest memory address
Ref CASResult = _CASPair(IR::SizeToOpSize(Size * 2), Expected_Lower, Expected_Upper, Desired_Lower, Desired_Upper, Src1);
auto [Result_Lower, Result_Upper] = ExtractPair(IR::SizeToOpSize(Size), CASResult);
HandleNZCV_RMW();
_CmpPairZ(IR::SizeToOpSize(Size), CASResult, Expected);
_CmpPairZ(IR::SizeToOpSize(Size), Result_Lower, Result_Upper, Expected_Lower, Expected_Upper);
CalculateDeferredFlags();
auto UpdateIfNotZF = [this](auto Reg, auto Value) {
@@ -4005,7 +4005,6 @@ void OpDispatchBuilder::CMPXCHGPairOp(OpcodeArgs) {
StoreGPRRegister(Reg, NZCVSelect(OpSize::i64Bit, {COND_NEQ}, Value, LoadGPRRegister(Reg)));
};
auto [Result_Lower, Result_Upper] = ExtractPair(IR::SizeToOpSize(Size), CASResult);
UpdateIfNotZF(X86State::REG_RAX, Result_Lower);
UpdateIfNotZF(X86State::REG_RDX, Result_Upper);
}
FEXCore/Source/Interface/IR/IR.json
+1 -1
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@@ -1182,7 +1182,7 @@
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
]
},
"CmpPairZ OpSize:#Size, GPRPair:$Src1, GPRPair:$Src2": {
"CmpPairZ OpSize:#Size, GPR:$Src1Lo, GPR:$Src1Hi, GPR:$Src2Lo, GPR:$Src2Hi": {
"Desc": ["Compares register pairs and sets Z accordingly, preserving N/Z/V.",
"This accelerates cmpxchg."],
"HasSideEffects": true,