Alyssa Rosenzweig 40812efaae OpcodeDispatcher: better handle SIB indexing ...

if we have shift and a constant, we can save an instruction

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2024-08-13 08:41:16 -04:00

..

Config

HostFeatures: Check for SVE bit permute extension

2024-07-10 21:45:07 -07:00

Context

FEXCore: Pass HostFeatures in to CreateNewContext directly

2024-08-08 21:02:41 -07:00

Core

OpcodeDispatcher: better handle SIB indexing

2024-08-13 08:41:16 -04:00

GDBJIT

Whole-tree reformat

2024-04-12 16:26:02 +02:00

HLE/Thunks

VDSO: Stop using a vector for a static

2024-07-11 23:53:57 -07:00

IR

OpcodeDispatcher: simplify RDRAND

2024-08-10 15:18:00 -04:00