Alyssa Rosenzweig 3bb9d44bf5 OpcodeDispatcher: optimize SetCFDirect ...

generally same # of instructions, but potentially fewer cycles:

old:
        "rmif x4, #63, #nzCv",
        "cfinv"

new:
        "xor x20, x4, #1",
        "rmif x20, #63, #nzCv"

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2024-08-10 13:06:42 -04:00

..

Config

HostFeatures: Check for SVE bit permute extension

2024-07-10 21:45:07 -07:00

Context

FEXCore: Pass HostFeatures in to CreateNewContext directly

2024-08-08 21:02:41 -07:00

Core

OpcodeDispatcher: optimize SetCFDirect

2024-08-10 13:06:42 -04:00

GDBJIT

Whole-tree reformat

2024-04-12 16:26:02 +02:00

HLE/Thunks

VDSO: Stop using a vector for a static

2024-07-11 23:53:57 -07:00

IR

CodeEmitter: Removes vestigial vixl usage

2024-08-03 21:04:56 -07:00