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81 Commits
Author SHA1 Message Date
Tony Wasserka 51e64c69f3 LogManager: Unconditionally evaluate assertion conditions 
A prevalent pattern in the FEX codebase is to compute some data and store it
in a maybe_unused variable that's only ever passed to LOGMAN_THROW_A_FMT.
Besides few exceptions, we never compute expensive data in the macro
arguments themselves, so we can remove a lot of code noise by unconditionally
evaluating the condition even in assertion-disabled builds.
 2025-08-25 10:36:01 +02:00
Ryan Houdek 0457bdc7ce Merge pull request #4751 from lioncash/perm 
ASIMDOps: Remove unused permute overloads
 2025-08-01 12:45:50 -07:00
Lioncache b460cbc91a ASIMDOps: Remove unused permute overloads 
These aren't used at all and don't really provide anything that the existing
non-templated overloads can't.
 2025-08-01 11:51:55 -04:00
Lioncache f7939078c2 ASIMDOps: Remove unnecessary ins() overload 
There's no difference between this and the non-templated version, in fact,
this variant wasn't even used at all, so we can just remove it.
 2025-08-01 11:24:44 -04:00
Lioncache e103af3b93 ASIMDOps: Move base opcode into ASIMDScalarCopy() 
Now we have no more duplicated opcodes in ASIMDOps.
 2025-08-01 11:13:58 -04:00
Lioncache 45bec06d5b ASIMDOps: Move base opcode into ASIMDFloatConvBetweenInt() 
Deduplicates the second last remaining instruction category in ASIMDOps
 2025-08-01 10:49:52 -04:00
Lioncache e624e87b29 ASIMDOps: Move base opcode into ASIMDExtract() 
Minor deduplication of the base opcode.
 2025-07-31 10:44:06 -04:00
Lioncache 6ff8d0953f ASIMDOps: Move base opcode into ASIMDPermute() 
Gets rid of the need to respecify the base opcode in every instruction implementation
 2025-07-31 10:43:17 -04:00
Lioncache 9f2fcdf0b3 ASIMDOps: Move base opcode into Crypto2RegSHA()/Crypto3RegSHA() 
Removes the need to specify the base opcode multiple times.
 2025-07-31 10:23:38 -04:00
Lioncache cecb9bfe32 ASIMDOps: Move base opcode into CryptoAES() 
Minor deduplication.
 2025-07-31 10:15:15 -04:00
Lioncache 6a989d844a ASIMDOps: Move base opcode into ASIMDTable() 
Gets rid of duplication of the opcode in all instruction implementations.
 2025-07-31 10:10:35 -04:00
Lioncache 017952e89e ASIMDOps: Constrain more instructions with IsQOrDRegister 
We had quite a few instructions that we weren't constraining with this,
now the instruction itself will show up in the failure output more immediately
instead of failing on the internal implementation function if anything is
incorrectly passed through.
 2025-07-30 19:03:33 -04:00
Lioncache b1ef8bbc5a ASIMDOps: Move base opcode into ASIMDModifiedImm() 2025-07-30 18:03:43 -04:00
Lioncache f19a6343dd ASIMDOps: Move base opcode into ASIMDShiftByImm() 
Avoids needing to duplicate the opcode all over the place
 2025-07-30 18:03:36 -04:00
Lioncache ed7bc28c21 ASIMDOps: Simplify size conditionals in several 2-reg misc instructions 
In many of these, the long ternaries are equivalent to a subtraction by 1,
which is much more efficient
 2025-07-30 16:31:33 -04:00
Lioncache 05dcb160bd ASIMDOps: Move base opcode into ASIMD2RegMisc() 
Avoids the need to specify the opcode repeatedly, making implementations less noisy.
 2025-07-30 16:25:24 -04:00
Lioncache a3e02cbafa ASIMDOps: Simplify conditionals in saddlv/uaddlv 
Really all these size conversions are emulating is a subtraction by 1.
Also we can drop in an assert that was missed in uaddlv
 2025-07-30 11:21:06 -04:00
Lioncache 4cca2f6915 ASIMDOps: Move base opcode into ASIMDAcrossLanes() 2025-07-30 11:07:08 -04:00
Lioncache 64ca48c4b1 ASIMDOps: Move base opcode into ASIMD3Different() 
Deduplicates the open-coded base opcode in the instruction implementations.
 2025-07-30 10:59:11 -04:00
Lioncache 74a897271f ASIMDOps: Move base opcode into ASIMD3Same() 
Moves the base opcode into the actual implementation, so that we
aren't open-coding it into every relevant instruction function.
 2025-07-30 10:40:17 -04:00
Lioncache ab6fc279ce ASIMDOps/SVEOps: Use IsStandardFloatSize() even more 
Forgot in #4697 to take into account that there are still parts of the
emitter that qualify with its own namespace.

This also removes those where applicable to be more in line with the rest
of the cases.
 2025-07-22 08:25:35 -04:00
Lioncache 2a8efa9891 SVEOps: Make use of IsStandardFloatSize() more 
Initially introduced in #4687 as a utility for ASIMD ops, this can be used
elsewhere as well to reduce the verbosity of some other assertions.
 2025-07-21 13:51:37 -04:00
Lioncache a615f8970a ASIMDOps: Constrain 3-reg same float arguments with IsQOrDRegister 
These are only intended to be used with QRegisters or DRegisters, so we can constrain these
so that the proper types are enforced at compile-time.
 2025-07-16 17:46:28 -04:00
Lioncache 708ea9d50a ASIMDOps: Merge half-float 3-reg same with single/double variants 2025-07-16 17:36:24 -04:00
Lioncache 82ffb379c4 ASIMDOps: Merge half-float 2-reg misc with single/double variants 
Unifies the interface, so that there's no need for a stark difference.

Previously, calling the single/double variant didn't require explicit template
arguments, but the half-float version did, which is inconsistent.

Technically it also made the interface more cumbersome to use in the event the
element size isn't able to be determined as a constant ahead of time.
 2025-07-16 10:16:49 -04:00
Lioncache 05d45ccb7f Emitter: Add helper for sanitizing floating point element sizes 
Will be used in a following change to reduce the amount of duplication
made in some floating point instructions.
 2025-07-16 09:19:45 -04:00
Lioncache d8da14d550 VixlUtils: Fix null pointer dereference vector in IsImmLogical() 
Technically we can end up doing null pointer dereferencing here since checks were being
chained with || instead of &&. So we can just separate the checks out.
 2025-07-10 12:09:20 -04:00
Ryan Houdek 646a5a7f9e CodeEmitter/ASIMD: Removes redundant ternary selection 
Redundant and unnecessary.

CID 482017
 2025-06-19 16:31:08 -07:00
Tony Wasserka 048ae597d2 CodeEmitter: Fix incorrect macro parameter passing 
Macros aren't aware of C++ templates, so the comma is considered a macro
argument separator unless the argument is wrapped in parentheses.
 2025-05-24 09:35:11 +02:00
Ryan Houdek 6beb4b0f8b Merge pull request #4533 from Sonicadvance1/align_tail_in_the_pale_moonlight 
JIT: Align JITCodeTail to native alignment
 2025-04-24 16:18:45 -07:00
Ryan Houdek e31127e39e CodeEmitter: Fix clang-format 2025-04-24 08:41:23 -07:00
Ryan Houdek 735f537846 JIT: Align JITCodeTail to native alignment 
Removes UB
 2025-04-24 08:40:43 -07:00
Ryan Houdek e7fce2de40 CodeEmitter: Adds udf support 2025-04-23 12:14:44 -07:00
Lioncache 63a2d1e1db CodeEmitter/ASIMDOps: Move three emitter helpers to private section 
These don't need to be public.
 2025-04-20 15:55:53 -04:00
Lioncache 644263a764 CodeEmitter/ASIMDOps: Constrain Q and D register requirements with concept 
Pulls these out into a single concept instead of having the same lengthy
requirements clause.
 2025-04-20 15:55:49 -04:00
Lioncache 4e6f183f77 CodeEmitter/LoadstoreOps: Add Load/store register (PAC) group 
Eh, what the heck. Gets rid of the last TODO marker in the base load-stores.
 2025-04-19 13:00:00 -04:00
Lioncache d71aca9e9b CodeEmitter/LoadStoreOps: Add Memory Copy and Memory Set category 
Adds all of the memory facilities in FEAT_MOPS to the emitter.
 2025-04-18 10:53:38 -04:00
Lioncache d7a08fc7d4 CodeEmitter/ASIMDOps: Support RADDHN{2}/RSUBHN{2} 
These are trivial enough to just drop right in.
 2025-04-17 20:13:30 -04:00
LC 572d6e0395 Merge pull request #4509 from Sonicadvance1/in_the_twilight_of_the_pale_blue_moon 
A couple of barrier and timing fixes.
 2025-04-17 17:30:03 -04:00
Lioncache bafcc8762b CodeEmitter/ScalarOps: Handle ASIMD scalar x indexed element group 2025-04-17 14:47:38 -04:00
Lioncache ec6ff7899d CodeEmitter/ScalarOps: Remove implemented TODO 
These scalar ops are already implemented and this was accidentally left in.
 2025-04-17 08:14:10 -04:00
Lioncache 6330b398a5 CodeEmitter/ScalarOps: Handle ASIMD scalar three same extra group 
These are trivial enough to drop in.
 2025-04-17 08:09:42 -04:00
Ryan Houdek da1868288d CodeEmitter: Fixes misaligned function 2025-04-15 15:47:31 -07:00
Ryan Houdek 753c5e72be CodeEmitter: Implement support for CNTVCTSS_EL0 2025-04-15 15:37:02 -07:00
Lioncache 222fcfd70e CodeEmitter/ASIMDOps: Add crypto two-register SHA512 category 2025-04-15 11:48:30 -04:00
Lioncache 95c8a70ce6 CodeEmitter/ASIMDOps: Add crypto four-reg category 2025-04-15 11:41:07 -04:00
Lioncache 0f6bec4d5e CodeEmitter/ASIMDOps: Add crypto three-reg SHA512 category 2025-04-15 11:31:00 -04:00
Lioncache 5fb0522c78 CodeEmitter/ASIMDOps: Add crypto three-reg imm2 category 2025-04-15 11:15:21 -04:00
Ryan Houdek aa0fc9071e CodeEmitter: Fixes typo in sha256h2 
This was accidentally encoding as sha256h.
 2025-04-02 12:38:47 -07:00
Lioncache 5708846a07 CodeEmitter/Registers: Replace use of deprecated std::is_trivial_v template 
std::is_trivial/std::is_trivial_v is deprecated in C++26, so we can just
use a more specific trait and be more explicit about what we want.

Also some of these static_asserts were testing the constraints of the wrong
class, so we can tidy those up as well.
 2025-03-29 00:28:14 -04:00