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https://github.com/FEX-Emu/FEX.git
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ASIMDOps: Merge half-float 3-reg same with single/double variants
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@@ -444,133 +444,6 @@ public:
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ASIMDScalarCopy(Op, 1, imm5, imm4, rd, rn);
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}
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// Advanced SIMD three same (FP16)
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fmaxnm(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(0, 0, 0b000, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fmla(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(0, 0, 0b001, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fadd(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(0, 0, 0b010, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fmulx(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(0, 0, 0b011, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fcmeq(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(0, 0, 0b100, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fmax(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(0, 0, 0b110, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void frecps(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(0, 0, 0b111, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fminnm(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(0, 1, 0b000, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fmls(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(0, 1, 0b001, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fsub(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(0, 1, 0b010, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fmin(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(0, 1, 0b110, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void frsqrts(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(0, 1, 0b111, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fmaxnmp(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(1, 0, 0b000, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void faddp(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(1, 0, 0b010, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fmul(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(1, 0, 0b011, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fcmge(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(1, 0, 0b100, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void facge(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(1, 0, 0b101, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fmaxp(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(1, 0, 0b110, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fdiv(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(1, 0, 0b111, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fminnmp(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(1, 1, 0b000, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fabd(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(1, 1, 0b010, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fcmgt(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(1, 1, 0b100, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void facgt(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(1, 1, 0b101, rm, rn, rd);
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}
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template<ARMEmitter::SubRegSize size, IsQOrDRegister T>
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requires (size == ARMEmitter::SubRegSize::i16Bit)
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void fminp(T rd, T rn, T rm) {
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ASIMDThreeSameFP16(1, 1, 0b110, rm, rn, rd);
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}
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// Advanced SIMD three-register extension
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template<IsQOrDRegister T>
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void sdot(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
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@@ -2241,102 +2114,116 @@ public:
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ASIMD3Same<T>(Op, 0, size, 0b10111, rd, rn, rm);
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}
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template<typename T>
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void fmaxnm(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
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if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
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LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
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void fmaxnm(SubRegSize size, T rd, T rn, T rm) {
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if constexpr (std::is_same_v<DRegister, T>) {
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LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
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}
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LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
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"subregsize supported");
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LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
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constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
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const ARMEmitter::SubRegSize ConvertedSize =
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size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit;
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if (size == SubRegSize::i16Bit) {
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ASIMDThreeSameFP16(0, 0, 0b000, rm, rn, rd);
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} else {
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constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
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const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
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ASIMD3Same<T>(Op, 0, ConvertedSize, 0b11000, rd, rn, rm);
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ASIMD3Same<T>(Op, 0, ConvertedSize, 0b11000, rd, rn, rm);
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}
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}
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template<typename T>
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void fmla(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
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if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
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LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
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void fmla(SubRegSize size, T rd, T rn, T rm) {
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if constexpr (std::is_same_v<DRegister, T>) {
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LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
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}
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LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
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"subregsize supported");
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LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
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constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
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const ARMEmitter::SubRegSize ConvertedSize =
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size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit;
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if (size == SubRegSize::i16Bit) {
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ASIMDThreeSameFP16(0, 0, 0b001, rm, rn, rd);
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} else {
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constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
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const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
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ASIMD3Same<T>(Op, 0, ConvertedSize, 0b11001, rd, rn, rm);
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ASIMD3Same<T>(Op, 0, ConvertedSize, 0b11001, rd, rn, rm);
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}
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}
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template<typename T>
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void fadd(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
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if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
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LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
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void fadd(SubRegSize size, T rd, T rn, T rm) {
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if constexpr (std::is_same_v<DRegister, T>) {
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LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
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}
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LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
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"subregsize supported");
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LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
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constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
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const ARMEmitter::SubRegSize ConvertedSize =
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size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit;
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if (size == SubRegSize::i16Bit) {
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ASIMDThreeSameFP16(0, 0, 0b010, rm, rn, rd);
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} else {
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constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
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const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
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ASIMD3Same<T>(Op, 0, ConvertedSize, 0b11010, rd, rn, rm);
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ASIMD3Same<T>(Op, 0, ConvertedSize, 0b11010, rd, rn, rm);
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}
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}
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template<typename T>
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void fmulx(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
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if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
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LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
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void fmulx(SubRegSize size, T rd, T rn, T rm) {
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if constexpr (std::is_same_v<DRegister, T>) {
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LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
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}
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LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
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"subregsize supported");
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LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
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constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
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const ARMEmitter::SubRegSize ConvertedSize =
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size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit;
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if (size == SubRegSize::i16Bit) {
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ASIMDThreeSameFP16(0, 0, 0b011, rm, rn, rd);
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} else {
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constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
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const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
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ASIMD3Same<T>(Op, 0, ConvertedSize, 0b11011, rd, rn, rm);
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ASIMD3Same<T>(Op, 0, ConvertedSize, 0b11011, rd, rn, rm);
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}
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}
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template<typename T>
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void fcmeq(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
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if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
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LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
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void fcmeq(SubRegSize size, T rd, T rn, T rm) {
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if constexpr (std::is_same_v<DRegister, T>) {
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LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
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}
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LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
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"subregsize supported");
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LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
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constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
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const ARMEmitter::SubRegSize ConvertedSize =
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size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit;
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if (size == SubRegSize::i16Bit) {
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ASIMDThreeSameFP16(0, 0, 0b100, rm, rn, rd);
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} else {
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constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
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const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
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ASIMD3Same<T>(Op, 0, ConvertedSize, 0b11100, rd, rn, rm);
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ASIMD3Same<T>(Op, 0, ConvertedSize, 0b11100, rd, rn, rm);
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}
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}
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template<typename T>
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void fmax(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
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if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
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LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
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void fmax(SubRegSize size, T rd, T rn, T rm) {
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if constexpr (std::is_same_v<DRegister, T>) {
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LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
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}
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LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
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"subregsize supported");
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LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
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constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
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const ARMEmitter::SubRegSize ConvertedSize =
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size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit;
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if (size == SubRegSize::i16Bit) {
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ASIMDThreeSameFP16(0, 0, 0b110, rm, rn, rd);
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} else {
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constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
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const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
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ASIMD3Same<T>(Op, 0, ConvertedSize, 0b11110, rd, rn, rm);
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ASIMD3Same<T>(Op, 0, ConvertedSize, 0b11110, rd, rn, rm);
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}
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}
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template<typename T>
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void frecps(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
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if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
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LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
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void frecps(SubRegSize size, T rd, T rn, T rm) {
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if constexpr (std::is_same_v<DRegister, T>) {
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LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
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}
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LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
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"subregsize supported");
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LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
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constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
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const ARMEmitter::SubRegSize ConvertedSize =
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size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit;
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if (size == SubRegSize::i16Bit) {
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ASIMDThreeSameFP16(0, 0, 0b111, rm, rn, rd);
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} else {
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constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
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const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
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ASIMD3Same<T>(Op, 0, ConvertedSize, 0b11111, rd, rn, rm);
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ASIMD3Same<T>(Op, 0, ConvertedSize, 0b11111, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void and_(T rd, T rn, T rm) {
|
||||
@@ -2359,59 +2246,74 @@ public:
|
||||
ASIMD3Same<T>(Op, 0, ARMEmitter::SubRegSize::i16Bit, 0b00011, rd, rn, rm);
|
||||
}
|
||||
template<typename T>
|
||||
void fminnm(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void fminnm(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 0, size, 0b11000, rd, rn, rm);
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(0, 1, 0b000, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 0, size, 0b11000, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void fmls(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void fmls(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 0, size, 0b11001, rd, rn, rm);
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(0, 1, 0b001, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 0, size, 0b11001, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void fsub(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void fsub(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 0, size, 0b11010, rd, rn, rm);
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(0, 1, 0b010, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 0, size, 0b11010, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void fmin(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void fmin(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 0, size, 0b11110, rd, rn, rm);
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(0, 1, 0b110, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 0, size, 0b11110, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void frsqrts(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void frsqrts(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 0, size, 0b11111, rd, rn, rm);
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(0, 1, 0b111, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 0, size, 0b11111, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void orr(T rd, T rn, T rm) {
|
||||
@@ -2582,102 +2484,116 @@ public:
|
||||
ASIMD3Same<T>(Op, 1, size, 0b10110, rd, rn, rm);
|
||||
}
|
||||
template<typename T>
|
||||
void fmaxnmp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void fmaxnmp(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
const ARMEmitter::SubRegSize ConvertedSize =
|
||||
size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit;
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(1, 0, 0b000, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
|
||||
|
||||
ASIMD3Same<T>(Op, 1, ConvertedSize, 0b11000, rd, rn, rm);
|
||||
ASIMD3Same<T>(Op, 1, ConvertedSize, 0b11000, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void faddp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void faddp(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
const ARMEmitter::SubRegSize ConvertedSize =
|
||||
size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit;
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(1, 0, 0b010, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
|
||||
|
||||
ASIMD3Same<T>(Op, 1, ConvertedSize, 0b11010, rd, rn, rm);
|
||||
ASIMD3Same<T>(Op, 1, ConvertedSize, 0b11010, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void fmul(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void fmul(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
const ARMEmitter::SubRegSize ConvertedSize =
|
||||
size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit;
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(1, 0, 0b011, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
|
||||
|
||||
ASIMD3Same<T>(Op, 1, ConvertedSize, 0b11011, rd, rn, rm);
|
||||
ASIMD3Same<T>(Op, 1, ConvertedSize, 0b11011, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void fcmge(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void fcmge(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
const ARMEmitter::SubRegSize ConvertedSize =
|
||||
size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit;
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(1, 0, 0b100, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
|
||||
|
||||
ASIMD3Same<T>(Op, 1, ConvertedSize, 0b11100, rd, rn, rm);
|
||||
ASIMD3Same<T>(Op, 1, ConvertedSize, 0b11100, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void facge(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void facge(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
const ARMEmitter::SubRegSize ConvertedSize =
|
||||
size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit;
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(1, 0, 0b101, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
|
||||
|
||||
ASIMD3Same<T>(Op, 1, ConvertedSize, 0b11101, rd, rn, rm);
|
||||
ASIMD3Same<T>(Op, 1, ConvertedSize, 0b11101, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void fmaxp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void fmaxp(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
const ARMEmitter::SubRegSize ConvertedSize =
|
||||
size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit;
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(1, 0, 0b110, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
|
||||
|
||||
ASIMD3Same<T>(Op, 1, ConvertedSize, 0b11110, rd, rn, rm);
|
||||
ASIMD3Same<T>(Op, 1, ConvertedSize, 0b11110, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void fdiv(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void fdiv(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
const ARMEmitter::SubRegSize ConvertedSize =
|
||||
size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit;
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(1, 0, 0b111, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
|
||||
|
||||
ASIMD3Same<T>(Op, 1, ConvertedSize, 0b11111, rd, rn, rm);
|
||||
ASIMD3Same<T>(Op, 1, ConvertedSize, 0b11111, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void eor(T rd, T rn, T rm) {
|
||||
@@ -2690,59 +2606,74 @@ public:
|
||||
ASIMD3Same<T>(Op, 1, ARMEmitter::SubRegSize::i16Bit, 0b00011, rd, rn, rm);
|
||||
}
|
||||
template<typename T>
|
||||
void fminnmp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void fminnmp(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 1, size, 0b11000, rd, rn, rm);
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(1, 1, 0b000, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 1, size, 0b11000, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void fabd(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void fabd(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 1, size, 0b11010, rd, rn, rm);
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(1, 1, 0b010, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 1, size, 0b11010, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void fcmgt(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void fcmgt(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 1, size, 0b11100, rd, rn, rm);
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(1, 1, 0b100, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 1, size, 0b11100, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void facgt(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void facgt(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 1, size, 0b11101, rd, rn, rm);
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(1, 1, 0b101, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 1, size, 0b11101, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void fminp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
void fminp(SubRegSize size, T rd, T rn, T rm) {
|
||||
if constexpr (std::is_same_v<DRegister, T>) {
|
||||
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
|
||||
}
|
||||
LOGMAN_THROW_A_FMT(size == ARMEmitter::SubRegSize::i64Bit || size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit "
|
||||
"subregsize supported");
|
||||
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
|
||||
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 1, size, 0b11110, rd, rn, rm);
|
||||
if (size == SubRegSize::i16Bit) {
|
||||
ASIMDThreeSameFP16(1, 1, 0b110, rm, rn, rd);
|
||||
} else {
|
||||
constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10;
|
||||
ASIMD3Same<T>(Op, 1, size, 0b11110, rd, rn, rm);
|
||||
}
|
||||
}
|
||||
template<typename T>
|
||||
void bit(T rd, T rn, T rm) {
|
||||
|
||||
Reference in new issue
Block a user