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CodeEmitter/ASIMDOps: Constrain Q and D register requirements with concept

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Pulls these out into a single concept instead of having the same lengthy
requirements clause.
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Lioncache committed 2025-04-20 15:55:49 -04:00
1 parent f912295690
commit 644263a764
3 files changed
+224 -334
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CodeEmitter/CodeEmitter/ASIMDOps.inl
+216 -326
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File diff suppressed because it is too large. Load diff
CodeEmitter/CodeEmitter/Emitter.h
+4
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@@ -573,6 +573,10 @@ enum class Rotation : uint32_t {
template<typename T>
concept IsXOrWRegister = std::is_same_v<T, XRegister> || std::is_same_v<T, WRegister>;
// Concept for contraining some instructions to accept only a QRegister or DRegister.
template<typename T>
concept IsQOrDRegister = std::is_same_v<T, QRegister> || std::is_same_v<T, DRegister>;
// Whether or not a given set of vector registers are sequential
// in increasing order as far as the register file is concerned (modulo its size)
//
CodeEmitter/CodeEmitter/LoadstoreOps.inl
+4 -8
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@@ -416,8 +416,7 @@ public:
0;
ASIMDSTLD<size, true, 1>(Op, Opcode, rt, Index, rn, Reg::r0);
}
template<SubRegSize size, typename T>
requires (std::is_same_v<QRegister, T> || std::is_same_v<DRegister, T>)
template<SubRegSize size, IsQOrDRegister T>
void ld1r(T rt, Register rn) {
constexpr uint32_t Op = 0b0000'1101'000 << 21;
constexpr uint32_t Opcode = 0b110;
@@ -435,8 +434,7 @@ public:
0;
ASIMDSTLD<size, true, 2>(Op, Opcode, rt, Index, rn, Reg::r0);
}
template<SubRegSize size, typename T>
requires (std::is_same_v<QRegister, T> || std::is_same_v<DRegister, T>)
template<SubRegSize size, IsQOrDRegister T>
void ld2r(T rt, T rt2, Register rn) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rt, rt2), "rt and rt2 must be sequential");
constexpr uint32_t Op = 0b0000'1101'000 << 21;
@@ -455,8 +453,7 @@ public:
0;
ASIMDSTLD<size, true, 3>(Op, Opcode, rt, Index, rn, Reg::r0);
}
template<SubRegSize size, typename T>
requires (std::is_same_v<QRegister, T> || std::is_same_v<DRegister, T>)
template<SubRegSize size, IsQOrDRegister T>
void ld3r(T rt, T rt2, T rt3, Register rn) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rt, rt2, rt3), "rt, rt2, and rt3 must be sequential");
constexpr uint32_t Op = 0b0000'1101'000 << 21;
@@ -475,8 +472,7 @@ public:
0;
ASIMDSTLD<size, true, 4>(Op, Opcode, rt, Index, rn, Reg::r0);
}
template<SubRegSize size, typename T>
requires (std::is_same_v<QRegister, T> || std::is_same_v<DRegister, T>)
template<SubRegSize size, IsQOrDRegister T>
void ld4r(T rt, T rt2, T rt3, T rt4, Register rn) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rt, rt2, rt3, rt4), "rt, rt2, rt3, and rt4 must be sequential");
constexpr uint32_t Op = 0b0000'1101'000 << 21;