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CodeEmitter/ASIMDOps: Add crypto four-reg category

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Lioncache committed 2025-04-15 11:41:07 -04:00
1 parent 0f6bec4d5e
commit 95c8a70ce6
2 files changed
+23 -2
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CodeEmitter/CodeEmitter/ASIMDOps.inl
+20 -1
View File
@@ -4534,7 +4534,16 @@ public:
}
// Cryptographic four-register
// TODO
void eor3(VRegister rd, VRegister rn, VRegister rm, VRegister ra) {
Crypto4Register(0b00, rm, ra, rn, rd);
}
void bcax(VRegister rd, VRegister rn, VRegister rm, VRegister ra) {
Crypto4Register(0b01, rm, ra, rn, rd);
}
void sm3ss1(VRegister rd, VRegister rn, VRegister rm, VRegister ra) {
Crypto4Register(0b10, rm, ra, rn, rd);
}
// Cryptographic two-register SHA 512
// TODO
// Conversion between floating-point and fixed-point
@@ -5012,6 +5021,16 @@ private:
dc32(Instr);
}
void Crypto4Register(uint32_t opcode, VRegister rm, VRegister ra, VRegister rn, VRegister rd) {
uint32_t Instr = 0b1100'1110'0000'0000'0000'0000'0000'0000;
Instr |= opcode << 21;
Instr |= rm.Idx() << 16;
Instr |= ra.Idx() << 10;
Instr |= rn.Idx() << 5;
Instr |= rd.Idx();
dc32(Instr);
}
// Conversion between floating-point and fixed-point
template<typename T, typename T2>
void ScalarConvertBetweenFPAndFixed(uint32_t S, uint32_t rmode, uint32_t opcode, uint32_t scale, ARMEmitter::Size GPRSize,
FEXCore/unittests/Emitter/ASIMD_Tests.cpp
+3 -1
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@@ -3137,7 +3137,9 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: ASIMD: Cryptographic three-register
TEST_SINGLE(sm4ekey(VReg::v30, VReg::v29, VReg::v15), "sm4ekey v30.4s, v29.4s, v15.4s");
}
TEST_CASE_METHOD(TestDisassembler, "Emitter: ASIMD: Cryptographic four-register") {
// TODO: Implement in emitter.
TEST_SINGLE(eor3(VReg::v30, VReg::v29, VReg::v15, VReg::v7), "eor3 v30.16b, v29.16b, v15.16b, v7.16b");
TEST_SINGLE(bcax(VReg::v30, VReg::v29, VReg::v15, VReg::v7), "bcax v30.16b, v29.16b, v15.16b, v7.16b");
TEST_SINGLE(sm3ss1(VReg::v30, VReg::v29, VReg::v15, VReg::v7), "sm3ss1 v30.4s, v29.4s, v15.4s, v7.4s");
}
TEST_CASE_METHOD(TestDisassembler, "Emitter: ASIMD: Cryptographic two-register SHA 512") {
// TODO: Implement in emitter.