LC
210514f74b
Vector: LoadSourceGPR -> LoadSourceFPR for MASKMOVOp
2026-07-10 07:24:39 -04:00
Ryan Houdek
5f2d19c7aa
Merge pull request #5685 from lioncash/faddv
2026-07-10 03:33:43 -07:00
Ryan Houdek
95e7c866cf
Merge pull request #5682 from lioncash/pid
2026-07-10 03:20:23 -07:00
Ryan Houdek
2effdb04bd
Merge pull request #5684 from lioncash/midr
2026-07-10 03:18:25 -07:00
LC
ede09a03db
VectorOps: Fix 256-bit FADDV path
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Avoids falling down to the SVE-128 path.
2026-07-10 05:50:22 -04:00
LC
849d60253c
CPUID: Fix MIDR walking in SetupHostHybridFlag()
2026-07-10 05:46:16 -04:00
LC
b5660c8a92
MiscOps: Avoid stack misalignment in ProcessorID
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This needs to be an add.
2026-07-10 05:41:54 -04:00
LC
54263bb5a7
ALUOps: Fix 32-bit MulH case
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These need to be 64-bit multiply and ubfx. Thankfully this case wasn't
actually hit in practice.
2026-07-10 05:39:14 -04:00
LC
caa030714b
IR: Remove unused VUShraI
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Given that this is currently unused and that we don't have the signed
equivalent implemented, we can just remove this for now.
2026-07-10 04:15:52 -04:00
LC
6488dcbb01
ALUOps: Remove unused macros
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These are now unused.
2026-07-10 03:30:03 -04:00
Ryan Houdek
4a091df8cc
Merge pull request #5672 from neobrain/feature_woa_code_cache_bitness
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CodeCache/WoA: Support mixed WoW64/ARM64EC processing
2026-07-09 14:55:21 -07:00
LC
1b1e46ff6c
VectorOps: Join identical branches in VFMLS/VFNMLS
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Same thing, just a little less redundant.
2026-07-09 16:33:26 -04:00
Ryan Houdek
3370d9af15
Merge pull request #5670 from simon902/MOVDoverride
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Fix movd when prefixed with 0x66
2026-07-09 13:02:08 -07:00
Ryan Houdek
9306de79ad
Merge pull request #5667 from simon902/CVTTSS2SIOverride
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Fix cvttss2si when prefixed with 0x66
2026-07-09 12:52:00 -07:00
LC
9b7c9f0fb6
Vector: Trim one instruction off insertq
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We can fold a bitwise not and and pair into a bic
2026-07-09 14:58:04 -04:00
LC
710b85be70
IR: Remove need to specify element size for vector bitwise ops
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Element size doesn't really mean anything here, considering all bits are
acted upon independently of segmentation.
Makes using these ops a little bit less noisy.
2026-07-09 13:26:51 -04:00
Tony Wasserka
54236df6e0
CodeCache: Record main executable bitness in code map
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Code maps already contain the main executable they were recorded from, so
it's convenient to capture the executable's bitness along the way.
2026-07-09 17:12:45 +02:00
Simon Scherer
fe08b96844
OpcodeDispatcher: Fix cvttss2si when prefixed with 0x66
2026-07-09 11:58:18 +02:00
Simon Scherer
4d78901420
OpcodeDispatcher: Fix movd when prefixed with 0x66
2026-07-09 11:46:48 +02:00
Ryan Houdek
9d18ecc5cb
FEXCore: Fixes a crash with multiblock if ProcessorID IR op is encountered
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If during multiblock code discovery a RDTSCP/RDPID instruction was
encountered then ProcessorID has an assert at JIT compile time. Make
sure to early exit with an illegal instruction encoding early instead.
Also make sure to correctly report RDPID support in CPUID, it's
technically a different bit than RDTSCP.
Fixes a crash in Crusader Kings 3's Paradox Launcher installer. Although
the installer seems to fail otherwise for some reason.
2026-07-08 17:41:03 -07:00
Ryan Houdek
5f2455c502
Merge pull request #5665 from lioncash/blendop
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[SVE256] Handle 256-bit blend operations much more efficiently
2026-07-08 16:43:20 -07:00
LC
6bc67609a3
[SVE256] Handle 256-bit blend operations much more efficiently
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We can massage a given selector into a valid predicate register bitmask
and then simply perform a merging move, which eliminates most busywork
around optimizing 256-bit blends.
In the future, once we drop SVE2.1 support in, we can use PMOV to
eliminate the load from memory and related constant management.
2026-07-08 17:35:12 -04:00
Ryan Houdek
168f4b1e6b
Context: Add support for single-step RIP ranges
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Useful when debugging a range.
2026-07-08 12:21:16 -07:00
LC
8a8827c980
Merge pull request #5664 from simon902/CMPXCHGZeroing
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OpcodeDispatcher: Fix 32bit cmpxchg zero extension with eax as first operand
2026-07-08 15:14:12 -04:00
Simon Scherer
3d65c030a8
OpcodeDispatcher: Fix 32bit cmpxchg zero extension with eax as destination operand and remove incorrect comment.
2026-07-08 14:58:32 +02:00
Simon Scherer
655102fc7d
JIT/ALUOps: Fix operand overlapping bug for pdep
2026-07-08 10:09:47 +02:00
Ryan Houdek
b90c9836cb
Merge pull request #5662 from lioncash/alias
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OpcodeDispatcher: Remove asterisk from BMI source args
2026-07-07 11:22:59 -07:00
LC
718f2e01f7
OpcodeDispatcher: Remove asterisk from BMI source args
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Keeps it consistent with the rest of the code and prevents breakages
whenever the Ref alias gets turned into its own value type.
2026-07-07 14:07:38 -04:00
Tony Wasserka
0ac6b3e8f3
CodeCache: Mark executable memory as EC code on ARM64EC
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See bd5b817c3a
2026-07-07 15:55:27 +02:00
Tony Wasserka
852e93aa74
Core: Fix dereference of invalid iterator
2026-07-06 15:07:37 +02:00
LC
7fd9b897c2
[SVE256] Handle 256-bit AES operations
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Currently we split these into two 128-bit operations since VIXL doesn't
have support for the unified SVE operations yet.
Now we fully support VAES on SVE256.
2026-07-03 21:52:59 -04:00
LC
5145324806
[SVE256] EncryptionOps: Handle 256-bit VPCLMULQDQ
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Since vixl now handles this, we can drop this support right in.
2026-07-03 21:22:05 -04:00
LC
d11b19fd2b
[SVE256] Ensure insertion behavior for PCLMUL SSE operations
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Also includes accompanying test to ensure it never breaks.
2026-07-03 20:15:34 -04:00
LC
684c568033
[SVE256] Ensure insertion behavior for SHA SSE operations
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These slipped through, so now we can add tests for them to prevent that
from happening again.
2026-07-03 20:09:50 -04:00
LC
ab4fb7b3ad
[SVE256] Ensure insertion behavior for AES operations on SSE
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These slipped through, so now we can add tests for them to prevent that
from happening again.
2026-07-03 19:35:31 -04:00
Ryan Houdek
6bcadde658
Merge pull request #5644 from lioncash/vmov
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VectorOps: Eliminate unnecessary moves in VMov if applicable
2026-07-01 17:28:42 -07:00
LC
c1e29f9013
VectorOps: Eliminate unnecessary moves in VMov if applicable
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If the destination and source don't match, then we can just zero
and insert directly into the destination instead of a temporary.
2026-06-30 05:06:26 -04:00
LC
4c27dfd5eb
VectorOps: Avoid temporary if able in 256-bit VFRecp
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If we're non-aliasing, we can make use of the destination reg directly.
Makes the non-RPRES path a little nicer.
2026-06-30 04:36:20 -04:00
LC
201216ba54
HostFeatures: Put SVE support querying into single function
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Lets us avoid open-coding long checks for the existence of either
SVE-128 or SVE-256.
2026-06-30 03:34:17 -04:00
Ryan Houdek
16f90b33f3
Merge pull request #5641 from lioncash/minmax
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VectorOps: Reduce temporary usage in 64-bit AdvSIMD min max paths
2026-07-01 14:17:18 -07:00
LC
d3a85e14d9
VectorOps: Reduce temporary usage in 64-bit AdvSIMD min max paths
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We can reorganize these such that they only use one temporary in the
worst case instead of two.
2026-06-30 01:30:40 -04:00
LC
3d289f4489
VectorOps: Avoid move in 256-bit VAddP/VFAddP if possible
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If the first source and destination alias, then it's fine to use the
register in destructive operations, since the source data doesn't need
to be preserved.
Tiny saving, but reduces overall register use in some cases.
2026-06-30 00:23:30 -04:00
LC
c6b0f360fe
AVX: Make use of table swapping constant to trim down relevant ops
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Now we can get rid of excessive overhead, with the ability to improve
this further in the future.
2026-06-29 12:51:30 -04:00
LC
ef19242be3
IR: Add constant for swapping midsections of 256-bit vectors around
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This'll let us eliminate some pretty gnarly inserts while
ZIP1Q/UZP1Q/etc are still unavailable.
2026-06-29 12:50:53 -04:00
Paulo Matos
37b010795e
Re-optimize FYL2X for reduced precision x87 path
2026-06-30 15:00:16 -07:00
LC
2cb4f8b6f5
AVX: Remove unnecessary moves from VPSHUF{D, HW, LW}
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These aren't necessary anymore, since these use operations
that already zero extend.
2026-06-29 08:43:11 -04:00
LC
600e2ddecf
Vector: Only signify 128-bit vector loads in UCOMISxOp
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Mainly a correctness change more than anything. The COMISX and
UCOMISX group of operations only ever load 128 bits when given
a vector source.
No change in codegen, but ensures this doesn't change if any backing
handling changes.
2026-06-28 15:40:14 -04:00
LC
2ec2c39cf1
AVX: Lessen codegen for VMOVMSKPD
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Performs the same thing as what we've done for VMOVMSKPS. Though,
the effect isn't as drastic, given we're only operating on a max
of four elements as opposed to 8.
2026-06-28 14:06:32 -04:00
LC
41fc57f46c
AVX: Lessen codegen for 256-bit VMOVMSKPS
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Currently we can trivially split this up and join the results, which
is much nicer than iterating all the elements individually and shifting
their sign bit over.
2026-06-28 13:52:19 -04:00
Ryan Houdek
9f2e982944
Merge pull request #5617 from simon902/vcvtps2ph
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OpcodeDispatcher: Fix missing zeroing for vcvtps2ph
2026-06-29 10:40:45 -07:00
LC