steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-06 07:00:20 +02:00
Code Issues Packages Projects Releases 66 Wiki Activity

Merge pull request #5962 from Sonicadvance1/249

Browse Source 
Rebase and add test to #5887
This commit is contained in:
LC authored and GitHub committed 2026-09-15 19:56:48 -04:00
2 parents 2790f89949 d06e98ed84
commit 19df181f65
109 files changed
+477 -198
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+17 -5
View File
@@ -3249,9 +3249,10 @@ void OpDispatchBuilder::RestoreX87State(Ref MemBase) {
auto NewFCW = _LoadMemGPR(OpSize::i16Bit, MemBase, OpSize::i16Bit);
_StoreContextGPR(OpSize::i16Bit, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));
Ref Top {};
{
auto NewFSW = _LoadMemGPR(OpSize::i16Bit, MemBase, Constant(2), OpSize::i16Bit, MemOffsetType::SXTX, 1);
ReconstructX87StateFromFSW_Helper(NewFSW);
Top = ReconstructX87StateFromFSW_Helper(NewFSW);
}
{
@@ -3260,10 +3261,21 @@ void OpDispatchBuilder::RestoreX87State(Ref MemBase) {
_StoreContextGPR(OpSize::i8Bit, NewFTW, offsetof(FEXCore::Core::CPUState, AbridgedFTW));
}
for (uint32_t i = 0; i < Core::CPUState::NUM_MMS; i += 2) {
auto MMRegs = LoadMemPairFPR(OpSize::i128Bit, MemBase, i * 16 + 32);
_StoreContextFPR(OpSize::i128Bit, MMRegs.Low, MMBaseOffset() + i * 16);
_StoreContextFPR(OpSize::i128Bit, MMRegs.High, MMBaseOffset() + (i + 1) * 16);
auto SevenConst = Constant(7);
auto low = Constant(~0ULL);
auto high = Constant(0xFFFF);
Ref Mask = _VLoadTwoGPRs(low, high);
const auto StoreSize = ReducedPrecisionMode ? OpSize::i64Bit : OpSize::i128Bit;
for (uint32_t i = 0; i < Core::CPUState::NUM_MMS; ++i) {
Ref Reg = _LoadMemFPR(OpSize::i128Bit, MemBase, Constant(16 * i + 32), OpSize::i8Bit, MemOffsetType::SXTX, 1);
// Mask off the top bits
Reg = _VAnd(OpSize::i128Bit, Reg, Mask);
if (ReducedPrecisionMode) {
// Convert to double precision
Reg = _F80CVT(OpSize::i64Bit, Reg);
}
_StoreContextFPRIndexed(Reg, Top, StoreSize, MMBaseOffset(), IR::OpSizeToSize(OpSize::i128Bit));
Top = _And(OpSize::i32Bit, Add(OpSize::i32Bit, Top, 1), SevenConst);
}
}
FEXCore/include/FEXCore/Core/DiskCache.h
+1 -1
View File
@@ -223,7 +223,7 @@ namespace DiskCache {
// TODO: This header is in global installed header path, but uses internal headers.
// Migrate this once that is fixed.
static constexpr uint16_t FormatVersion = 23;
static constexpr uint16_t FormatVersion = 24;
FEX_DEFAULT_VISIBILITY uint16_t GetFormatVersion();
} // namespace DiskCache
unittests/ASM/FEX_bugs/x87_fxrstor_stack.asm
+115
View File
@@ -0,0 +1,115 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0xb9533de8ad0967d2", "0xb615"],
"XMM1": ["0x30ae762c30b556de", "0x9af3"],
"XMM2": ["0xe86b2b5774313a97", "0x1f6d"],
"XMM3": ["0x48510f254d2fa47f", "0x4886"],
"XMM4": ["0", "0"],
"XMM5": ["0x782366128a6789f2", "0xf881"],
"XMM6": ["0xa56724426b4c72f1", "0xd415"],
"XMM7": ["0xb76472a37404b890", "0x10ad"],
"MM7": ["0x48510f254d2fa47f", "0x4886"],
"MM6": ["0xe86b2b5774313a97", "0x1f6d"],
"MM5": ["0x30ae762c30b556de", "0x9af3"],
"MM4": ["0xb9533de8ad0967d2", "0xb615"],
"MM3": ["0xb76472a37404b890", "0x10ad"],
"MM2": ["0xa56724426b4c72f1", "0xd415"],
"MM1": ["0x782366128a6789f2", "0xf881"],
"MM0": ["0", "0"]
}
}
%endif
; FEX had a bug where fxrstor wasn't restoring x87 registers in the correct order.
; Init x87
fninit
; Load registers with zero
times 8 fldz
; Empty them
times 8 ffreep st0
; Load seven of them with random data
fld tword [rel .random_data + (0 * 10)]
fld tword [rel .random_data + (1 * 10)]
fld tword [rel .random_data + (2 * 10)]
fld tword [rel .random_data + (3 * 10)]
fld tword [rel .random_data + (4 * 10)]
fld tword [rel .random_data + (5 * 10)]
fld tword [rel .random_data + (6 * 10)]
; Rotate the stack a couple of times
fincstp
fincstp
fincstp
; Save the data
fxsave [rel .save_data]
; Init x87
fninit
; Load registers with zero
times 8 fldz
; Empty them
times 8 ffreep st0
; Rotate the stack a couple of times
fincstp
fincstp
; Restore the data
fxrstor [rel .save_data]
; Load the x87 register data in to vectors for testing.
movups xmm0, [rel .save_data + 0x20 + (0 * 16)]
movups xmm1, [rel .save_data + 0x20 + (1 * 16)]
movups xmm2, [rel .save_data + 0x20 + (2 * 16)]
movups xmm3, [rel .save_data + 0x20 + (3 * 16)]
movups xmm4, [rel .save_data + 0x20 + (4 * 16)]
movups xmm5, [rel .save_data + 0x20 + (5 * 16)]
movups xmm6, [rel .save_data + 0x20 + (6 * 16)]
movups xmm7, [rel .save_data + 0x20 + (7 * 16)]
pand xmm0, [rel .x87_mask]
pand xmm1, [rel .x87_mask]
pand xmm2, [rel .x87_mask]
pand xmm3, [rel .x87_mask]
pand xmm4, [rel .x87_mask]
pand xmm5, [rel .x87_mask]
pand xmm6, [rel .x87_mask]
pand xmm7, [rel .x87_mask]
hlt
align 4096
.save_data:
times 64 dq 0
.x87_mask:
dq 0xffff_ffff_ffff_ffff, 0xffff
align 16
; 256bytes of random data
.random_data:
db 0x7f, 0xa4, 0x2f, 0x4d, 0x25, 0x0f, 0x51, 0x48, 0x86, 0x48, 0x97, 0x3a, 0x31, 0x74, 0x57, 0x2b
db 0x6b, 0xe8, 0x6d, 0x1f, 0xde, 0x56, 0xb5, 0x30, 0x2c, 0x76, 0xae, 0x30, 0xf3, 0x9a, 0xd2, 0x67
db 0x09, 0xad, 0xe8, 0x3d, 0x53, 0xb9, 0x15, 0xb6, 0x90, 0xb8, 0x04, 0x74, 0xa3, 0x72, 0x64, 0xb7
db 0xad, 0x10, 0xf1, 0x72, 0x4c, 0x6b, 0x42, 0x24, 0x67, 0xa5, 0x15, 0xd4, 0xf2, 0x89, 0x67, 0x8a
db 0x12, 0x66, 0x23, 0x78, 0x81, 0xf8, 0x96, 0x89, 0xa9, 0xa2, 0x3c, 0x3d, 0x82, 0x6b, 0xa2, 0x19
db 0xb0, 0x12, 0x97, 0x68, 0xab, 0x58, 0xf6, 0x00, 0x72, 0x19, 0xd2, 0x1e, 0x03, 0x9d, 0x7d, 0xc9
db 0xc8, 0x55, 0xdf, 0x98, 0x22, 0x43, 0x86, 0x1c, 0xcc, 0xe9, 0x1b, 0x89, 0xda, 0xfe, 0x9b, 0xb2
db 0x47, 0x21, 0x0f, 0x71, 0x28, 0xbd, 0xb0, 0x88, 0x38, 0xac, 0xb5, 0x7f, 0x88, 0x5e, 0xe9, 0xc4
db 0xe4, 0x5b, 0x3e, 0xd0, 0x2a, 0x8c, 0xdf, 0xa7, 0xea, 0x95, 0xd3, 0xc2, 0xee, 0xd1, 0x70, 0x6c
db 0x18, 0x77, 0xc1, 0x38, 0x7b, 0xfc, 0xa9, 0x58, 0x92, 0xe8, 0xc6, 0xcd, 0x07, 0x5d, 0x3d, 0x76
db 0xf4, 0x4c, 0x5b, 0x25, 0x7f, 0x9b, 0x02, 0x41, 0x78, 0x39, 0x9e, 0x3e, 0x4c, 0xa2, 0x79, 0xca
db 0x1c, 0xe9, 0xf2, 0x9a, 0xaf, 0x6d, 0xfa, 0x57, 0x10, 0xc7, 0xfd, 0x5f, 0x20, 0x80, 0xf5, 0x65
db 0x3c, 0x77, 0xfb, 0xa8, 0xdf, 0x94, 0x16, 0x4f, 0xc0, 0x78, 0x00, 0x76, 0x03, 0x8c, 0x82, 0x10
db 0x7f, 0x07, 0xe0, 0x02, 0x92, 0xbb, 0xf9, 0x2e, 0xfa, 0x3d, 0x88, 0xc8, 0x24, 0x27, 0xa6, 0x1e
db 0x04, 0x90, 0xf6, 0xf8, 0x76, 0x0a, 0x4c, 0x94, 0xbc, 0xb7, 0x8d, 0x8b, 0xf9, 0x65, 0xf5, 0x07
db 0x7f, 0xc1, 0x37, 0x78, 0xa1, 0x1f, 0xc4, 0x10, 0x6c, 0x29, 0x5e, 0x7e, 0x32, 0x24, 0x92, 0x09
unittests/InstructionCountCI/AFP/H0F3A.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"roundss xmm0, xmm1, 00000000b": {
unittests/InstructionCountCI/AFP/SVE256/Secondary.json
+1 -1
View File
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"cvtpi2ps xmm0, [rax]": {
unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json
+1 -1
View File
@@ -9,7 +9,7 @@
"DisabledHostFeatures": [
"RPRES"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"cvtsi2ss xmm0, eax": {
unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json
+1 -1
View File
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"cvtsi2sd xmm0, eax": {
unittests/InstructionCountCI/AFP/Secondary.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"cvtpi2ps xmm0, [rax]": {
unittests/InstructionCountCI/AFP/Secondary_REP.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"RPRES"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"cvtsi2ss xmm0, eax": {
unittests/InstructionCountCI/AFP/Secondary_REPNE.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"cvtsi2sd xmm0, eax": {
unittests/InstructionCountCI/AFP/VEX_map1.json
+1 -1
View File
@@ -9,7 +9,7 @@
"DisabledHostFeatures": [
"RPRES"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vsqrtss xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AFP/VEX_map3.json
+1 -1
View File
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vroundss xmm0, xmm1, 00000000b": {
unittests/InstructionCountCI/AVX128/FMA4.json
+1 -1
View File
@@ -7,7 +7,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vfmaddsubps xmm0, xmm1, xmm2, xmm3": {
unittests/InstructionCountCI/AVX128/VEX_map1.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vmovups xmm0, xmm0": {
unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vaddsubpd xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FLAGM2",
"SVE256"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vmovntps [rax], xmm0": {
unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vucomiss xmm0, xmm1": {
unittests/InstructionCountCI/AVX128/VEX_map2.json
+1 -1
View File
@@ -11,7 +11,7 @@
"I8MM",
"DOTPROD"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vpshufb xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vfmadd132ss xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json
+1 -1
View File
@@ -12,7 +12,7 @@
"SVE256",
"I8MM"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vpdpbusd xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json
+1 -1
View File
@@ -11,7 +11,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vpdpbusd xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FLAGM2",
"SVE256"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vmovntdqa xmm0, [rax]": {
unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
+1 -1
View File
@@ -11,7 +11,7 @@
"SVE256",
"SVEBITPERM"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vtestps xmm0, xmm1": {
unittests/InstructionCountCI/AVX128/VEX_map3.json
+1 -1
View File
@@ -7,7 +7,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vpermq ymm0, ymm1, 1": {
unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json
+1 -1
View File
@@ -8,7 +8,7 @@
"AFP",
"SVE256"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vblendvps xmm0, xmm1, xmm2, xmm3": {
unittests/InstructionCountCI/AVX128/VEX_map_group.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"SVE128"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vpsrlw xmm0, xmm1, 0": {
unittests/InstructionCountCI/Atomics.json
+1 -1
View File
@@ -9,7 +9,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"lock add byte [rax], cl": {
unittests/InstructionCountCI/Crypto/H0F38.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"sha1nexte xmm0, xmm1": {
unittests/InstructionCountCI/Crypto/H0F38_SVE128.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"sha1nexte xmm0, xmm1": {
unittests/InstructionCountCI/Crypto/H0F3A.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"pclmulqdq xmm0, xmm1, 00000b": {
unittests/InstructionCountCI/DDD.json
+1 -1
View File
@@ -10,7 +10,7 @@
"AFP",
"RPRES"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Comment": [
"These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers",
unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
+1 -1
View File
@@ -8,7 +8,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Comment": [
"Instructions that explicitly push against the limits of ARM's loadstore instructions"
unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json
+1 -1
View File
@@ -8,7 +8,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Comment": [
"Instructions that explicitly push against the limits of ARM's loadstore instructions"
unittests/InstructionCountCI/FEXOpt/MultiInst.json
+1 -1
View File
@@ -13,7 +13,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json
+1 -1
View File
@@ -11,7 +11,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"RPRES"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json
+1 -1
View File
@@ -14,7 +14,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json
+1 -1
View File
@@ -14,7 +14,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Comment": [
"These are instruction combinations that could be more optimal if FEX optimized for them"
unittests/InstructionCountCI/FEXOpt/libnss.json
+1 -1
View File
@@ -12,7 +12,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Comment": [],
"Instructions": {
unittests/InstructionCountCI/FlagM/Atomics.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"lock add byte [rax], cl": {
unittests/InstructionCountCI/FlagM/FlagOpts.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"Chained add": {
unittests/InstructionCountCI/FlagM/H0F38.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"ptest xmm0, xmm1": {
unittests/InstructionCountCI/FlagM/HotBlocks.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"The Witcher 3": {
unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"Sonic Mania movie player": {
unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"FMOD scalar loop": {
unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"The Sims 1 hot block": {
unittests/InstructionCountCI/FlagM/Primary.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"add bl, cl": {
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"add al, 1": {
unittests/InstructionCountCI/FlagM/Primary_32Bit.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"push es": {
unittests/InstructionCountCI/FlagM/Secondary.json
+1 -1
View File
@@ -11,7 +11,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"ucomiss xmm0, xmm1": {
unittests/InstructionCountCI/FlagM/SecondaryGroup.json
+120 -44
View File
@@ -11,7 +11,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"sgdt [rax]": {
@@ -1364,7 +1364,7 @@
]
},
"fxrstor [rax]": {
"ExpectedInstructionCount": 48,
"ExpectedInstructionCount": 86,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
@@ -1372,30 +1372,68 @@
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #1051]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w24, w20, #14, #1",
"ubfx w22, w20, #8, #1",
"ubfx w23, w20, #9, #1",
"ubfx w24, w20, #10, #1",
"ubfx w30, w20, #14, #1",
"ubfx w20, w20, #0, #1",
"strb w21, [x28, #1048]",
"strb w22, [x28, #1049]",
"strb w23, [x28, #1050]",
"strb w24, [x28, #1054]",
"strb w22, [x28, #1048]",
"strb w23, [x28, #1049]",
"strb w24, [x28, #1050]",
"strb w30, [x28, #1054]",
"strb w20, [x28, #1040]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1202]",
"ldp q2, q3, [x4, #32]",
"str q2, [x28, #1056]",
"str q3, [x28, #1072]",
"ldp q2, q3, [x4, #64]",
"str q2, [x28, #1088]",
"str q3, [x28, #1104]",
"ldp q2, q3, [x4, #96]",
"str q2, [x28, #1120]",
"str q3, [x28, #1136]",
"ldp q2, q3, [x4, #128]",
"str q2, [x28, #1152]",
"str q3, [x28, #1168]",
"mov x20, #0xffffffffffffffff",
"mov w22, #0xffff",
"fmov d2, x20",
"fmov v2.D[1], x22",
"ldr q3, [x4, #32]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x21, lsl #4",
"str q3, [x0, #1056]",
"add w20, w21, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #48]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #64]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #80]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #96]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #112]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #128]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #144]",
"and v2.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1056]",
"ldp q16, q17, [x4, #160]",
"ldp q18, q19, [x4, #192]",
"ldp q20, q21, [x4, #224]",
@@ -1703,43 +1741,81 @@
]
},
"xrstor [rax]": {
"ExpectedInstructionCount": 133,
"ExpectedInstructionCount": 171,
"Comment": "GROUP15 0x0F 0xAE /5",
"ExpectedArm64ASM": [
"sub sp, sp, #0x40 (64)",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #0, #1",
"cbnz x20, #+0x8",
"b #+0x7c",
"b #+0x114",
"ldrh w20, [x4]",
"strh w20, [x28, #1200]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #1051]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w24, w20, #14, #1",
"ubfx w22, w20, #8, #1",
"ubfx w23, w20, #9, #1",
"ubfx w24, w20, #10, #1",
"ubfx w30, w20, #14, #1",
"ubfx w20, w20, #0, #1",
"strb w21, [x28, #1048]",
"strb w22, [x28, #1049]",
"strb w23, [x28, #1050]",
"strb w24, [x28, #1054]",
"strb w22, [x28, #1048]",
"strb w23, [x28, #1049]",
"strb w24, [x28, #1050]",
"strb w30, [x28, #1054]",
"strb w20, [x28, #1040]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1202]",
"ldp q2, q3, [x4, #32]",
"str q2, [x28, #1056]",
"str q3, [x28, #1072]",
"ldp q2, q3, [x4, #64]",
"str q2, [x28, #1088]",
"str q3, [x28, #1104]",
"ldp q2, q3, [x4, #96]",
"str q2, [x28, #1120]",
"str q3, [x28, #1136]",
"ldp q2, q3, [x4, #128]",
"str q2, [x28, #1152]",
"str q3, [x28, #1168]",
"mov x20, #0xffffffffffffffff",
"mov w22, #0xffff",
"fmov d2, x20",
"fmov v2.D[1], x22",
"ldr q3, [x4, #32]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x21, lsl #4",
"str q3, [x0, #1056]",
"add w20, w21, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #48]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #64]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #80]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #96]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #112]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #128]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #144]",
"and v2.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1056]",
"b #+0x4c",
"mov w20, #0x37f",
"strh w20, [x28, #1200]",
unittests/InstructionCountCI/FlagM/SecondaryModRM.json
+1 -1
View File
@@ -11,7 +11,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"xgetbv": {
unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
+1 -1
View File
@@ -11,7 +11,7 @@
"AFP",
"FCMA"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"ucomisd xmm0, xmm1": {
unittests/InstructionCountCI/FlagM/Secondary_REP.json
+1 -1
View File
@@ -12,7 +12,7 @@
"AFP",
"CSSC"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"popcnt ax, bx": {
unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json
+1 -1
View File
@@ -12,7 +12,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"popcnt ax, bx": {
unittests/InstructionCountCI/FlagM/VEX_map1.json
+1 -1
View File
@@ -12,7 +12,7 @@
"RPRES",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vucomiss xmm0, xmm1": {
unittests/InstructionCountCI/FlagM/VEX_map2.json
+1 -1
View File
@@ -10,7 +10,7 @@
"AFP",
"SVEBITPERM"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vtestps xmm0, xmm1": {
unittests/InstructionCountCI/FlagM/VEX_map_group.json
+1 -1
View File
@@ -9,7 +9,7 @@
"DisabledHostFeatures": [
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"blsr eax, ebx": {
unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87-HalfLife.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87-Oblivion.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
+1 -1
View File
@@ -10,7 +10,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87.json
+1 -1
View File
@@ -11,7 +11,7 @@
"CSSC",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"fadd dword [rax]": {
unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"Block1": {
unittests/InstructionCountCI/FlagM/x87_f64.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"fadd dword [rax]": {
unittests/InstructionCountCI/H0F38.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FLAGM2",
"CRYPTO"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"pshufb mm0, mm1": {
unittests/InstructionCountCI/H0F3A.json
+1 -1
View File
@@ -8,7 +8,7 @@
"AFP",
"CRYPTO"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Comment": [
"SSE4.2 string instructions are skipped here.",
unittests/InstructionCountCI/H0F3A_SVE128.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"dpps xmm0, xmm1, 00000000b": {
unittests/InstructionCountCI/MOPS/Primary.json
+1 -1
View File
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"rep movsb": {
unittests/InstructionCountCI/Primary.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FLAGM2",
"MOPS"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"add bl, cl": {
unittests/InstructionCountCI/PrimaryGroup.json
+1 -1
View File
@@ -9,7 +9,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Comment": [
"Instructions in this table that are marked optimal don't have their flag calculation part of this assumption",
unittests/InstructionCountCI/Primary_32Bit.json
+1 -1
View File
@@ -9,7 +9,7 @@
"FlagM",
"FlagM2"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"push es": {
unittests/InstructionCountCI/RPRES/DDD.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"pfrcpv mm0, mm1": {
unittests/InstructionCountCI/RPRES/Secondary.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"rsqrtps xmm0, xmm1": {
unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"rsqrtss xmm0, xmm1": {
unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json
+1 -1
View File
@@ -8,7 +8,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vrsqrtps xmm0, xmm1": {
unittests/InstructionCountCI/Repeat.json
+1 -1
View File
@@ -6,7 +6,7 @@
"SVE128",
"SVE256"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {}
}
unittests/InstructionCountCI/SSE42_Strings.json
+1 -1
View File
@@ -33,7 +33,7 @@
" - 1b: ECX = MSB",
"[7] - Reserved"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"pcmpestrm xmm0, xmm1, 0_0_00_00_00b": {
unittests/InstructionCountCI/Secondary.json
+1 -1
View File
@@ -12,7 +12,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Comment": [
"MMX instructions are defined as optimal without SRA being used for these instructions.",
unittests/InstructionCountCI/SecondaryGroup.json
+120 -44
View File
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"sgdt [rax]": {
@@ -1636,7 +1636,7 @@
]
},
"fxrstor [rax]": {
"ExpectedInstructionCount": 48,
"ExpectedInstructionCount": 86,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
@@ -1644,30 +1644,68 @@
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #1051]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w24, w20, #14, #1",
"ubfx w22, w20, #8, #1",
"ubfx w23, w20, #9, #1",
"ubfx w24, w20, #10, #1",
"ubfx w30, w20, #14, #1",
"ubfx w20, w20, #0, #1",
"strb w21, [x28, #1048]",
"strb w22, [x28, #1049]",
"strb w23, [x28, #1050]",
"strb w24, [x28, #1054]",
"strb w22, [x28, #1048]",
"strb w23, [x28, #1049]",
"strb w24, [x28, #1050]",
"strb w30, [x28, #1054]",
"strb w20, [x28, #1040]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1202]",
"ldp q2, q3, [x4, #32]",
"str q2, [x28, #1056]",
"str q3, [x28, #1072]",
"ldp q2, q3, [x4, #64]",
"str q2, [x28, #1088]",
"str q3, [x28, #1104]",
"ldp q2, q3, [x4, #96]",
"str q2, [x28, #1120]",
"str q3, [x28, #1136]",
"ldp q2, q3, [x4, #128]",
"str q2, [x28, #1152]",
"str q3, [x28, #1168]",
"mov x20, #0xffffffffffffffff",
"mov w22, #0xffff",
"fmov d2, x20",
"fmov v2.D[1], x22",
"ldr q3, [x4, #32]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x21, lsl #4",
"str q3, [x0, #1056]",
"add w20, w21, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #48]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #64]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #80]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #96]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #112]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #128]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #144]",
"and v2.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1056]",
"ldp q16, q17, [x4, #160]",
"ldp q18, q19, [x4, #192]",
"ldp q20, q21, [x4, #224]",
@@ -1871,43 +1909,81 @@
]
},
"xrstor [rax]": {
"ExpectedInstructionCount": 133,
"ExpectedInstructionCount": 171,
"Comment": "GROUP15 0x0F 0xAE /5",
"ExpectedArm64ASM": [
"sub sp, sp, #0x40 (64)",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #0, #1",
"cbnz x20, #+0x8",
"b #+0x7c",
"b #+0x114",
"ldrh w20, [x4]",
"strh w20, [x28, #1200]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #1051]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w24, w20, #14, #1",
"ubfx w22, w20, #8, #1",
"ubfx w23, w20, #9, #1",
"ubfx w24, w20, #10, #1",
"ubfx w30, w20, #14, #1",
"ubfx w20, w20, #0, #1",
"strb w21, [x28, #1048]",
"strb w22, [x28, #1049]",
"strb w23, [x28, #1050]",
"strb w24, [x28, #1054]",
"strb w22, [x28, #1048]",
"strb w23, [x28, #1049]",
"strb w24, [x28, #1050]",
"strb w30, [x28, #1054]",
"strb w20, [x28, #1040]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1202]",
"ldp q2, q3, [x4, #32]",
"str q2, [x28, #1056]",
"str q3, [x28, #1072]",
"ldp q2, q3, [x4, #64]",
"str q2, [x28, #1088]",
"str q3, [x28, #1104]",
"ldp q2, q3, [x4, #96]",
"str q2, [x28, #1120]",
"str q3, [x28, #1136]",
"ldp q2, q3, [x4, #128]",
"str q2, [x28, #1152]",
"str q3, [x28, #1168]",
"mov x20, #0xffffffffffffffff",
"mov w22, #0xffff",
"fmov d2, x20",
"fmov v2.D[1], x22",
"ldr q3, [x4, #32]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x21, lsl #4",
"str q3, [x0, #1056]",
"add w20, w21, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #48]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #64]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #80]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #96]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #112]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #128]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #144]",
"and v2.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1056]",
"b #+0x4c",
"mov w20, #0x37f",
"strh w20, [x28, #1200]",
unittests/InstructionCountCI/SecondaryModRM.json
+1 -1
View File
@@ -11,7 +11,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"xgetbv": {
unittests/InstructionCountCI/Secondary_32Bit.json
+1 -1
View File
@@ -7,7 +7,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"push fs": {
unittests/InstructionCountCI/Secondary_OpSize.json
+1 -1
View File
@@ -12,7 +12,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"movupd xmm0, xmm0": {
unittests/InstructionCountCI/Secondary_OpSize_FCMA.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"addsubpd xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_OpSize_SVE128.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"psrlw xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_OpSize_SVE256.json
+1 -1
View File
@@ -7,7 +7,7 @@
"AFP"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"pmulhuw xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REP.json
+1 -1
View File
@@ -12,7 +12,7 @@
"FRINTTS",
"CSSC"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"movss xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REPNE.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FCMA",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"movsd xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REPNE_FCMA.json
+1 -1
View File
@@ -9,7 +9,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"addsubps xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REPNE_SVE128.json
+1 -1
View File
@@ -10,7 +10,7 @@
"FCMA",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"cvtpd2dq xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REP_FRINTTS.json
+1 -1
View File
@@ -12,7 +12,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"cvttss2si eax, xmm0": {
unittests/InstructionCountCI/Secondary_SVE128.json
+1 -1
View File
@@ -8,7 +8,7 @@
"SVE256",
"AFP"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"movmskps eax, xmm0": {
unittests/InstructionCountCI/VEX_map1.json
+1 -1
View File
@@ -13,7 +13,7 @@
"FLAGM2",
"FRINTTS"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vmovups xmm0, xmm0": {
unittests/InstructionCountCI/VEX_map1_FCMA.json
+1 -1
View File
@@ -8,7 +8,7 @@
"FCMA"
],
"DisabledHostFeatures": [],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vaddsubpd xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/VEX_map1_FRINTTS.json
+1 -1
View File
@@ -13,7 +13,7 @@
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vcvttss2si eax, xmm0": {
unittests/InstructionCountCI/VEX_map2.json
+1 -1
View File
@@ -13,7 +13,7 @@
"I8MM",
"DOTPROD"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vpshufb xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/VEX_map2_DOTPROD.json
+1 -1
View File
@@ -13,7 +13,7 @@
"SVEBITPERM",
"I8MM"
],
"BinaryCacheVersion": 23
"BinaryCacheVersion": 24
},
"Instructions": {
"vpdpbusd xmm0, xmm1, xmm2": {
Loaded 100 of 109 files, more files were not shown because too many files have changed in this diff. Show more