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FEX-Emu--FEX/unittests/InstructionCountCI/SecondaryGroup.json
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Ryan Houdek d06e98ed84 InstcountCI: Update
2026-09-15 16:40:55 -07:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [
"RNG"
],
"DisabledHostFeatures": [
"SVE128",
"SVE256",
"AFP",
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 24
},
"Instructions": {
"sgdt [rax]": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP7 0x0F 0x1 /0",
"ExpectedArm64ASM": [
"strh wzr, [x4]",
"mov x20, #0xfffffffffffe0000",
"stur x20, [x4, #2]"
]
},
"bt ax, 0": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"bt eax, 0": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"bt rax, 0": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"bt ax, 15": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #15, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"bt eax, 31": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #31, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"bt rax, 63": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"lsr x20, x4, #63",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"bt word [rax], 0": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"bt dword [rax], 0": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"bt qword [rax], 0": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"bt word [rax], 15": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #1]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"bt dword [rax], 31": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #3]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"bt qword [rax], 63": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #7]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"bts ax, 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"orr w20, w4, #0x1",
"bfxil x4, x20, #0, #16",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"bts eax, 0": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"orr w4, w4, #0x1",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"bts rax, 0": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"orr x4, x4, #0x1",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"bts ax, 15": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"ubfx x20, x4, #15, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"orr w20, w4, #0x8000",
"bfxil x4, x20, #0, #16",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"bts eax, 31": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"ubfx x20, x4, #31, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"orr w4, w4, #0x80000000",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"bts rax, 63": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"lsr x20, x4, #63",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"orr x4, x4, #0x8000000000000000",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"bts word [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"orr x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"bts dword [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"orr x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"bts qword [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"orr x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"bts word [rax], 15": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #1]",
"orr x21, x20, #0x80",
"strb w21, [x4, #1]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"bts dword [rax], 31": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #3]",
"orr x21, x20, #0x80",
"strb w21, [x4, #3]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"bts qword [rax], 63": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #7]",
"orr x21, x20, #0x80",
"strb w21, [x4, #7]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock bts word [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldsetalb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock bts dword [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldsetalb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock bts qword [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldsetalb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock bts word [rax], 15": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x1 (1)",
"ldsetalb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock bts dword [rax], 31": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x3 (3)",
"ldsetalb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock bts qword [rax], 63": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x7 (7)",
"ldsetalb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btr ax, 0": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"and w20, w4, #0xfffffffe",
"bfxil x4, x20, #0, #16",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"btr eax, 0": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"and w4, w4, #0xfffffffe",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"btr rax, 0": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"and x4, x4, #0xfffffffffffffffe",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"btr ax, 15": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ubfx x20, x4, #15, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"and w20, w4, #0xffff7fff",
"bfxil x4, x20, #0, #16",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"btr eax, 31": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ubfx x20, x4, #31, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"and w4, w4, #0x7fffffff",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"btr rax, 63": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"lsr x20, x4, #63",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"and x4, x4, #0x7fffffffffffffff",
"eor w20, w21, #0x20000000",
"msr nzcv, x20"
]
},
"btr word [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"and x21, x20, #0xfffffffffffffffe",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btr dword [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"and x21, x20, #0xfffffffffffffffe",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btr qword [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"and x21, x20, #0xfffffffffffffffe",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btr word [rax], 15": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #1]",
"and x21, x20, #0xffffffffffffff7f",
"strb w21, [x4, #1]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btr dword [rax], 31": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #3]",
"and x21, x20, #0xffffffffffffff7f",
"strb w21, [x4, #3]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btr qword [rax], 63": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #7]",
"and x21, x20, #0xffffffffffffff7f",
"strb w21, [x4, #7]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock btr word [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldclralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock btr dword [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldclralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock btr qword [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldclralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock btr word [rax], 15": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x1 (1)",
"ldclralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock btr dword [rax], 31": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x3 (3)",
"ldclralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock btr qword [rax], 63": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x7 (7)",
"ldclralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btc ax, 0": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"eor w20, w4, #0x1",
"ubfx x21, x20, #0, #1",
"mrs x22, nzcv",
"bfi w22, w21, #29, #1",
"bfxil x4, x20, #0, #16",
"msr nzcv, x22"
]
},
"btc eax, 0": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"eor w4, w4, #0x1",
"ubfx x20, x4, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btc rax, 0": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"eor x4, x4, #0x1",
"ubfx x20, x4, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btc ax, 15": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"eor w20, w4, #0x8000",
"ubfx x21, x20, #15, #1",
"mrs x22, nzcv",
"bfi w22, w21, #29, #1",
"bfxil x4, x20, #0, #16",
"msr nzcv, x22"
]
},
"btc eax, 31": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"eor w4, w4, #0x80000000",
"ubfx x20, x4, #31, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btc rax, 63": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"eor x4, x4, #0x8000000000000000",
"lsr x20, x4, #63",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btc word [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btc dword [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btc qword [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btc word [rax], 15": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #1]",
"eor x21, x20, #0x80",
"strb w21, [x4, #1]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btc dword [rax], 31": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #3]",
"eor x21, x20, #0x80",
"strb w21, [x4, #3]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"btc qword [rax], 63": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #7]",
"eor x21, x20, #0x80",
"strb w21, [x4, #7]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock btc word [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldeoralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock btc dword [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldeoralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock btc qword [rax], 0": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldeoralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock btc word [rax], 15": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x1 (1)",
"ldeoralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock btc dword [rax], 31": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x3 (3)",
"ldeoralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock btc qword [rax], 63": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x7 (7)",
"ldeoralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"cmpxchg8b [rbp]": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP9 0x0F 0xC7 /1",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x5",
"caspal w20, w21, w6, w7, [x9]",
"mrs x0, nzcv",
"cmp w20, w4",
"ccmp w21, w5, #nzcv, eq",
"cset w1, eq",
"bfi w0, w1, #30, #1",
"msr nzcv, x0",
"csel x4, x20, x4, ne",
"csel x5, x21, x5, ne"
]
},
"cmpxchg16b [rbp]": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP9 0x0F 0xC7 /1",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x5",
"caspal x20, x21, x6, x7, [x9]",
"mrs x0, nzcv",
"cmp x20, x4",
"ccmp x21, x5, #nzcv, eq",
"cset w1, eq",
"bfi w0, w1, #30, #1",
"msr nzcv, x0",
"csel x4, x20, x4, ne",
"csel x5, x21, x5, ne"
]
},
"rdrand ax": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
"bfxil x4, x20, #0, #16",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"mov w0, w27",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
]
},
"rdrand eax": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
"mov w4, w20",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"mov w0, w27",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
]
},
"rdrand rax": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x4, rndr",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"mov w0, w27",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
]
},
"rdseed ax": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"bfxil x4, x20, #0, #16",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"mov w0, w27",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
]
},
"rdseed eax": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"mov w4, w20",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"mov w0, w27",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
]
},
"rdseed rax": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x4, rndrrs",
"cset x20, eq",
"mov w26, #0x1",
"mov w27, #0x0",
"mov w0, w27",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
]
},
"rdpid eax": {
"ExpectedInstructionCount": 20,
"Comment": "GROUP9 0xF3 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #1032]",
"str x25, [x28, #176]",
"str x8, [x28, #64]",
"mov w0, #0x100",
"str x0, [x28, #1480]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
"add x1, sp, #0x4 (4)",
"svc #0x0",
"ldp w0, w1, [sp]",
"add sp, sp, #0x10 (16)",
"ldr x25, [x28, #176]",
"ldr w8, [x28, #1032]",
"msr nzcv, x8",
"ldr x8, [x28, #64]",
"str xzr, [x28, #1480]",
"orr x20, x0, x1, lsl #12",
"mov w4, w20"
]
},
"rdpid rax": {
"ExpectedInstructionCount": 20,
"Comment": "GROUP9 0xF3 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #1032]",
"str x25, [x28, #176]",
"str x8, [x28, #64]",
"mov w0, #0x100",
"str x0, [x28, #1480]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
"add x1, sp, #0x4 (4)",
"svc #0x0",
"ldp w0, w1, [sp]",
"add sp, sp, #0x10 (16)",
"ldr x25, [x28, #176]",
"ldr w8, [x28, #1032]",
"msr nzcv, x8",
"ldr x8, [x28, #64]",
"str xzr, [x28, #1480]",
"orr x20, x0, x1, lsl #12",
"mov w4, w20"
]
},
"psrlw mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": []
},
"psrlw mm0, 15": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ushr v2.8h, v2.8h, #15",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrlw mm0, 16": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrlw xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": []
},
"psrlw xmm0, 15": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ushr v16.8h, v16.8h, #15"
]
},
"psrlw xmm0, 16": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"psraw mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": []
},
"psraw mm0, 15": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psraw mm0, 16": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psraw xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": []
},
"psraw xmm0, 15": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"sshr v16.8h, v16.8h, #15"
]
},
"psraw xmm0, 16": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"sshr v16.8h, v16.8h, #15"
]
},
"psllw mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": []
},
"psllw mm0, 15": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"shl v2.8h, v2.8h, #15",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psllw mm0, 16": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psllw xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": []
},
"psllw xmm0, 15": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"shl v16.8h, v16.8h, #15"
]
},
"psllw xmm0, 16": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"psrld mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": []
},
"psrld mm0, 31": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ushr v2.4s, v2.4s, #31",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrld mm0, 32": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrld xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": []
},
"psrld xmm0, 31": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ushr v16.4s, v16.4s, #31"
]
},
"psrld xmm0, 32": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"psrad mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": []
},
"psrad mm0, 31": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrad mm0, 32": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrad xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": []
},
"psrad xmm0, 31": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"sshr v16.4s, v16.4s, #31"
]
},
"psrad xmm0, 32": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"sshr v16.4s, v16.4s, #31"
]
},
"pslld mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": []
},
"pslld mm0, 31": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"shl v2.4s, v2.4s, #31",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pslld mm0, 32": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"pslld xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": []
},
"pslld xmm0, 31": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"shl v16.4s, v16.4s, #31"
]
},
"pslld xmm0, 32": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"psrlq mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": []
},
"psrlq mm0, 63": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"ushr v2.2d, v2.2d, #63",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrlq mm0, 64": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psrlq xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": []
},
"psrlq xmm0, 63": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ushr v16.2d, v16.2d, #63"
]
},
"psrlq xmm0, 64": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"psrldq xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /3",
"ExpectedArm64ASM": []
},
"psrldq xmm0, 15": {
"ExpectedInstructionCount": 2,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ext v16.16b, v16.16b, v2.16b, #15"
]
},
"psrldq xmm0, 16": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"psllq mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": []
},
"psllq mm0, 63": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"shl v2.2d, v2.2d, #63",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psllq mm0, 64": {
"ExpectedInstructionCount": 7,
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"strb wzr, [x28, #1051]",
"mov w20, #0xffff",
"strb w20, [x28, #1202]",
"ldr d2, [x28, #1056]",
"movi v2.2d, #0x0",
"str d2, [x28, #1056]",
"strh w20, [x28, #1064]"
]
},
"psllq xmm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": []
},
"psllq xmm0, 63": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"shl v16.2d, v16.2d, #63"
]
},
"psllq xmm0, 64": {
"ExpectedInstructionCount": 1,
"Type": "SSE",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"fxsave [rax]": {
"ExpectedInstructionCount": 68,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #1200]",
"strh w20, [x4]",
"ldrb w20, [x28, #1051]",
"lsl x20, x20, #11",
"ldrb w21, [x28, #1048]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #1049]",
"orr x20, x20, x21, lsl #9",
"ldrb w21, [x28, #1050]",
"orr x20, x20, x21, lsl #10",
"ldrb w21, [x28, #1054]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #1040]",
"orr x20, x20, x21",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1202]",
"strb w20, [x4, #4]",
"ldrb w20, [x28, #1051]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #32]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #48]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #64]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #80]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #96]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #112]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #128]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #144]",
"stp q16, q17, [x4, #160]",
"stp q18, q19, [x4, #192]",
"stp q20, q21, [x4, #224]",
"stp q22, q23, [x4, #256]",
"stp q24, q25, [x4, #288]",
"stp q26, q27, [x4, #320]",
"stp q28, q29, [x4, #352]",
"stp q30, q31, [x4, #384]",
"ldr w20, [x28, #972]",
"mov w21, #0xffc0",
"and w20, w20, #0xffc0",
"stp w20, w21, [x4, #24]"
]
},
"rdfsbase eax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr w4, [x28, #1000]"
]
},
"rdfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr x4, [x28, #1000]"
]
},
"fxrstor [rax]": {
"ExpectedInstructionCount": 86,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"strh w20, [x28, #1200]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #1051]",
"ubfx w22, w20, #8, #1",
"ubfx w23, w20, #9, #1",
"ubfx w24, w20, #10, #1",
"ubfx w30, w20, #14, #1",
"ubfx w20, w20, #0, #1",
"strb w22, [x28, #1048]",
"strb w23, [x28, #1049]",
"strb w24, [x28, #1050]",
"strb w30, [x28, #1054]",
"strb w20, [x28, #1040]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1202]",
"mov x20, #0xffffffffffffffff",
"mov w22, #0xffff",
"fmov d2, x20",
"fmov v2.D[1], x22",
"ldr q3, [x4, #32]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x21, lsl #4",
"str q3, [x0, #1056]",
"add w20, w21, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #48]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #64]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #80]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #96]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #112]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #128]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #144]",
"and v2.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1056]",
"ldp q16, q17, [x4, #160]",
"ldp q18, q19, [x4, #192]",
"ldp q20, q21, [x4, #224]",
"ldp q22, q23, [x4, #256]",
"ldp q24, q25, [x4, #288]",
"ldp q26, q27, [x4, #320]",
"ldp q28, q29, [x4, #352]",
"ldp q30, q31, [x4, #384]",
"ldr w20, [x4, #24]",
"and w20, w20, #0xffc0",
"str w20, [x28, #972]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x21, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0"
]
},
"rdgsbase eax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr w4, [x28, #992]"
]
},
"rdgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr x4, [x28, #992]"
]
},
"ldmxcsr [rax]": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"and w20, w20, #0xffc0",
"str w20, [x28, #972]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x21, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0"
]
},
"wrfsbase eax": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #1000]"
]
},
"wrfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"str x4, [x28, #1000]"
]
},
"stmxcsr [rax]": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"ldr w20, [x28, #972]",
"and w20, w20, #0xffc0",
"str w20, [x4]"
]
},
"wrgsbase eax": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #992]"
]
},
"wrgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"str x4, [x28, #992]"
]
},
"xsave [rax]": {
"ExpectedInstructionCount": 98,
"Comment": "GROUP15 0x0F 0xAE /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"cbnz x20, #+0x8",
"b #+0xe4",
"ldrh w20, [x28, #1200]",
"strh w20, [x4]",
"ldrb w20, [x28, #1051]",
"lsl x20, x20, #11",
"ldrb w21, [x28, #1048]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #1049]",
"orr x20, x20, x21, lsl #9",
"ldrb w21, [x28, #1050]",
"orr x20, x20, x21, lsl #10",
"ldrb w21, [x28, #1054]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #1040]",
"orr x20, x20, x21",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1202]",
"strb w20, [x4, #4]",
"ldrb w20, [x28, #1051]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #32]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #48]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #64]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #80]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #96]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #112]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #128]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #144]",
"ubfx x20, x4, #1, #1",
"cbnz x20, #+0x8",
"b #+0x24",
"stp q16, q17, [x4, #160]",
"stp q18, q19, [x4, #192]",
"stp q20, q21, [x4, #224]",
"stp q22, q23, [x4, #256]",
"stp q24, q25, [x4, #288]",
"stp q26, q27, [x4, #320]",
"stp q28, q29, [x4, #352]",
"stp q30, q31, [x4, #384]",
"ubfx x20, x4, #2, #1",
"cbnz x20, #+0x8",
"b #+0x44",
"ldp q2, q3, [x28, #192]",
"stp q2, q3, [x4, #576]",
"ldp q2, q3, [x28, #224]",
"stp q2, q3, [x4, #608]",
"ldp q2, q3, [x28, #256]",
"stp q2, q3, [x4, #640]",
"ldp q2, q3, [x28, #288]",
"stp q2, q3, [x4, #672]",
"ldp q2, q3, [x28, #320]",
"stp q2, q3, [x4, #704]",
"ldp q2, q3, [x28, #352]",
"stp q2, q3, [x4, #736]",
"ldp q2, q3, [x28, #384]",
"stp q2, q3, [x4, #768]",
"ldp q2, q3, [x28, #416]",
"stp q2, q3, [x4, #800]",
"ubfx x20, x4, #1, #2",
"cbnz x20, #+0x8",
"b #+0x14",
"ldr w20, [x28, #972]",
"mov w21, #0xffc0",
"and w20, w20, #0xffc0",
"stp w20, w21, [x4, #24]",
"ubfx x20, x4, #0, #3",
"str x20, [x4, #512]"
]
},
"lfence": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /5",
"ExpectedArm64ASM": [
"dmb ld"
]
},
"xrstor [rax]": {
"ExpectedInstructionCount": 171,
"Comment": "GROUP15 0x0F 0xAE /5",
"ExpectedArm64ASM": [
"sub sp, sp, #0x40 (64)",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #0, #1",
"cbnz x20, #+0x8",
"b #+0x114",
"ldrh w20, [x4]",
"strh w20, [x28, #1200]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #1051]",
"ubfx w22, w20, #8, #1",
"ubfx w23, w20, #9, #1",
"ubfx w24, w20, #10, #1",
"ubfx w30, w20, #14, #1",
"ubfx w20, w20, #0, #1",
"strb w22, [x28, #1048]",
"strb w23, [x28, #1049]",
"strb w24, [x28, #1050]",
"strb w30, [x28, #1054]",
"strb w20, [x28, #1040]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1202]",
"mov x20, #0xffffffffffffffff",
"mov w22, #0xffff",
"fmov d2, x20",
"fmov v2.D[1], x22",
"ldr q3, [x4, #32]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x21, lsl #4",
"str q3, [x0, #1056]",
"add w20, w21, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #48]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #64]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #80]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #96]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #112]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #128]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #144]",
"and v2.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1056]",
"b #+0x4c",
"mov w20, #0x37f",
"strh w20, [x28, #1200]",
"strb wzr, [x28, #1051]",
"strb wzr, [x28, #1202]",
"strb wzr, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb wzr, [x28, #1050]",
"strb wzr, [x28, #1054]",
"strb wzr, [x28, #1040]",
"movi v2.2d, #0x0",
"str q2, [x28, #1056]",
"str q2, [x28, #1072]",
"str q2, [x28, #1088]",
"str q2, [x28, #1104]",
"str q2, [x28, #1120]",
"str q2, [x28, #1136]",
"str q2, [x28, #1152]",
"str q2, [x28, #1168]",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #1",
"cbnz x20, #+0x8",
"b #+0x28",
"ldp q16, q17, [x4, #160]",
"ldp q18, q19, [x4, #192]",
"ldp q20, q21, [x4, #224]",
"ldp q22, q23, [x4, #256]",
"ldp q24, q25, [x4, #288]",
"ldp q26, q27, [x4, #320]",
"ldp q28, q29, [x4, #352]",
"ldp q30, q31, [x4, #384]",
"b #+0x44",
"movi v31.2d, #0x0",
"mov v30.16b, v31.16b",
"mov v29.16b, v31.16b",
"mov v28.16b, v31.16b",
"mov v27.16b, v31.16b",
"mov v26.16b, v31.16b",
"mov v25.16b, v31.16b",
"mov v24.16b, v31.16b",
"mov v23.16b, v31.16b",
"mov v22.16b, v31.16b",
"mov v21.16b, v31.16b",
"mov v20.16b, v31.16b",
"mov v19.16b, v31.16b",
"mov v18.16b, v31.16b",
"mov v17.16b, v31.16b",
"mov v16.16b, v31.16b",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #2, #1",
"cbnz x20, #+0x8",
"b #+0x58",
"ldp q2, q3, [x4, #576]",
"ldp q4, q5, [x4, #608]",
"ldp q6, q7, [x4, #640]",
"ldp q8, q9, [x4, #672]",
"ldp q10, q11, [x4, #704]",
"ldp q12, q13, [x4, #736]",
"ldp q14, q15, [x4, #768]",
"str q2, [sp]",
"str q3, [sp, #32]",
"ldp q2, q3, [x4, #800]",
"stp q2, q3, [x28, #416]",
"stp q14, q15, [x28, #384]",
"stp q12, q13, [x28, #352]",
"stp q10, q11, [x28, #320]",
"stp q8, q9, [x28, #288]",
"stp q6, q7, [x28, #256]",
"stp q4, q5, [x28, #224]",
"ldr q2, [sp]",
"ldr q3, [sp, #32]",
"stp q2, q3, [x28, #192]",
"b #+0x28",
"movi v2.2d, #0x0",
"stp q2, q2, [x28, #416]",
"stp q2, q2, [x28, #384]",
"stp q2, q2, [x28, #352]",
"stp q2, q2, [x28, #320]",
"stp q2, q2, [x28, #288]",
"stp q2, q2, [x28, #256]",
"stp q2, q2, [x28, #224]",
"stp q2, q2, [x28, #192]",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #2",
"cbnz x20, #+0x8",
"b #+0x34",
"ldr w20, [x4, #24]",
"and w20, w20, #0xffc0",
"str w20, [x28, #972]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x21, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0",
"b #+0x4",
"add sp, sp, #0x40 (64)"
]
},
"mfence": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /6",
"ExpectedArm64ASM": [
"dmb sy"
]
},
"clwb [rax]": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /6",
"ExpectedArm64ASM": [
"dc cvac, x4"
]
},
"sfence": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /7",
"ExpectedArm64ASM": [
"dmb st"
]
},
"clflush [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP15 0x0F 0xAE /7",
"ExpectedArm64ASM": [
"dc civac, x4",
"dsb ish"
]
},
"clflushopt [rax]": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /7",
"ExpectedArm64ASM": [
"dc civac, x4"
]
},
"prefetchnta [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"GROUP16 0x0F 0x18 /0"
],
"ExpectedArm64ASM": [
"prfm pldl1strm, [x4]"
]
},
"prefetcht0 [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"GROUP16 0x0F 0x18 /1"
],
"ExpectedArm64ASM": [
"prfm pldl1keep, [x4]"
]
},
"prefetcht1 [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"GROUP16 0x0F 0x18 /2"
],
"ExpectedArm64ASM": [
"prfm pldl2keep, [x4]"
]
},
"prefetcht2 [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"GROUP16 0x0F 0x18 /3"
],
"ExpectedArm64ASM": [
"prfm pldl3keep, [x4]"
]
},
"db 0x0f, 0x18, 0x20;": {
"ExpectedInstructionCount": 0,
"Comment": [
"GROUP16 0x0F 0x18 /4",
"nop dword [rax]",
"NOP implementation"
],
"ExpectedArm64ASM": []
},
"db 0x0f, 0x0d, 0x00": {
"ExpectedInstructionCount": 1,
"Comment": [
"GROUPP 0x0F 0x0D /0",
"prefetch_exclusive [rax]"
],
"ExpectedArm64ASM": [
"prfm pldl1keep, [x4]"
]
},
"prefetchw [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"GROUPP 0x0F 0x0D /1"
],
"ExpectedArm64ASM": [
"prfm pstl1keep, [x4]"
]
},
"prefetchwt1 [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"GROUPP 0x0F 0x0D /2"
],
"ExpectedArm64ASM": [
"prfm pstl1keep, [x4]"
]
}
}
}
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