diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 56e083031..6cf764f45 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -3249,9 +3249,10 @@ void OpDispatchBuilder::RestoreX87State(Ref MemBase) { auto NewFCW = _LoadMemGPR(OpSize::i16Bit, MemBase, OpSize::i16Bit); _StoreContextGPR(OpSize::i16Bit, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); + Ref Top {}; { auto NewFSW = _LoadMemGPR(OpSize::i16Bit, MemBase, Constant(2), OpSize::i16Bit, MemOffsetType::SXTX, 1); - ReconstructX87StateFromFSW_Helper(NewFSW); + Top = ReconstructX87StateFromFSW_Helper(NewFSW); } { @@ -3260,10 +3261,21 @@ void OpDispatchBuilder::RestoreX87State(Ref MemBase) { _StoreContextGPR(OpSize::i8Bit, NewFTW, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); } - for (uint32_t i = 0; i < Core::CPUState::NUM_MMS; i += 2) { - auto MMRegs = LoadMemPairFPR(OpSize::i128Bit, MemBase, i * 16 + 32); - _StoreContextFPR(OpSize::i128Bit, MMRegs.Low, MMBaseOffset() + i * 16); - _StoreContextFPR(OpSize::i128Bit, MMRegs.High, MMBaseOffset() + (i + 1) * 16); + auto SevenConst = Constant(7); + auto low = Constant(~0ULL); + auto high = Constant(0xFFFF); + Ref Mask = _VLoadTwoGPRs(low, high); + const auto StoreSize = ReducedPrecisionMode ? OpSize::i64Bit : OpSize::i128Bit; + for (uint32_t i = 0; i < Core::CPUState::NUM_MMS; ++i) { + Ref Reg = _LoadMemFPR(OpSize::i128Bit, MemBase, Constant(16 * i + 32), OpSize::i8Bit, MemOffsetType::SXTX, 1); + // Mask off the top bits + Reg = _VAnd(OpSize::i128Bit, Reg, Mask); + if (ReducedPrecisionMode) { + // Convert to double precision + Reg = _F80CVT(OpSize::i64Bit, Reg); + } + _StoreContextFPRIndexed(Reg, Top, StoreSize, MMBaseOffset(), IR::OpSizeToSize(OpSize::i128Bit)); + Top = _And(OpSize::i32Bit, Add(OpSize::i32Bit, Top, 1), SevenConst); } } diff --git a/FEXCore/include/FEXCore/Core/DiskCache.h b/FEXCore/include/FEXCore/Core/DiskCache.h index 88b84bb36..99fc830cc 100644 --- a/FEXCore/include/FEXCore/Core/DiskCache.h +++ b/FEXCore/include/FEXCore/Core/DiskCache.h @@ -223,7 +223,7 @@ namespace DiskCache { // TODO: This header is in global installed header path, but uses internal headers. // Migrate this once that is fixed. - static constexpr uint16_t FormatVersion = 23; + static constexpr uint16_t FormatVersion = 24; FEX_DEFAULT_VISIBILITY uint16_t GetFormatVersion(); } // namespace DiskCache diff --git a/unittests/ASM/FEX_bugs/x87_fxrstor_stack.asm b/unittests/ASM/FEX_bugs/x87_fxrstor_stack.asm new file mode 100644 index 000000000..f5207fee2 --- /dev/null +++ b/unittests/ASM/FEX_bugs/x87_fxrstor_stack.asm @@ -0,0 +1,115 @@ +%ifdef CONFIG +{ + "RegData": { + "XMM0": ["0xb9533de8ad0967d2", "0xb615"], + "XMM1": ["0x30ae762c30b556de", "0x9af3"], + "XMM2": ["0xe86b2b5774313a97", "0x1f6d"], + "XMM3": ["0x48510f254d2fa47f", "0x4886"], + "XMM4": ["0", "0"], + "XMM5": ["0x782366128a6789f2", "0xf881"], + "XMM6": ["0xa56724426b4c72f1", "0xd415"], + "XMM7": ["0xb76472a37404b890", "0x10ad"], + "MM7": ["0x48510f254d2fa47f", "0x4886"], + "MM6": ["0xe86b2b5774313a97", "0x1f6d"], + "MM5": ["0x30ae762c30b556de", "0x9af3"], + "MM4": ["0xb9533de8ad0967d2", "0xb615"], + "MM3": ["0xb76472a37404b890", "0x10ad"], + "MM2": ["0xa56724426b4c72f1", "0xd415"], + "MM1": ["0x782366128a6789f2", "0xf881"], + "MM0": ["0", "0"] + } +} +%endif + +; FEX had a bug where fxrstor wasn't restoring x87 registers in the correct order. + +; Init x87 +fninit + +; Load registers with zero +times 8 fldz + +; Empty them +times 8 ffreep st0 + +; Load seven of them with random data +fld tword [rel .random_data + (0 * 10)] +fld tword [rel .random_data + (1 * 10)] +fld tword [rel .random_data + (2 * 10)] +fld tword [rel .random_data + (3 * 10)] +fld tword [rel .random_data + (4 * 10)] +fld tword [rel .random_data + (5 * 10)] +fld tword [rel .random_data + (6 * 10)] + +; Rotate the stack a couple of times +fincstp +fincstp +fincstp + +; Save the data +fxsave [rel .save_data] + +; Init x87 +fninit + +; Load registers with zero +times 8 fldz + +; Empty them +times 8 ffreep st0 + +; Rotate the stack a couple of times +fincstp +fincstp + +; Restore the data +fxrstor [rel .save_data] + +; Load the x87 register data in to vectors for testing. +movups xmm0, [rel .save_data + 0x20 + (0 * 16)] +movups xmm1, [rel .save_data + 0x20 + (1 * 16)] +movups xmm2, [rel .save_data + 0x20 + (2 * 16)] +movups xmm3, [rel .save_data + 0x20 + (3 * 16)] +movups xmm4, [rel .save_data + 0x20 + (4 * 16)] +movups xmm5, [rel .save_data + 0x20 + (5 * 16)] +movups xmm6, [rel .save_data + 0x20 + (6 * 16)] +movups xmm7, [rel .save_data + 0x20 + (7 * 16)] +pand xmm0, [rel .x87_mask] +pand xmm1, [rel .x87_mask] +pand xmm2, [rel .x87_mask] +pand xmm3, [rel .x87_mask] +pand xmm4, [rel .x87_mask] +pand xmm5, [rel .x87_mask] +pand xmm6, [rel .x87_mask] +pand xmm7, [rel .x87_mask] + + + +hlt + +align 4096 +.save_data: +times 64 dq 0 + +.x87_mask: +dq 0xffff_ffff_ffff_ffff, 0xffff + +align 16 +; 256bytes of random data +.random_data: +db 0x7f, 0xa4, 0x2f, 0x4d, 0x25, 0x0f, 0x51, 0x48, 0x86, 0x48, 0x97, 0x3a, 0x31, 0x74, 0x57, 0x2b +db 0x6b, 0xe8, 0x6d, 0x1f, 0xde, 0x56, 0xb5, 0x30, 0x2c, 0x76, 0xae, 0x30, 0xf3, 0x9a, 0xd2, 0x67 +db 0x09, 0xad, 0xe8, 0x3d, 0x53, 0xb9, 0x15, 0xb6, 0x90, 0xb8, 0x04, 0x74, 0xa3, 0x72, 0x64, 0xb7 +db 0xad, 0x10, 0xf1, 0x72, 0x4c, 0x6b, 0x42, 0x24, 0x67, 0xa5, 0x15, 0xd4, 0xf2, 0x89, 0x67, 0x8a +db 0x12, 0x66, 0x23, 0x78, 0x81, 0xf8, 0x96, 0x89, 0xa9, 0xa2, 0x3c, 0x3d, 0x82, 0x6b, 0xa2, 0x19 +db 0xb0, 0x12, 0x97, 0x68, 0xab, 0x58, 0xf6, 0x00, 0x72, 0x19, 0xd2, 0x1e, 0x03, 0x9d, 0x7d, 0xc9 +db 0xc8, 0x55, 0xdf, 0x98, 0x22, 0x43, 0x86, 0x1c, 0xcc, 0xe9, 0x1b, 0x89, 0xda, 0xfe, 0x9b, 0xb2 +db 0x47, 0x21, 0x0f, 0x71, 0x28, 0xbd, 0xb0, 0x88, 0x38, 0xac, 0xb5, 0x7f, 0x88, 0x5e, 0xe9, 0xc4 +db 0xe4, 0x5b, 0x3e, 0xd0, 0x2a, 0x8c, 0xdf, 0xa7, 0xea, 0x95, 0xd3, 0xc2, 0xee, 0xd1, 0x70, 0x6c +db 0x18, 0x77, 0xc1, 0x38, 0x7b, 0xfc, 0xa9, 0x58, 0x92, 0xe8, 0xc6, 0xcd, 0x07, 0x5d, 0x3d, 0x76 +db 0xf4, 0x4c, 0x5b, 0x25, 0x7f, 0x9b, 0x02, 0x41, 0x78, 0x39, 0x9e, 0x3e, 0x4c, 0xa2, 0x79, 0xca +db 0x1c, 0xe9, 0xf2, 0x9a, 0xaf, 0x6d, 0xfa, 0x57, 0x10, 0xc7, 0xfd, 0x5f, 0x20, 0x80, 0xf5, 0x65 +db 0x3c, 0x77, 0xfb, 0xa8, 0xdf, 0x94, 0x16, 0x4f, 0xc0, 0x78, 0x00, 0x76, 0x03, 0x8c, 0x82, 0x10 +db 0x7f, 0x07, 0xe0, 0x02, 0x92, 0xbb, 0xf9, 0x2e, 0xfa, 0x3d, 0x88, 0xc8, 0x24, 0x27, 0xa6, 0x1e +db 0x04, 0x90, 0xf6, 0xf8, 0x76, 0x0a, 0x4c, 0x94, 0xbc, 0xb7, 0x8d, 0x8b, 0xf9, 0x65, 0xf5, 0x07 +db 0x7f, 0xc1, 0x37, 0x78, 0xa1, 0x1f, 0xc4, 0x10, 0x6c, 0x29, 0x5e, 0x7e, 0x32, 0x24, 0x92, 0x09 diff --git a/unittests/InstructionCountCI/AFP/H0F3A.json b/unittests/InstructionCountCI/AFP/H0F3A.json index 861176fb5..05b2eef9f 100644 --- a/unittests/InstructionCountCI/AFP/H0F3A.json +++ b/unittests/InstructionCountCI/AFP/H0F3A.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "roundss xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json index 53138a298..2ee6828d8 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "cvtpi2ps xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json index 51cf1d728..f10fb6fd5 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "RPRES" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "cvtsi2ss xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json index c889e990f..8af82c7ac 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "cvtsi2sd xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/Secondary.json b/unittests/InstructionCountCI/AFP/Secondary.json index daa4eae42..2dd20bf9a 100644 --- a/unittests/InstructionCountCI/AFP/Secondary.json +++ b/unittests/InstructionCountCI/AFP/Secondary.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "cvtpi2ps xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/AFP/Secondary_REP.json b/unittests/InstructionCountCI/AFP/Secondary_REP.json index 8215c8f29..6c2c7b7a8 100644 --- a/unittests/InstructionCountCI/AFP/Secondary_REP.json +++ b/unittests/InstructionCountCI/AFP/Secondary_REP.json @@ -9,7 +9,7 @@ "SVE256", "RPRES" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "cvtsi2ss xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json index 7b9581069..6c4b88021 100644 --- a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "cvtsi2sd xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/VEX_map1.json b/unittests/InstructionCountCI/AFP/VEX_map1.json index 8d1dcaa7a..f46104fc1 100644 --- a/unittests/InstructionCountCI/AFP/VEX_map1.json +++ b/unittests/InstructionCountCI/AFP/VEX_map1.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "RPRES" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vsqrtss xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AFP/VEX_map3.json b/unittests/InstructionCountCI/AFP/VEX_map3.json index b1e051f6b..39742fc75 100644 --- a/unittests/InstructionCountCI/AFP/VEX_map3.json +++ b/unittests/InstructionCountCI/AFP/VEX_map3.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vroundss xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/AVX128/FMA4.json b/unittests/InstructionCountCI/AVX128/FMA4.json index 13dfaeba9..df2f4d3f5 100644 --- a/unittests/InstructionCountCI/AVX128/FMA4.json +++ b/unittests/InstructionCountCI/AVX128/FMA4.json @@ -7,7 +7,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vfmaddsubps xmm0, xmm1, xmm2, xmm3": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json index c5a2937c3..6d443fdae 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json @@ -13,7 +13,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vmovups xmm0, xmm0": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json b/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json index 4cf6f1c4c..f82eae33b 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vaddsubpd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json index 66f492acd..3b98a5f52 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json @@ -10,7 +10,7 @@ "FLAGM2", "SVE256" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vmovntps [rax], xmm0": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json index 5611c3562..508106952 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json @@ -10,7 +10,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vucomiss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json index 9e80af38c..13ab1d0c3 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json @@ -11,7 +11,7 @@ "I8MM", "DOTPROD" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vpshufb xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json b/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json index 1e9c78f24..c5c160db0 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json @@ -8,7 +8,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vfmadd132ss xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json b/unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json index 78ee5f870..d828acc57 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json @@ -12,7 +12,7 @@ "SVE256", "I8MM" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vpdpbusd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json b/unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json index b552c50b1..29f64d06d 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json @@ -11,7 +11,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vpdpbusd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json index 70539e2bd..3022de827 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json @@ -10,7 +10,7 @@ "FLAGM2", "SVE256" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vmovntdqa xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json index b5c63dc72..fa066b329 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json @@ -11,7 +11,7 @@ "SVE256", "SVEBITPERM" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vtestps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3.json b/unittests/InstructionCountCI/AVX128/VEX_map3.json index 0e0b57970..4e36db210 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map3.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map3.json @@ -7,7 +7,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vpermq ymm0, ymm1, 1": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json index 46f56dfa3..af8d604a1 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json @@ -8,7 +8,7 @@ "AFP", "SVE256" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vblendvps xmm0, xmm1, xmm2, xmm3": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map_group.json b/unittests/InstructionCountCI/AVX128/VEX_map_group.json index 85b2d5d76..8de6f0dff 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map_group.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map_group.json @@ -9,7 +9,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vpsrlw xmm0, xmm1, 0": { diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json index 817106e07..1465a1546 100644 --- a/unittests/InstructionCountCI/Atomics.json +++ b/unittests/InstructionCountCI/Atomics.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "lock add byte [rax], cl": { diff --git a/unittests/InstructionCountCI/Crypto/H0F38.json b/unittests/InstructionCountCI/Crypto/H0F38.json index a1867553b..ea1d02f62 100644 --- a/unittests/InstructionCountCI/Crypto/H0F38.json +++ b/unittests/InstructionCountCI/Crypto/H0F38.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "sha1nexte xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json b/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json index a574047ec..7eefa34fe 100644 --- a/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json +++ b/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "sha1nexte xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json index 0200714a3..9b6ff373d 100644 --- a/unittests/InstructionCountCI/Crypto/H0F3A.json +++ b/unittests/InstructionCountCI/Crypto/H0F3A.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "pclmulqdq xmm0, xmm1, 00000b": { diff --git a/unittests/InstructionCountCI/DDD.json b/unittests/InstructionCountCI/DDD.json index 5c3ea04f8..81eed20bd 100644 --- a/unittests/InstructionCountCI/DDD.json +++ b/unittests/InstructionCountCI/DDD.json @@ -10,7 +10,7 @@ "AFP", "RPRES" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Comment": [ "These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers", diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json index 7998f8aa5..e6998eb48 100644 --- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json +++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json @@ -8,7 +8,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Comment": [ "Instructions that explicitly push against the limits of ARM's loadstore instructions" diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json index fb21370ec..8ac80e8df 100644 --- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json +++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json @@ -8,7 +8,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Comment": [ "Instructions that explicitly push against the limits of ARM's loadstore instructions" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst.json b/unittests/InstructionCountCI/FEXOpt/MultiInst.json index 5ff1893da..42be1e2f3 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst.json @@ -13,7 +13,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json index be2e2864c..511f359d5 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json @@ -11,7 +11,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json index 3e3dda4d2..40430638a 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json @@ -9,7 +9,7 @@ "SVE256", "RPRES" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json index 9f626d493..1c76b79bb 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json @@ -14,7 +14,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json index 0515c613b..1a5a32103 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json @@ -14,7 +14,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/libnss.json b/unittests/InstructionCountCI/FEXOpt/libnss.json index 2e5353148..f838ed4cd 100644 --- a/unittests/InstructionCountCI/FEXOpt/libnss.json +++ b/unittests/InstructionCountCI/FEXOpt/libnss.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Comment": [], "Instructions": { diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json index 4ba57e777..f649c8623 100644 --- a/unittests/InstructionCountCI/FlagM/Atomics.json +++ b/unittests/InstructionCountCI/FlagM/Atomics.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "lock add byte [rax], cl": { diff --git a/unittests/InstructionCountCI/FlagM/FlagOpts.json b/unittests/InstructionCountCI/FlagM/FlagOpts.json index 73563b444..6d0352163 100644 --- a/unittests/InstructionCountCI/FlagM/FlagOpts.json +++ b/unittests/InstructionCountCI/FlagM/FlagOpts.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "Chained add": { diff --git a/unittests/InstructionCountCI/FlagM/H0F38.json b/unittests/InstructionCountCI/FlagM/H0F38.json index a374da336..440a4741f 100644 --- a/unittests/InstructionCountCI/FlagM/H0F38.json +++ b/unittests/InstructionCountCI/FlagM/H0F38.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "ptest xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json index e08d85b31..cbcafb723 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "The Witcher 3": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json index 89404f2d1..5ebd9a774 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "Sonic Mania movie player": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json index b31fd46c0..8b86dc0e0 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json @@ -10,7 +10,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "FMOD scalar loop": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json index 51f68b7ad..dd24b8ff4 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "The Sims 1 hot block": { diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index 77a132589..6a2880af9 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "add bl, cl": { diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index f64d6ba1d..3943e52f2 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "add al, 1": { diff --git a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json index 41c905339..935b7d089 100644 --- a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "push es": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index 61491a922..35f882a42 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -11,7 +11,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "ucomiss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json index d4db03717..51e472990 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json @@ -11,7 +11,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "sgdt [rax]": { @@ -1364,7 +1364,7 @@ ] }, "fxrstor [rax]": { - "ExpectedInstructionCount": 48, + "ExpectedInstructionCount": 86, "Comment": "GROUP15 0x0F 0xAE /1", "ExpectedArm64ASM": [ "ldrh w20, [x4]", @@ -1372,30 +1372,68 @@ "ldrh w20, [x4, #2]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #1051]", - "ubfx w21, w20, #8, #1", - "ubfx w22, w20, #9, #1", - "ubfx w23, w20, #10, #1", - "ubfx w24, w20, #14, #1", + "ubfx w22, w20, #8, #1", + "ubfx w23, w20, #9, #1", + "ubfx w24, w20, #10, #1", + "ubfx w30, w20, #14, #1", "ubfx w20, w20, #0, #1", - "strb w21, [x28, #1048]", - "strb w22, [x28, #1049]", - "strb w23, [x28, #1050]", - "strb w24, [x28, #1054]", + "strb w22, [x28, #1048]", + "strb w23, [x28, #1049]", + "strb w24, [x28, #1050]", + "strb w30, [x28, #1054]", "strb w20, [x28, #1040]", "ldrb w20, [x4, #4]", "strb w20, [x28, #1202]", - "ldp q2, q3, [x4, #32]", - "str q2, [x28, #1056]", - "str q3, [x28, #1072]", - "ldp q2, q3, [x4, #64]", - "str q2, [x28, #1088]", - "str q3, [x28, #1104]", - "ldp q2, q3, [x4, #96]", - "str q2, [x28, #1120]", - "str q3, [x28, #1136]", - "ldp q2, q3, [x4, #128]", - "str q2, [x28, #1152]", - "str q3, [x28, #1168]", + "mov x20, #0xffffffffffffffff", + "mov w22, #0xffff", + "fmov d2, x20", + "fmov v2.D[1], x22", + "ldr q3, [x4, #32]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x21, lsl #4", + "str q3, [x0, #1056]", + "add w20, w21, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #48]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #64]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #80]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #96]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #112]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #128]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #144]", + "and v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1056]", "ldp q16, q17, [x4, #160]", "ldp q18, q19, [x4, #192]", "ldp q20, q21, [x4, #224]", @@ -1703,43 +1741,81 @@ ] }, "xrstor [rax]": { - "ExpectedInstructionCount": 133, + "ExpectedInstructionCount": 171, "Comment": "GROUP15 0x0F 0xAE /5", "ExpectedArm64ASM": [ "sub sp, sp, #0x40 (64)", "ldr x20, [x4, #512]", "ubfx x20, x20, #0, #1", "cbnz x20, #+0x8", - "b #+0x7c", + "b #+0x114", "ldrh w20, [x4]", "strh w20, [x28, #1200]", "ldrh w20, [x4, #2]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #1051]", - "ubfx w21, w20, #8, #1", - "ubfx w22, w20, #9, #1", - "ubfx w23, w20, #10, #1", - "ubfx w24, w20, #14, #1", + "ubfx w22, w20, #8, #1", + "ubfx w23, w20, #9, #1", + "ubfx w24, w20, #10, #1", + "ubfx w30, w20, #14, #1", "ubfx w20, w20, #0, #1", - "strb w21, [x28, #1048]", - "strb w22, [x28, #1049]", - "strb w23, [x28, #1050]", - "strb w24, [x28, #1054]", + "strb w22, [x28, #1048]", + "strb w23, [x28, #1049]", + "strb w24, [x28, #1050]", + "strb w30, [x28, #1054]", "strb w20, [x28, #1040]", "ldrb w20, [x4, #4]", "strb w20, [x28, #1202]", - "ldp q2, q3, [x4, #32]", - "str q2, [x28, #1056]", - "str q3, [x28, #1072]", - "ldp q2, q3, [x4, #64]", - "str q2, [x28, #1088]", - "str q3, [x28, #1104]", - "ldp q2, q3, [x4, #96]", - "str q2, [x28, #1120]", - "str q3, [x28, #1136]", - "ldp q2, q3, [x4, #128]", - "str q2, [x28, #1152]", - "str q3, [x28, #1168]", + "mov x20, #0xffffffffffffffff", + "mov w22, #0xffff", + "fmov d2, x20", + "fmov v2.D[1], x22", + "ldr q3, [x4, #32]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x21, lsl #4", + "str q3, [x0, #1056]", + "add w20, w21, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #48]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #64]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #80]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #96]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #112]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #128]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #144]", + "and v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1056]", "b #+0x4c", "mov w20, #0x37f", "strh w20, [x28, #1200]", diff --git a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json index cde34eaa9..74016e414 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json @@ -11,7 +11,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "xgetbv": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json index b05cc9f31..27f783edd 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json @@ -11,7 +11,7 @@ "AFP", "FCMA" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "ucomisd xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP.json b/unittests/InstructionCountCI/FlagM/Secondary_REP.json index a3d424690..0c3263595 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_REP.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_REP.json @@ -12,7 +12,7 @@ "AFP", "CSSC" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "popcnt ax, bx": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json b/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json index dbf9b57dc..4acf40641 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "popcnt ax, bx": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json index 4750a3d76..d3b2a9ada 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map1.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vucomiss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map2.json b/unittests/InstructionCountCI/FlagM/VEX_map2.json index c734eaa45..c02af6a6d 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map2.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map2.json @@ -10,7 +10,7 @@ "AFP", "SVEBITPERM" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vtestps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map_group.json b/unittests/InstructionCountCI/FlagM/VEX_map_group.json index 4ae460bd6..b4140e877 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map_group.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map_group.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "blsr eax, ebx": { diff --git a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json index 8fceede69..f66d2dcce 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json +++ b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json index 6a68ae350..3b15bf753 100644 --- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json index 6c721aa42..54242c441 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json index 32a5028f2..7c89719a7 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index 656ea8b4e..d944d509e 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -11,7 +11,7 @@ "CSSC", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "fadd dword [rax]": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json index d1c759a17..6211e2086 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json index e927a1988..5a02b2d0b 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json index 133f99b3e..420a8baa7 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json index aadbdd9aa..5d3021716 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index 8ddfd0750..6858331c3 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "fadd dword [rax]": { diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index 00a75f4d6..a5c84c508 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -10,7 +10,7 @@ "FLAGM2", "CRYPTO" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "pshufb mm0, mm1": { diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index 99a4226e3..90cb108f4 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -8,7 +8,7 @@ "AFP", "CRYPTO" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Comment": [ "SSE4.2 string instructions are skipped here.", diff --git a/unittests/InstructionCountCI/H0F3A_SVE128.json b/unittests/InstructionCountCI/H0F3A_SVE128.json index afc48a22d..b975aea8f 100644 --- a/unittests/InstructionCountCI/H0F3A_SVE128.json +++ b/unittests/InstructionCountCI/H0F3A_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "dpps xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/MOPS/Primary.json b/unittests/InstructionCountCI/MOPS/Primary.json index 517cb1b38..052821c94 100644 --- a/unittests/InstructionCountCI/MOPS/Primary.json +++ b/unittests/InstructionCountCI/MOPS/Primary.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "rep movsb": { diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index a886181d2..b9bc6ac26 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -10,7 +10,7 @@ "FLAGM2", "MOPS" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "add bl, cl": { diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index e547f4929..fa7d8cc91 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Comment": [ "Instructions in this table that are marked optimal don't have their flag calculation part of this assumption", diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index ef85ab6c0..02db907a2 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -9,7 +9,7 @@ "FlagM", "FlagM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "push es": { diff --git a/unittests/InstructionCountCI/RPRES/DDD.json b/unittests/InstructionCountCI/RPRES/DDD.json index e37904a73..00b1867ef 100644 --- a/unittests/InstructionCountCI/RPRES/DDD.json +++ b/unittests/InstructionCountCI/RPRES/DDD.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "pfrcpv mm0, mm1": { diff --git a/unittests/InstructionCountCI/RPRES/Secondary.json b/unittests/InstructionCountCI/RPRES/Secondary.json index 419f536b4..5d2c81180 100644 --- a/unittests/InstructionCountCI/RPRES/Secondary.json +++ b/unittests/InstructionCountCI/RPRES/Secondary.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "rsqrtps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json index f7b2eb025..f6826b1e4 100644 --- a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json +++ b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "rsqrtss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json index 78c4842f2..433f63012 100644 --- a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json +++ b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json @@ -8,7 +8,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vrsqrtps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Repeat.json b/unittests/InstructionCountCI/Repeat.json index 27a7c125f..cbf5a50fa 100644 --- a/unittests/InstructionCountCI/Repeat.json +++ b/unittests/InstructionCountCI/Repeat.json @@ -6,7 +6,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": {} } diff --git a/unittests/InstructionCountCI/SSE42_Strings.json b/unittests/InstructionCountCI/SSE42_Strings.json index 78c48f124..eb516e2bd 100644 --- a/unittests/InstructionCountCI/SSE42_Strings.json +++ b/unittests/InstructionCountCI/SSE42_Strings.json @@ -33,7 +33,7 @@ " - 1b: ECX = MSB", "[7] - Reserved" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "pcmpestrm xmm0, xmm1, 0_0_00_00_00b": { diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 128858327..8d09e7e29 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Comment": [ "MMX instructions are defined as optimal without SRA being used for these instructions.", diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index 1c508fd3b..63c7fd5e7 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "sgdt [rax]": { @@ -1636,7 +1636,7 @@ ] }, "fxrstor [rax]": { - "ExpectedInstructionCount": 48, + "ExpectedInstructionCount": 86, "Comment": "GROUP15 0x0F 0xAE /1", "ExpectedArm64ASM": [ "ldrh w20, [x4]", @@ -1644,30 +1644,68 @@ "ldrh w20, [x4, #2]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #1051]", - "ubfx w21, w20, #8, #1", - "ubfx w22, w20, #9, #1", - "ubfx w23, w20, #10, #1", - "ubfx w24, w20, #14, #1", + "ubfx w22, w20, #8, #1", + "ubfx w23, w20, #9, #1", + "ubfx w24, w20, #10, #1", + "ubfx w30, w20, #14, #1", "ubfx w20, w20, #0, #1", - "strb w21, [x28, #1048]", - "strb w22, [x28, #1049]", - "strb w23, [x28, #1050]", - "strb w24, [x28, #1054]", + "strb w22, [x28, #1048]", + "strb w23, [x28, #1049]", + "strb w24, [x28, #1050]", + "strb w30, [x28, #1054]", "strb w20, [x28, #1040]", "ldrb w20, [x4, #4]", "strb w20, [x28, #1202]", - "ldp q2, q3, [x4, #32]", - "str q2, [x28, #1056]", - "str q3, [x28, #1072]", - "ldp q2, q3, [x4, #64]", - "str q2, [x28, #1088]", - "str q3, [x28, #1104]", - "ldp q2, q3, [x4, #96]", - "str q2, [x28, #1120]", - "str q3, [x28, #1136]", - "ldp q2, q3, [x4, #128]", - "str q2, [x28, #1152]", - "str q3, [x28, #1168]", + "mov x20, #0xffffffffffffffff", + "mov w22, #0xffff", + "fmov d2, x20", + "fmov v2.D[1], x22", + "ldr q3, [x4, #32]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x21, lsl #4", + "str q3, [x0, #1056]", + "add w20, w21, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #48]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #64]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #80]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #96]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #112]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #128]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #144]", + "and v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1056]", "ldp q16, q17, [x4, #160]", "ldp q18, q19, [x4, #192]", "ldp q20, q21, [x4, #224]", @@ -1871,43 +1909,81 @@ ] }, "xrstor [rax]": { - "ExpectedInstructionCount": 133, + "ExpectedInstructionCount": 171, "Comment": "GROUP15 0x0F 0xAE /5", "ExpectedArm64ASM": [ "sub sp, sp, #0x40 (64)", "ldr x20, [x4, #512]", "ubfx x20, x20, #0, #1", "cbnz x20, #+0x8", - "b #+0x7c", + "b #+0x114", "ldrh w20, [x4]", "strh w20, [x28, #1200]", "ldrh w20, [x4, #2]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #1051]", - "ubfx w21, w20, #8, #1", - "ubfx w22, w20, #9, #1", - "ubfx w23, w20, #10, #1", - "ubfx w24, w20, #14, #1", + "ubfx w22, w20, #8, #1", + "ubfx w23, w20, #9, #1", + "ubfx w24, w20, #10, #1", + "ubfx w30, w20, #14, #1", "ubfx w20, w20, #0, #1", - "strb w21, [x28, #1048]", - "strb w22, [x28, #1049]", - "strb w23, [x28, #1050]", - "strb w24, [x28, #1054]", + "strb w22, [x28, #1048]", + "strb w23, [x28, #1049]", + "strb w24, [x28, #1050]", + "strb w30, [x28, #1054]", "strb w20, [x28, #1040]", "ldrb w20, [x4, #4]", "strb w20, [x28, #1202]", - "ldp q2, q3, [x4, #32]", - "str q2, [x28, #1056]", - "str q3, [x28, #1072]", - "ldp q2, q3, [x4, #64]", - "str q2, [x28, #1088]", - "str q3, [x28, #1104]", - "ldp q2, q3, [x4, #96]", - "str q2, [x28, #1120]", - "str q3, [x28, #1136]", - "ldp q2, q3, [x4, #128]", - "str q2, [x28, #1152]", - "str q3, [x28, #1168]", + "mov x20, #0xffffffffffffffff", + "mov w22, #0xffff", + "fmov d2, x20", + "fmov v2.D[1], x22", + "ldr q3, [x4, #32]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x21, lsl #4", + "str q3, [x0, #1056]", + "add w20, w21, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #48]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #64]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #80]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #96]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #112]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #128]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1056]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldr q3, [x4, #144]", + "and v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1056]", "b #+0x4c", "mov w20, #0x37f", "strh w20, [x28, #1200]", diff --git a/unittests/InstructionCountCI/SecondaryModRM.json b/unittests/InstructionCountCI/SecondaryModRM.json index a733e4c41..4fa1f8da4 100644 --- a/unittests/InstructionCountCI/SecondaryModRM.json +++ b/unittests/InstructionCountCI/SecondaryModRM.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "xgetbv": { diff --git a/unittests/InstructionCountCI/Secondary_32Bit.json b/unittests/InstructionCountCI/Secondary_32Bit.json index 7dec6d0ab..bfeb9cb91 100644 --- a/unittests/InstructionCountCI/Secondary_32Bit.json +++ b/unittests/InstructionCountCI/Secondary_32Bit.json @@ -7,7 +7,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "push fs": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index 2e613f705..02092e33b 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "movupd xmm0, xmm0": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json index f604ca73b..107ef387a 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "addsubpd xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json index 76bcd32df..ebd8554e2 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "psrlw xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json index 612704dab..a7f98e717 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "pmulhuw xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 18fc4fe1d..94c644003 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -12,7 +12,7 @@ "FRINTTS", "CSSC" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "movss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index 31ee12c96..03f4a21c2 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -10,7 +10,7 @@ "FCMA", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "movsd xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json index 93641f01d..3436cde9f 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json +++ b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "addsubps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json index ad5293759..02246c0c9 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json @@ -10,7 +10,7 @@ "FCMA", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "cvtpd2dq xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json b/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json index 4c875bb4f..e8e27af5c 100644 --- a/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json +++ b/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "cvttss2si eax, xmm0": { diff --git a/unittests/InstructionCountCI/Secondary_SVE128.json b/unittests/InstructionCountCI/Secondary_SVE128.json index 88cc8e370..5cc438d91 100644 --- a/unittests/InstructionCountCI/Secondary_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "movmskps eax, xmm0": { diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 0460d8d95..3ee41030f 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -13,7 +13,7 @@ "FLAGM2", "FRINTTS" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vmovups xmm0, xmm0": { diff --git a/unittests/InstructionCountCI/VEX_map1_FCMA.json b/unittests/InstructionCountCI/VEX_map1_FCMA.json index b68736c44..a308e4bd0 100644 --- a/unittests/InstructionCountCI/VEX_map1_FCMA.json +++ b/unittests/InstructionCountCI/VEX_map1_FCMA.json @@ -8,7 +8,7 @@ "FCMA" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vaddsubpd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json index 639e6c050..1550265ac 100644 --- a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json +++ b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json @@ -13,7 +13,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vcvttss2si eax, xmm0": { diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index f4703dbb8..d572b4460 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -13,7 +13,7 @@ "I8MM", "DOTPROD" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vpshufb xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map2_DOTPROD.json b/unittests/InstructionCountCI/VEX_map2_DOTPROD.json index 7a8f445bc..c53e4e38e 100644 --- a/unittests/InstructionCountCI/VEX_map2_DOTPROD.json +++ b/unittests/InstructionCountCI/VEX_map2_DOTPROD.json @@ -13,7 +13,7 @@ "SVEBITPERM", "I8MM" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vpdpbusd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map2_I8MM.json b/unittests/InstructionCountCI/VEX_map2_I8MM.json index e6240de8d..3b97e4a93 100644 --- a/unittests/InstructionCountCI/VEX_map2_I8MM.json +++ b/unittests/InstructionCountCI/VEX_map2_I8MM.json @@ -12,7 +12,7 @@ "FLAGM2", "SVEBITPERM" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vpdpbusd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map2_svebitperm.json b/unittests/InstructionCountCI/VEX_map2_svebitperm.json index a95496e8f..af9a3b73e 100644 --- a/unittests/InstructionCountCI/VEX_map2_svebitperm.json +++ b/unittests/InstructionCountCI/VEX_map2_svebitperm.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "pext eax, ebx, ecx": { diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 30fd3f9ed..18ed03c2c 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -8,7 +8,7 @@ "DisabledHostFeatures": [ "AFP" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vpermq ymm0, ymm1, 1": { diff --git a/unittests/InstructionCountCI/VEX_map_group.json b/unittests/InstructionCountCI/VEX_map_group.json index 0ee0ac0f1..9562fa2ae 100644 --- a/unittests/InstructionCountCI/VEX_map_group.json +++ b/unittests/InstructionCountCI/VEX_map_group.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "vpsrlw xmm0, xmm1, 0": { diff --git a/unittests/InstructionCountCI/X87ldst-SVE.json b/unittests/InstructionCountCI/X87ldst-SVE.json index d55740af0..8ce9f6291 100644 --- a/unittests/InstructionCountCI/X87ldst-SVE.json +++ b/unittests/InstructionCountCI/X87ldst-SVE.json @@ -11,7 +11,7 @@ "FLAGM2", "RPRES" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "fstp tword [rax]": { diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 1d94886fe..b6161926f 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -10,7 +10,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "fadd dword [rax]": { diff --git a/unittests/InstructionCountCI/x87_32Bit.json b/unittests/InstructionCountCI/x87_32Bit.json index 5c12f3520..6415ea77e 100644 --- a/unittests/InstructionCountCI/x87_32Bit.json +++ b/unittests/InstructionCountCI/x87_32Bit.json @@ -10,7 +10,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "Multiple fld/fst": { diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index a11ae35e9..2f6f416eb 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "fadd dword [rax]": { diff --git a/unittests/InstructionCountCI/x87_f64_32Bit.json b/unittests/InstructionCountCI/x87_f64_32Bit.json index 970ff96da..35a5393ea 100644 --- a/unittests/InstructionCountCI/x87_f64_32Bit.json +++ b/unittests/InstructionCountCI/x87_f64_32Bit.json @@ -15,7 +15,7 @@ "SVE256", "CSSC" ], - "BinaryCacheVersion": 23 + "BinaryCacheVersion": 24 }, "Instructions": { "fstp dword [ebx*4+0x204a20]": {