Ryan Houdek fba7c4bedc IR/RA: Fixes register aliasing and pre-colouring for AVX ...

This is the cause of a bunch of redundant moves that shows up in
InstCountCI. Fixing this aliasing and pre-colouring issue causes a ton
of 256-bit operations to become optimal.

2023-10-04 10:04:06 -07:00

..

Config

Config: Adds an option to disable vixl sim indirect runtime calls

2023-10-02 16:23:11 -07:00

Context

FEXCore: Wire up the new option to disable vixl indirect runtimes

2023-10-02 16:26:12 -07:00

Core

OpcodeDispatcher: Minor optimization in vzeroall

2023-10-04 10:01:13 -07:00

GDBJIT

FEXCore/Interface/GDBJIT: Adds SPDX identifier

2023-09-19 17:33:15 -07:00

HLE/Thunks

FEXCore/Interface/Thunks: Adds SPDX identifier

2023-09-19 17:33:14 -07:00

IR

IR/RA: Fixes register aliasing and pre-colouring for AVX

2023-10-04 10:04:06 -07:00