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FEX-Emu--FEX/FEXCore/Source/Interface/IR
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Ryan Houdek fba7c4bedc IR/RA: Fixes register aliasing and pre-colouring for AVX 
This is the cause of a bunch of redundant moves that shows up in
InstCountCI. Fixing this aliasing and pre-colouring issue causes a ton
of 256-bit operations to become optimal.
2023-10-04 10:04:06 -07:00
..
Passes
IR/RA: Fixes register aliasing and pre-colouring for AVX
2023-10-04 10:04:06 -07:00
AOTIR.cpp
FEXCore/Interface/IR: Adds SPDX identifier
2023-09-19 17:33:14 -07:00
AOTIR.h
FEXCore/Interface/IR: Adds SPDX identifier
2023-09-19 17:33:14 -07:00
IR.json
X87F64: Implement FABS with vector instruction
2023-10-01 14:39:55 +10:30
IRDumper.cpp
IR: Add bit masking selects
2023-09-22 19:07:42 -04:00
IREmitter.cpp
FEXCore/Interface/IR: Adds SPDX identifier
2023-09-19 17:33:14 -07:00
IRParser.cpp
IR: Add bit masking selects
2023-09-22 19:07:42 -04:00
Passes.h
Passes: Rename SyscallOptimization
2023-09-24 17:25:38 -07:00
PassManager.cpp
Passes: Rename SyscallOptimization
2023-09-24 17:25:38 -07:00
PassManager.h
Passes: Rename SyscallOptimization
2023-09-24 17:25:38 -07:00