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FEX-Emu--FEX/unittests/InstructionCountCI/Secondary_32Bit.json
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Alyssa Rosenzweig cea551c2ac InstCountCI: Update
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-17 17:37:24 -04:00

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{
"Features": {
"Bitness": 32,
"EnabledHostFeatures": [],
"DisabledHostFeatures": [
"SVE128",
"SVE256"
]
},
"Instructions": {
"push fs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #146]",
"str w20, [x8, #-4]!"
]
},
"pop fs": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xa1",
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #146]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #176]"
]
},
"push gs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa8",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #144]",
"str w20, [x8, #-4]!"
]
},
"pop gs": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xa9",
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #144]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #168]"
]
}
}
}