mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 14:00:16 +02:00
504 lines
13 KiB
JSON
504 lines
13 KiB
JSON
{
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"Features": {
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"Bitness": 32,
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"EnabledHostFeatures": [],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"FlagM",
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"FlagM2"
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]
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},
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"Instructions": {
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"push es": {
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"ExpectedInstructionCount": 2,
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"Comment": "0x06",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #136]",
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"str w20, [x8, #-4]!"
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]
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},
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"pop es": {
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"ExpectedInstructionCount": 7,
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"Comment": "0x07",
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"ExpectedArm64ASM": [
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"ldr w20, [x8]",
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"add x8, x8, #0x4 (4)",
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"strh w20, [x28, #136]",
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"ubfx w20, w20, #3, #13",
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"add x0, x28, x20, lsl #2",
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"ldr w20, [x0, #896]",
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"str w20, [x28, #152]"
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]
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},
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"push cs": {
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"ExpectedInstructionCount": 2,
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"Comment": "0x0e",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #138]",
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"str w20, [x8, #-4]!"
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]
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},
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"push ss": {
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"ExpectedInstructionCount": 2,
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"Comment": "0x16",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #140]",
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"str w20, [x8, #-4]!"
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]
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},
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"pop ss": {
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"ExpectedInstructionCount": 7,
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"Comment": "0x17",
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"ExpectedArm64ASM": [
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"ldr w20, [x8]",
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"add x8, x8, #0x4 (4)",
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"strh w20, [x28, #140]",
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"ubfx w20, w20, #3, #13",
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"add x0, x28, x20, lsl #2",
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"ldr w20, [x0, #896]",
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"str w20, [x28, #160]"
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]
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},
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"push ds": {
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"ExpectedInstructionCount": 2,
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"Comment": "0x1e",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #142]",
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"str w20, [x8, #-4]!"
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]
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},
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"pop ds": {
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"ExpectedInstructionCount": 7,
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"Comment": "0x1f",
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"ExpectedArm64ASM": [
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"ldr w20, [x8]",
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"add x8, x8, #0x4 (4)",
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"strh w20, [x28, #142]",
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"ubfx w20, w20, #3, #13",
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"add x0, x28, x20, lsl #2",
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"ldr w20, [x0, #896]",
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"str w20, [x28, #164]"
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]
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},
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"daa": {
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"ExpectedInstructionCount": 56,
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"Comment": "0x27",
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"ExpectedArm64ASM": [
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"cset w20, hs",
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"eor w21, w27, w26",
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"ubfx w21, w21, #4, #1",
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"uxtb w22, w4",
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"mrs x23, nzcv",
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"and w23, w23, #0xdfffffff",
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"msr nzcv, x23",
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"and x23, x22, #0xf",
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"mrs x24, nzcv",
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"cmp x23, #0x9 (9)",
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"cset x23, hi",
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"orr x21, x21, x23",
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"msr nzcv, x24",
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"cbnz x21, #+0xc",
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"mov w27, #0x0",
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"b #+0x2c",
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"add x21, x22, #0x6 (6)",
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"bfxil w4, w21, #0, #8",
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"cset w21, hs",
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"orr x21, x20, x21",
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"mrs x23, nzcv",
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"mov w0, w23",
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"bfi w0, w21, #29, #1",
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"mov w21, w0",
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"mov w27, #0x10",
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"msr nzcv, x21",
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"mrs x21, nzcv",
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"cmp x22, #0x99 (153)",
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"cset x22, hi",
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"orr x20, x20, x22",
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"msr nzcv, x21",
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"cbnz x20, #+0x14",
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"mrs x20, nzcv",
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"and w20, w20, #0xdfffffff",
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"msr nzcv, x20",
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"b #+0x1c",
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"uxtb w20, w4",
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"add x20, x20, #0x60 (96)",
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"bfxil w4, w20, #0, #8",
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"mrs x20, nzcv",
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"orr w20, w20, #0x20000000",
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"msr nzcv, x20",
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"uxtb w26, w4",
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"and x20, x26, #0x80",
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"mrs x21, nzcv",
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"cmp x20, #0x0 (0)",
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"cset x20, hs",
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"mov w0, w21",
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"bfi w0, w20, #31, #1",
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"mov w20, w0",
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"and x21, x26, #0xff",
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"cmp x21, #0x0 (0)",
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"cset x21, eq",
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"bfi w20, w21, #30, #1",
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"eor w27, w27, w26",
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"msr nzcv, x20"
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]
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},
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"das": {
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"ExpectedInstructionCount": 56,
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"Comment": "0x2f",
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"ExpectedArm64ASM": [
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"cset w20, hs",
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"eor w21, w27, w26",
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"ubfx w21, w21, #4, #1",
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"uxtb w22, w4",
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"mrs x23, nzcv",
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"and w23, w23, #0xdfffffff",
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"msr nzcv, x23",
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"and x23, x22, #0xf",
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"mrs x24, nzcv",
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"cmp x23, #0x9 (9)",
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"cset x23, hi",
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"orr x21, x21, x23",
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"msr nzcv, x24",
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"cbnz x21, #+0xc",
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"mov w27, #0x0",
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"b #+0x2c",
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"sub x21, x22, #0x6 (6)",
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"bfxil w4, w21, #0, #8",
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"cset w21, hs",
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"orr x21, x20, x21",
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"mrs x23, nzcv",
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"mov w0, w23",
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"bfi w0, w21, #29, #1",
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"mov w21, w0",
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"mov w27, #0x10",
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"msr nzcv, x21",
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"mrs x21, nzcv",
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"cmp x22, #0x99 (153)",
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"cset x22, hi",
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"orr x20, x20, x22",
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"msr nzcv, x21",
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"cbnz x20, #+0x14",
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"mrs x20, nzcv",
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"and w20, w20, #0xdfffffff",
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"msr nzcv, x20",
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"b #+0x1c",
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"uxtb w20, w4",
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"sub x20, x20, #0x60 (96)",
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"bfxil w4, w20, #0, #8",
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"mrs x20, nzcv",
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"orr w20, w20, #0x20000000",
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"msr nzcv, x20",
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"uxtb w26, w4",
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"and x20, x26, #0x80",
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"mrs x21, nzcv",
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"cmp x20, #0x0 (0)",
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"cset x20, hs",
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"mov w0, w21",
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"bfi w0, w20, #31, #1",
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"mov w20, w0",
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"and x21, x26, #0xff",
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"cmp x21, #0x0 (0)",
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"cset x21, eq",
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"bfi w20, w21, #30, #1",
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"eor w27, w27, w26",
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"msr nzcv, x20"
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]
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},
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"aaa": {
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"ExpectedInstructionCount": 24,
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"Comment": "0x37",
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"ExpectedArm64ASM": [
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"eor w20, w27, w26",
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"ubfx w20, w20, #4, #1",
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"uxtb w21, w4",
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"uxth w22, w4",
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"and x21, x21, #0xf",
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"mrs x23, nzcv",
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"cmp x21, #0x9 (9)",
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"cset x21, hi",
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"orr x20, x20, x21",
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"msr nzcv, x23",
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"cbnz x20, #+0x1c",
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"mov w20, #0xff0f",
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"and x20, x22, x20",
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"bfxil w4, w20, #0, #16",
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"mov w27, #0x0",
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"msr nzcv, x27",
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"b #+0x20",
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"add x20, x22, #0x106 (262)",
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"mov w21, #0xff0f",
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"and x20, x20, x21",
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"bfxil w4, w20, #0, #16",
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"mov w20, #0x20000000",
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"mov w27, #0x10",
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"msr nzcv, x20"
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]
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},
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"aas": {
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"ExpectedInstructionCount": 25,
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"Comment": "0x3f",
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"ExpectedArm64ASM": [
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"eor w20, w27, w26",
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"ubfx w20, w20, #4, #1",
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"uxtb w21, w4",
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"uxth w22, w4",
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"and x21, x21, #0xf",
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"mrs x23, nzcv",
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"cmp x21, #0x9 (9)",
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"cset x21, hi",
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"orr x20, x20, x21",
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"msr nzcv, x23",
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"cbnz x20, #+0x1c",
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"mov w20, #0xff0f",
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"and x20, x22, x20",
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"bfxil w4, w20, #0, #16",
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"mov w27, #0x0",
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"msr nzcv, x27",
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"b #+0x24",
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"sub x20, x22, #0x6 (6)",
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"sub x20, x20, #0x100 (256)",
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"mov w21, #0xff0f",
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"and x20, x20, x21",
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"bfxil w4, w20, #0, #16",
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"mov w20, #0x20000000",
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"mov w27, #0x10",
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"msr nzcv, x20"
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]
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},
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"inc ax": {
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"ExpectedInstructionCount": 11,
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"Comment": "0x40",
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"ExpectedArm64ASM": [
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"uxth w27, w4",
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"add w26, w27, #0x1 (1)",
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"bfxil w4, w26, #0, #16",
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"cset w20, hs",
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"cmn wzr, w26, lsl #16",
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"mrs x21, nzcv",
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"bic w22, w26, w27",
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"ubfx x22, x22, #15, #1",
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"orr w21, w21, w22, lsl #28",
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"orr w20, w21, w20, lsl #29",
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"msr nzcv, x20"
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]
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},
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"inc eax": {
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"ExpectedInstructionCount": 10,
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"Comment": "0x40",
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"ExpectedArm64ASM": [
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"mov w27, w4",
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"add w4, w27, #0x1 (1)",
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"mov w26, w4",
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"cset w20, hs",
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"cmn w27, #0x1 (1)",
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"mrs x21, nzcv",
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"mov w0, w21",
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"bfi w0, w20, #29, #1",
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"mov w20, w0",
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"msr nzcv, x20"
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]
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},
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"dec ax": {
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"ExpectedInstructionCount": 11,
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"Comment": "0x48",
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"ExpectedArm64ASM": [
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"uxth w27, w4",
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"sub w26, w27, #0x1 (1)",
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"bfxil w4, w26, #0, #16",
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"cset w20, hs",
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"cmn wzr, w26, lsl #16",
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"mrs x21, nzcv",
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"bic w22, w27, w26",
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"ubfx x22, x22, #15, #1",
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"orr w21, w21, w22, lsl #28",
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"orr w20, w21, w20, lsl #29",
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"msr nzcv, x20"
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]
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},
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"push ax": {
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"ExpectedInstructionCount": 1,
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"Comment": "0x50",
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"ExpectedArm64ASM": [
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"strh w4, [x8, #-2]!"
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]
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},
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"push eax": {
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"ExpectedInstructionCount": 1,
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"Comment": "0x50",
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"ExpectedArm64ASM": [
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"str w4, [x8, #-4]!"
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]
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},
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"dec eax": {
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"ExpectedInstructionCount": 10,
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"Comment": "0x48",
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"ExpectedArm64ASM": [
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"mov w27, w4",
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"sub w4, w27, #0x1 (1)",
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"mov w26, w4",
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"cset w20, hs",
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"cmp w27, #0x1 (1)",
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"mrs x21, nzcv",
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"mov w0, w21",
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"bfi w0, w20, #29, #1",
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"mov w20, w0",
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"msr nzcv, x20"
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]
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},
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"pusha": {
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"ExpectedInstructionCount": 10,
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"Comment": "0x60",
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"ExpectedArm64ASM": [
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"mov w20, w8",
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"str w4, [x20, #-4]!",
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"str w5, [x20, #-4]!",
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"str w6, [x20, #-4]!",
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"str w7, [x20, #-4]!",
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"str w8, [x20, #-4]!",
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"str w9, [x20, #-4]!",
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"str w10, [x20, #-4]!",
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"mov w8, w20",
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"str w11, [x8, #-4]!"
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]
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},
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"pushad": {
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"ExpectedInstructionCount": 10,
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"Comment": "0x60",
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"ExpectedArm64ASM": [
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"mov w20, w8",
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"str w4, [x20, #-4]!",
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"str w5, [x20, #-4]!",
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"str w6, [x20, #-4]!",
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"str w7, [x20, #-4]!",
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"str w8, [x20, #-4]!",
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"str w9, [x20, #-4]!",
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"str w10, [x20, #-4]!",
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"mov w8, w20",
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"str w11, [x8, #-4]!"
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]
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},
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"popa": {
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"ExpectedInstructionCount": 14,
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"Comment": "0x61",
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"ExpectedArm64ASM": [
|
|
"ldr w11, [x8]",
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|
"add x20, x8, #0x4 (4)",
|
|
"ldr w10, [x8, #4]",
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"add x21, x20, #0x4 (4)",
|
|
"ldr w9, [x20, #4]",
|
|
"add x20, x21, #0x8 (8)",
|
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"ldr w7, [x21, #8]",
|
|
"add x21, x20, #0x4 (4)",
|
|
"ldr w6, [x20, #4]",
|
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"add x20, x21, #0x4 (4)",
|
|
"ldr w5, [x21, #4]",
|
|
"add x21, x20, #0x4 (4)",
|
|
"ldr w4, [x20, #4]",
|
|
"add x8, x21, #0x4 (4)"
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|
]
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},
|
|
"popad": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": "0x61",
|
|
"ExpectedArm64ASM": [
|
|
"ldr w11, [x8]",
|
|
"add x20, x8, #0x4 (4)",
|
|
"ldr w10, [x8, #4]",
|
|
"add x21, x20, #0x4 (4)",
|
|
"ldr w9, [x20, #4]",
|
|
"add x20, x21, #0x8 (8)",
|
|
"ldr w7, [x21, #8]",
|
|
"add x21, x20, #0x4 (4)",
|
|
"ldr w6, [x20, #4]",
|
|
"add x20, x21, #0x4 (4)",
|
|
"ldr w5, [x21, #4]",
|
|
"add x21, x20, #0x4 (4)",
|
|
"ldr w4, [x20, #4]",
|
|
"add x8, x21, #0x4 (4)"
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]
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|
},
|
|
"aam": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0xd4",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"mov w21, #0xa",
|
|
"udiv x22, x20, x21",
|
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"udiv x2, x20, x21",
|
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"msub x20, x2, x21, x20",
|
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"lsl x21, x22, #8",
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"add x20, x21, x20",
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"bfxil w4, w20, #0, #16",
|
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"uxtb w26, w4",
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"cmn wzr, w26, lsl #24"
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]
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},
|
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"aad": {
|
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"ExpectedInstructionCount": 10,
|
|
"Comment": "0xd5",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"uxth w21, w4",
|
|
"lsr w21, w21, #8",
|
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"mov w22, #0xa",
|
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"mul x21, x21, x22",
|
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"add x20, x20, x21",
|
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"and x20, x20, #0xff",
|
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"bfxil w4, w20, #0, #16",
|
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"uxtb w26, w4",
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"cmn wzr, w26, lsl #24"
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]
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},
|
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"db 0xd4, 0x40": {
|
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"ExpectedInstructionCount": 10,
|
|
"Comment": [
|
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"aam with a different immediate byte base",
|
|
"0xd4"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
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"mov w21, #0x40",
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"udiv x22, x20, x21",
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"udiv x2, x20, x21",
|
|
"msub x20, x2, x21, x20",
|
|
"lsl x21, x22, #8",
|
|
"add x20, x21, x20",
|
|
"bfxil w4, w20, #0, #16",
|
|
"uxtb w26, w4",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"db 0xd5, 0x40": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": [
|
|
"aad with a different immediate byte base",
|
|
"0xd5"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"uxth w21, w4",
|
|
"lsr w21, w21, #8",
|
|
"lsl x21, x21, #6",
|
|
"add x20, x20, x21",
|
|
"and x20, x20, #0xff",
|
|
"bfxil w4, w20, #0, #16",
|
|
"uxtb w26, w4",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"salc": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0xd6",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"cset w21, hs",
|
|
"add w20, w20, w21",
|
|
"uxtb w21, w4",
|
|
"sub w20, w21, w20",
|
|
"bfxil w4, w20, #0, #8"
|
|
]
|
|
}
|
|
}
|
|
}
|