steam-frame/FEX-Emu--FEX
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FEX-Emu--FEX/FEXCore/Source/Interface/Core/JIT
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Lioncache 1f6c6345d9 VectorOps: Handle SVE VURAvg a little better 
We can perform less moves by checking for scenarios where aliasing
occurs. Since addition is commutative (usually, general-case anyway),
order of inputs doesn't strictly matter here.
2023-10-19 12:14:12 +02:00
..
Arm64
VectorOps: Handle SVE VURAvg a little better
2023-10-19 12:14:12 +02:00
JITCore.h
FEXCore/Interface/Core/JIT: Adds SPDX identifier
2023-09-19 17:33:15 -07:00