Lioncache 1f6c6345d9 VectorOps: Handle SVE VURAvg a little better ...

We can perform less moves by checking for scenarios where aliasing
occurs. Since addition is commutative (usually, general-case anyway),
order of inputs doesn't strictly matter here.

2023-10-19 12:14:12 +02:00

..

Config

FEXCore: Implements support for RPRES

2023-10-07 23:13:47 -07:00

Context

InstCountCI: Support multiple instructions in the tests

2023-10-09 21:49:53 -07:00

Core

VectorOps: Handle SVE VURAvg a little better

2023-10-19 12:14:12 +02:00

GDBJIT

FEXCore/Interface/GDBJIT: Adds SPDX identifier

2023-09-19 17:33:15 -07:00

HLE/Thunks

FEXCore/Interface/Thunks: Adds SPDX identifier

2023-09-19 17:33:14 -07:00

IR

IR: Adds scalar vector insert operations

2023-10-10 03:17:19 -07:00