Lioncache 1f6c6345d9 VectorOps: Handle SVE VURAvg a little better ...

We can perform less moves by checking for scenarios where aliasing
occurs. Since addition is commutative (usually, general-case anyway),
order of inputs doesn't strictly matter here.

2023-10-19 12:14:12 +02:00

..

Common

Merge pull request #3120 from Sonicadvance1/more_optimal_x87

2023-09-21 15:35:37 -07:00

Interface

VectorOps: Handle SVE VURAvg a little better

2023-10-19 12:14:12 +02:00

Utils

FEXCore/Utils: Adds SPDX identifier

2023-09-19 17:33:14 -07:00

CMakeLists.txt

FEXCore/IR: Changes over to automated IR dispatch generation

2023-10-07 15:01:47 -07:00