Docs: Update for release FEX-2209

Thunks: Consolidate all generated code to one file per library per platform

.github/workflows/ccpp.yml

@@ -40,7 +40,6 @@ jobs:
       # Use a bash shell so we can use the same syntax for environment variable
       # access regardless of the host operating system
       shell: bash
-      working-directory: ${{runner.workspace}}/build
       run: $GITHUB_WORKSPACE/Scripts/CI_FetchRootFS.py
 
     - name : submodule checkout
@@ -65,7 +64,7 @@ jobs:
       # Note the current convention is to use the -S and -B options here to specify source
       # and build directories, but this is only available with CMake 3.13 and higher.
       # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DENABLE_INTERPRETER=True -DBUILD_FEX_LINUX_TESTS=True
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DENABLE_INTERPRETER=True -DBUILD_FEX_LINUX_TESTS=True -DBUILD_THUNKS=True
 
     - name: Build
       working-directory: ${{runner.workspace}}/build
@@ -178,6 +177,17 @@ jobs:
       working-directory: ${{runner.workspace}}/build
       run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_FEXLinuxTests.log || true
 
+    - name: Thunkgen tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target thunkgen_tests
+
+    - name: Thunkgen Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ThunkgenTests.log || true
+
     - name: Truncate test results
       if: ${{ always() }}
       shell: bash

.gitignore

@@ -10,3 +10,4 @@ out/
 .vscode/
 .vs/
 *.pyc
+.cache

.gitmodules

@@ -49,3 +49,7 @@
 	shallow = true
 	path = External/robin-map
 	url = https://github.com/Tessil/robin-map.git
+[submodule "External/Vulkan-Headers"]
+	shallow = true
+	path = External/Vulkan-Headers
+	url = https://github.com/KhronosGroup/Vulkan-Headers.git

CMakeLists.txt

@@ -20,7 +20,6 @@ option(ENABLE_GDB_SYMBOLS "Enables GDBSymbols integration support" ${HAVE_GDB_JI
 option(ENABLE_VISUAL_DEBUGGER "Enables the visual debugger for compiling" FALSE)
 option(ENABLE_STRICT_WERROR "Enables stricter -Werror for CI" FALSE)
 option(ENABLE_WERROR "Enables -Werror" FALSE)
-option(ENABLE_STATIC_PIE "Enables static-pie build" FALSE)
 option(ENABLE_JEMALLOC "Enables jemalloc allocator" TRUE)
 option(ENABLE_OFFLINE_TELEMETRY "Enables FEX offline telemetry" TRUE)
 option(ENABLE_COMPILE_TIME_TRACE "Enables time trace compile option" FALSE)
@@ -140,130 +139,6 @@ if(DEFINED ENV{TERMUX_VERSION} OR ENABLE_TERMUX_BUILD)
   set(ENABLE_JEMALLOC FALSE)
 endif()
 
-if (ENABLE_STATIC_PIE)
-  if (_M_ARM_64 AND ENABLE_LLD)
-    message (FATAL_ERROR "Static linking does not currently work with AArch64+lld. Use GNU ld for now.")
-  endif()
-
-  file(WRITE ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt.c
-    "int main(int argc, char* argv[])
-      {
-        return 0;
-      }")
-
-  # Compile the test application with our LD_OVERRIDE and static-pie options
-  try_compile(
-    COMPILE_RESULT
-    ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp
-    ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt.c
-    COMPILE_DEFINITIONS "-fPIE ${LD_OVERRIDE}"
-    LINK_LIBRARIES "-static-pie ${LD_OVERRIDE}"
-    COPY_FILE ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt
-  )
-
-  if (${COMPILE_RESULT})
-    # Read the symbols from the elf
-    execute_process(COMMAND
-      readelf -s ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt
-      OUTPUT_FILE ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/plt_out.txt
-      OUTPUT_VARIABLE PLT_SYMBOLS)
-
-    # Pull out the __rela_iplt_{start,end} symbols if they exist
-    execute_process(COMMAND
-      "grep" "__rela_iplt" ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/plt_out.txt
-      OUTPUT_VARIABLE PLT_SYMBOLS)
-
-    set (SYMBOLS_FINE TRUE)
-    set (HAS_IPLT -1)
-    # Check if we have any symbols in our grep output
-    # The symbols must either not exist at all OR the symbols are zero
-    if (PLT_SYMBOLS)
-      string(FIND ${PLT_SYMBOLS} "__rela_iplt_start" HAS_IPLT)
-    endif()
-
-    if (NOT HAS_IPLT EQUAL -1)
-      # We have some symbols from readelf. Let's parse the results to check if they are zero
-      # Format: '35: 0000000000000000     0 NOTYPE  LOCAL  HIDDEN   UND __rela_iplt_start'
-      string(REPLACE "\n" ";" SYMBOL_LIST ${PLT_SYMBOLS})
-      foreach (SYMBOL ${SYMBOL_LIST})
-        # strip any leading and trailing whitespace
-        string (STRIP ${SYMBOL} SYMBOL)
-        # Convert string to a list
-        string(REPLACE " " ";" SYMBOL_VALUES ${SYMBOL}})
-        # Pull out the address argument
-        list(GET SYMBOL_VALUES 1 OFFSET)
-
-        # Check against integer zero
-        if (NOT ${OFFSET} EQUAL 0)
-          # Symbol wasn't zero, this now fails
-          set (SYMBOLS_FINE FALSE)
-        endif()
-      endforeach()
-    endif()
-
-    if (SYMBOLS_FINE)
-      # We can now exnable static-pie
-      set (STATIC_PIE_OPTIONS "-static-pie")
-      # Pthreads has an issue with exposing symbols
-      # We need to make some concessions to the pthread gods
-      if (ENABLE_LLD)
-        set (PTHREAD_LIB
-          -Wl,--undefined-glob=pthread_*
-          -Wl,--undefined=__cxa_finalize
-          -Wl,--undefined=_pthread_cleanup_push_defer
-          -Wl,--undefined=_pthread_cleanup_pop_restore
-          -Wl,--undefined=__pthread_cleanup_upto
-          pthread)
-      else()
-        set (PTHREAD_LIB
-          -Wl,--undefined=pthread_join
-          -Wl,--undefined=pthread_attr_getdetachstate
-          -Wl,--undefined=pthread_sigmask
-          -Wl,--undefined=pthread_mutex_lock
-          -Wl,--undefined=pthread_cond_init
-          -Wl,--undefined=pthread_attr_init
-          -Wl,--undefined=pthread_mutex_unlock
-          -Wl,--undefined=pthread_mutexattr_destroy
-          -Wl,--undefined=pthread_detach
-          -Wl,--undefined=pthread_mutex_init
-          -Wl,--undefined=pthread_getattr_np
-          -Wl,--undefined=pthread_cond_timedwait
-          -Wl,--undefined=pthread_attr_destroy
-          -Wl,--undefined=pthread_mutexattr_settype
-          -Wl,--undefined=pthread_rwlock_unlock
-          -Wl,--undefined=pthread_rwlock_wrlock
-          -Wl,--undefined=pthread_setspecific
-          -Wl,--undefined=pthread_create
-          -Wl,--undefined=pthread_cond_clockwait
-          -Wl,--undefined=pthread_key_create
-          -Wl,--undefined=pthread_rwlock_rdlock
-          -Wl,--undefined=pthread_setname_np
-          -Wl,--undefined=pthread_cond_signal
-          -Wl,--undefined=pthread_mutexattr_init
-          -Wl,--undefined=pthread_attr_setstack
-          -Wl,--undefined=pthread_self
-          -Wl,--undefined=pthread_getaffinity_np
-          -Wl,--undefined=pthread_cond_wait
-          -Wl,--undefined=pthread_mutex_trylock
-          -Wl,--undefined=pthread_cond_broadcast
-          -Wl,--undefined=pthread_cond_destroy
-          -Wl,--undefined=pthread_getspecific
-          -Wl,--undefined=pthread_key_delete
-          -Wl,--undefined=pthread_once
-          -Wl,--undefined=__cxa_finalize
-          -Wl,--undefined=_pthread_cleanup_push_defer
-          -Wl,--undefined=_pthread_cleanup_pop_restore
-          -Wl,--undefined=__pthread_cleanup_upto
-          pthread)
-      endif()
-    else()
-      message (FATAL_ERROR "Application has __rela_iplt_{start,end} symbols. Which means static-pie can't be enabled")
-    endif()
-  else()
-    message (FATAL_ERROR "Couldn't compile static-pie test. Static-pie can't be enabled! Is your glibc compiled without static-pie?")
-  endif()
-endif()
-
 if (ENABLE_ASAN)
   add_definitions(-DENABLE_ASAN=1)
   add_compile_options(-fno-omit-frame-pointer -fsanitize=address -fsanitize-address-use-after-scope)
@@ -499,15 +374,20 @@ add_subdirectory(Source/)
 add_subdirectory(Data/AppConfig/)
 
 # Install the ThunksDB file
-install(
-  FILES ${CMAKE_CURRENT_SOURCE_DIR}/Data/ThunksDB.json
-  DESTINATION ${DATA_DIRECTORY}/)
+file(GLOB CONFIG_SOURCES CONFIGURE_DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/Data/*.json)
+
+# Any application configuration json file gets installed
+foreach(CONFIG_SRC ${CONFIG_SOURCES})
+  install(FILES ${CONFIG_SRC}
+    DESTINATION ${DATA_DIRECTORY}/)
+endforeach()
 
 if (BUILD_TESTS)
   add_subdirectory(unittests/)
 endif()
 
 if (BUILD_THUNKS)
+  set (FEX_PROJECT_SOURCE_DIR ${PROJECT_SOURCE_DIR})
   add_subdirectory(ThunkLibs/Generator)
 
   # Thunk targets for both host libraries and IDE integration
@@ -527,6 +407,7 @@ if (BUILD_THUNKS)
       "-DCMAKE_TOOLCHAIN_FILE:FILEPATH=${X86_TOOLCHAIN_FILE}"
       "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}"
       "-DSTRUCT_VERIFIER=${CMAKE_SOURCE_DIR}/Scripts/StructPackVerifier.py"
+      "-DFEX_PROJECT_SOURCE_DIR=${FEX_PROJECT_SOURCE_DIR}"
       "-DGENERATOR_EXE=$<TARGET_FILE:thunkgen>"
     INSTALL_COMMAND ""
     BUILD_ALWAYS ON
@@ -593,15 +474,9 @@ endif()
 
 # Package creation
 set (CPACK_GENERATOR "DEB")
-if (ENABLE_STATIC_PIE)
-  set (CPACK_PACKAGE_NAME fex-emu-static)
-  set (CPACK_DEBIAN_PACKAGE_CONFLICTS "fex-emu")
-else()
-  set (CPACK_PACKAGE_NAME fex-emu)
-  set (CPACK_DEBIAN_PACKAGE_CONFLICTS "fex-emu-static")
-endif()
+set (CPACK_PACKAGE_NAME fex-emu)
 set (CPACK_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${GIT_DESCRIBE_STRING}_${CMAKE_SYSTEM_PROCESSOR}")
-set (CPACK_PACKAGE_CONTACT "FEX-Emu Maintainers <team@fex-emu.org>")
+set (CPACK_PACKAGE_CONTACT "FEX-Emu Maintainers <team@fex-emu.com>")
 set (CPACK_PACKAGE_VERSION_MAJOR "${FEX_VERSION_MAJOR}")
 set (CPACK_PACKAGE_VERSION_MINOR "${FEX_VERSION_MINOR}")
 set (CPACK_PACKAGE_VERSION_PATCH "${FEX_VERSION_PATCH}")

CODE_OF_CONDUCT.md

@@ -55,7 +55,7 @@ further defined and clarified by project maintainers.
 ## Enforcement
 
 Instances of abusive, harassing, or otherwise unacceptable behavior may be
-reported by contacting the project team at team@fex-emu.org. All
+reported by contacting the project team at team@fex-emu.com. All
 complaints will be reviewed and investigated and will result in a response that
 is deemed necessary and appropriate to the circumstances. The project team is
 obligated to maintain confidentiality with regard to the reporter of an incident.

Data/AppConfig/CMakeLists.txt

@@ -11,15 +11,15 @@ endforeach()
 # First generate then install it
 foreach(GEN_CONFIG_SRC ${GEN_CONFIG_SOURCES})
   # Get the filename only component
-  get_filename_component(CONFIG_NAME ${GEN_CONFIG_SRC} NAME_WE)
+  get_filename_component(CONFIG_NAME ${GEN_CONFIG_SRC} NAME_WLE)
 
   # Configure it
   configure_file(
     ${GEN_CONFIG_SRC}
-    ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME}.json)
+    ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME})
 
   # Then install the configured json
   install(
-    FILES ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME}.json
+    FILES ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME}
     DESTINATION ${DATA_DIRECTORY}/AppConfig/)
 endforeach()

Data/AppConfig/VC_redist.x64.exe.json

@@ -0,0 +1,5 @@
+{
+  "Config": {
+    "x86dec_SynchronizeRIPOnAllBlocks": "1"
+  }
+}

Data/AppConfig/VC_redist.x86.exe.json

@@ -0,0 +1,5 @@
+{
+  "Config": {
+    "x86dec_SynchronizeRIPOnAllBlocks": "1"
+  }
+}

Data/AppConfig/vcredist_x64.exe.json

@@ -0,0 +1,5 @@
+{
+  "Config": {
+    "x86dec_SynchronizeRIPOnAllBlocks": "1"
+  }
+}

Data/AppConfig/vcredist_x86.exe.json

@@ -0,0 +1,5 @@
+{
+  "Config": {
+    "x86dec_SynchronizeRIPOnAllBlocks": "1"
+  }
+}

External/FEXCore/CMakeLists.txt

@@ -46,14 +46,14 @@ if (OVERRIDE_VERSION STREQUAL "detect")
 
   if (GIT_FOUND)
     execute_process(
-      COMMAND ${GIT_EXECUTABLE} rev-parse --short HEAD
+      COMMAND ${GIT_EXECUTABLE} rev-parse --short=7 HEAD
       WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
       OUTPUT_VARIABLE GIT_SHORT_HASH
       ERROR_QUIET
       OUTPUT_STRIP_TRAILING_WHITESPACE
     )
     execute_process(
-      COMMAND ${GIT_EXECUTABLE} describe
+      COMMAND ${GIT_EXECUTABLE} describe --abbrev=7
       WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
       OUTPUT_VARIABLE GIT_DESCRIBE_STRING
       ERROR_QUIET

External/FEXCore/Scripts/json_ir_generator.py

@@ -321,8 +321,6 @@ def print_ir_structs(defines):
 
 
         if op.SSAArgNum > 0:
-            # Add helpers for accessing SSA arguments, given how frequently they're accessed
-
             output_file.write("\t// Get index of argument by name\n")
             SSAArg = 0
             for arg in op.Arguments:
@@ -330,14 +328,6 @@ def print_ir_structs(defines):
                     output_file.write("\tstatic constexpr size_t {}_Index = {};\n".format(arg.Name, SSAArg))
                     SSAArg = SSAArg + 1
 
-            output_file.write("\n")
-            output_file.write("\t[[nodiscard]] OrderedNodeWrapper& Args(size_t Index) {\n")
-            output_file.write("\t\treturn Header.Args[Index];\n")
-            output_file.write("\t}\n")
-            output_file.write("\t[[nodiscard]] const OrderedNodeWrapper& Args(size_t Index) const {\n")
-            output_file.write("\t\treturn Header.Args[Index];\n")
-            output_file.write("\t}\n")
-
 
         output_file.write("};\n")
 

External/FEXCore/Source/Common/BitSet.h

@@ -20,12 +20,12 @@ struct BitSet final {
   ElementType *Memory;
   void Allocate(size_t Elements) {
     size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize;
-    LOGMAN_THROW_A_FMT((AllocateSize * MinimumSize) >= Elements, "Fail");
+    LOGMAN_THROW_AA_FMT((AllocateSize * MinimumSize) >= Elements, "Fail");
     Memory = static_cast<ElementType*>(FEXCore::Allocator::malloc(AllocateSize));
   }
   void Realloc(size_t Elements) {
     size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize;
-    LOGMAN_THROW_A_FMT((AllocateSize * MinimumSize) >= Elements, "Fail");
+    LOGMAN_THROW_AA_FMT((AllocateSize * MinimumSize) >= Elements, "Fail");
     Memory = static_cast<ElementType*>(FEXCore::Allocator::realloc(Memory, AllocateSize));
   }
   void Free() {
@@ -64,7 +64,7 @@ struct BitSetView final {
   ElementType *Memory;
 
   void GetView(BitSet<T> &Set, uint64_t ElementOffset) {
-    LOGMAN_THROW_A_FMT((ElementOffset % MinimumSize) == 0,
+    LOGMAN_THROW_AA_FMT((ElementOffset % MinimumSize) == 0,
                        "Bitset view offset needs to be aligned to size of backing element");
     Memory = &Set.Memory[ElementOffset / MinimumSizeBits];
   }

External/FEXCore/Source/Common/JitSymbols.cpp

@@ -7,6 +7,11 @@
 
 namespace FEXCore {
   JITSymbols::JITSymbols() : fp{nullptr, std::fclose} {
+  }
+
+  JITSymbols::~JITSymbols() = default;
+
+  void JITSymbols::InitFile() {
     const auto PerfMap = fmt::format("/tmp/perf-{}.map", getpid());
 
     fp.reset(fopen(PerfMap.c_str(), "wb"));
@@ -16,8 +21,6 @@ namespace FEXCore {
     }
   }
 
-  JITSymbols::~JITSymbols() = default;
-
   void JITSymbols::Register(const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize) {
     if (!fp) return;
 

External/FEXCore/Source/Common/JitSymbols.h

@@ -11,6 +11,7 @@ public:
   JITSymbols();
   ~JITSymbols();
 
+  void InitFile();
   void Register(const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize);
   void Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name);
   void Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name, uintptr_t Offset);

External/FEXCore/Source/Interface/Config/Config.cpp

@@ -82,7 +82,7 @@ namespace JSON {
     json_t const* ConfigList = json_getProperty(json, "Config");
 
     if (!ConfigList) {
-      LogMan::Msg::EFmt("Couldn't get config list");
+      // This is a non-error if the configuration file exists but no Config section
       return;
     }
 
@@ -154,15 +154,20 @@ namespace JSON {
     return ConfigDir;
   }
 
-  std::string GetConfigFileLocation() {
+  std::string GetConfigFileLocation(bool Global) {
     std::string ConfigFile{};
-    const char *AppConfig = getenv("FEX_APP_CONFIG");
-    if (AppConfig) {
-      // App config environment variable overwrites only the config file
-      ConfigFile = AppConfig;
+    if (Global) {
+      ConfigFile = GetConfigDirectory(true) + "Config.json";
     }
     else {
-      ConfigFile = GetConfigDirectory(false) + "Config.json";
+      const char *AppConfig = getenv("FEX_APP_CONFIG");
+      if (AppConfig) {
+        // App config environment variable overwrites only the config file
+        ConfigFile = AppConfig;
+      }
+      else {
+        ConfigFile = GetConfigDirectory(false) + "Config.json";
+      }
     }
     return ConfigFile;
   }
@@ -206,7 +211,8 @@ namespace JSON {
   static std::map<FEXCore::Config::LayerType, std::unique_ptr<FEXCore::Config::Layer>> ConfigLayers;
   static FEXCore::Config::Layer *Meta{};
 
-  constexpr std::array<FEXCore::Config::LayerType, 6> LoadOrder = {
+  constexpr std::array<FEXCore::Config::LayerType, 7> LoadOrder = {
+    FEXCore::Config::LayerType::LAYER_GLOBAL_MAIN,
     FEXCore::Config::LayerType::LAYER_MAIN,
     FEXCore::Config::LayerType::LAYER_GLOBAL_APP,
     FEXCore::Config::LayerType::LAYER_LOCAL_APP,
@@ -613,7 +619,7 @@ namespace JSON {
   // Application loaders
   class MainLoader final : public FEXCore::Config::OptionMapper {
   public:
-    explicit MainLoader();
+    explicit MainLoader(FEXCore::Config::LayerType Type);
     explicit MainLoader(std::string ConfigFile);
     void Load() override;
 
@@ -659,9 +665,9 @@ namespace JSON {
     }
   }
 
-  MainLoader::MainLoader()
-    : FEXCore::Config::OptionMapper(FEXCore::Config::LayerType::LAYER_MAIN)
-    , Config{FEXCore::Config::GetConfigFileLocation()} {
+  MainLoader::MainLoader(FEXCore::Config::LayerType Type)
+    : FEXCore::Config::OptionMapper(Type)
+    , Config{FEXCore::Config::GetConfigFileLocation(Type == FEXCore::Config::LayerType::LAYER_GLOBAL_MAIN)} {
   }
 
   MainLoader::MainLoader(std::string ConfigFile)
@@ -735,12 +741,16 @@ namespace JSON {
     }
   }
 
+  std::unique_ptr<FEXCore::Config::Layer> CreateGlobalMainLayer() {
+    return std::make_unique<FEXCore::Config::MainLoader>(FEXCore::Config::LayerType::LAYER_GLOBAL_MAIN);
+  }
+
   std::unique_ptr<FEXCore::Config::Layer> CreateMainLayer(std::string const *File) {
     if (File) {
       return std::make_unique<FEXCore::Config::MainLoader>(*File);
     }
     else {
-      return std::make_unique<FEXCore::Config::MainLoader>();
+      return std::make_unique<FEXCore::Config::MainLoader>(FEXCore::Config::LayerType::LAYER_MAIN);
     }
   }
 

External/FEXCore/Source/Interface/Config/Config.json.in

@@ -49,6 +49,13 @@
           "Cache JIT object code to drive.",
           "Allows JIT code to be shared between applications"
         ]
+      },
+      "EnableAVX": {
+        "Type": "bool",
+        "Default": "true",
+        "Desc": [
+          "Determines whether or not we use the expanded register file for AVX or not"
+        ]
       }
     },
     "Emulation": {
@@ -309,6 +316,16 @@
           "Forces a process to stall out on initialization",
           "Useful for a process that keeps restarting and doesn't work"
         ]
+      },
+      "x86dec_SynchronizeRIPOnAllBlocks": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "An application that uses try-catch or longjump extensively needs the ability to do context aware state flushing",
+          "In the case of FEX's block-linking, it won't always ensure that RIP is synchronized.",
+          "If an exception occurs and RIP isn't synchronized, then FEX's exception stack restore may not long jump as expected",
+          "Can be useful for Wine applications that rely on stack unwinding"
+        ]
       }
     },
     "Misc": {
@@ -334,6 +351,13 @@
         "Desc": [
           "Loads an AOT IR cache for the loaded executable."
         ]
+      },
+      "ServerSocketPath": {
+        "Type": "str",
+        "Default": "",
+        "Desc": [
+          "Override for a FEXServer socket path. Only useful for chroots."
+        ]
       }
     }
   },
@@ -351,6 +375,17 @@
         "Type": "str",
         "Default": ""
       },
+      "APP_CONFIG_NAME": {
+        "Type": "str",
+        "Default": "",
+        "Desc": [
+          "This is the application config name that has been loaded.",
+          "This differs from APP_FILENAME in two ways",
+          "Where APP_FILENAME always points to the executable path that FEX-Emu is executing.",
+          "This matches what is used to load the AppLayer configuration name.",
+          "When running through a compatibility layer like wine, this will only be the exe name, instead of wine full path."
+        ]
+      },
       "IS64BIT_MODE": {
         "Type": "bool",
         "Default": "false"

External/FEXCore/Source/Interface/Context/Context.cpp

@@ -110,6 +110,10 @@ namespace FEXCore::Context {
   void RegisterExternalSyscallVisitor(FEXCore::Context::Context *CTX, [[maybe_unused]] uint64_t Syscall, [[maybe_unused]] FEXCore::HLE::SyscallVisitor *Visitor) {
   }
 
+  HostFeatures GetHostFeatures(const FEXCore::Context::Context *CTX) {
+    return CTX->HostFeatures;
+  }
+
   void HandleCallback(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread, uint64_t RIP) {
     CTX->HandleCallback(Thread, RIP);
   }
@@ -198,6 +202,10 @@ namespace FEXCore::Context {
     return CTX->AddCustomIREntrypoint(Entrypoint, Handler, Creator, Data);
   }
 
+  void AppendThunkDefinitions(FEXCore::Context::Context *CTX, std::vector<FEXCore::IR::ThunkDefinition> const& Definitions) {
+    CTX->AppendThunkDefinitions(Definitions);
+  }
+
 namespace Debug {
   void CompileRIP(FEXCore::Context::Context *CTX, uint64_t RIP) {
     CTX->CompileRIP(CTX->ParentThread, RIP);

External/FEXCore/Source/Interface/Context/Context.h

@@ -1,8 +1,8 @@
 #pragma once
 
 #include "Common/JitSymbols.h"
+#include "FEXHeaderUtils/ScopedSignalMask.h"
 #include "Interface/Core/CPUID.h"
-#include "Interface/Core/HostFeatures.h"
 #include "Interface/Core/X86HelperGen.h"
 #include "Interface/Core/ObjectCache/ObjectCacheService.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
@@ -10,6 +10,7 @@
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/Context.h>
 #include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Core/HostFeatures.h>
 #include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/Utils/CompilerDefs.h>
@@ -113,6 +114,8 @@ namespace FEXCore::Context {
       FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
       FEX_CONFIG_OPT(CacheObjectCodeCompilation, CACHEOBJECTCODECOMPILATION);
       FEX_CONFIG_OPT(x87ReducedPrecision, X87REDUCEDPRECISION);
+      FEX_CONFIG_OPT(x86dec_SynchronizeRIPOnAllBlocks, X86DEC_SYNCHRONIZERIPONALLBLOCKS);
+      FEX_CONFIG_OPT(EnableAVX, ENABLEAVX);
     } Config;
 
     FEXCore::HostFeatures HostFeatures;
@@ -121,6 +124,7 @@ namespace FEXCore::Context {
     FEXCore::Core::InternalThreadState* ParentThread;
     std::vector<FEXCore::Core::InternalThreadState*> Threads;
     std::atomic_bool CoreShuttingDown{false};
+    bool NeedToCheckXID{true};
 
     std::mutex IdleWaitMutex;
     std::condition_variable IdleWaitCV;
@@ -129,8 +133,8 @@ namespace FEXCore::Context {
     Event PauseWait;
     bool Running{};
 
-    std::shared_mutex CodeInvalidationMutex; 
-    
+    std::shared_mutex CodeInvalidationMutex;
+
     FEXCore::CPUIDEmu CPUID;
     FEXCore::HLE::SyscallHandler *SyscallHandler{};
     FEXCore::HLE::SourcecodeResolver *SourcecodeResolver{};
@@ -170,13 +174,26 @@ namespace FEXCore::Context {
     void RegisterHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required);
     void RegisterFrontendHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required);
 
-    // Must be called from owning thread
-    static void RemoveThreadCodeEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
+    static void ThreadRemoveCodeEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
+    static void ThreadAddBlockLink(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestDestination, uintptr_t HostLink, const std::function<void()> &delinker);
 
-    // Wrapper which takes CpuStateFrame instead of InternalThreadState
+    template<auto Fn>
+    static uint64_t ThreadExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame, uint64_t *record) {
+      FHU::ScopedSignalMaskWithSharedLock lk(Frame->Thread->CTX->CodeInvalidationMutex);
+
+      return Fn(Frame, record);
+    }
+
+    // Wrapper which takes CpuStateFrame instead of InternalThreadState and unique_locks CodeInvalidationMutex
     // Must be called from owning thread
-    static void RemoveThreadCodeEntryFromJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
-      RemoveThreadCodeEntry(Frame->Thread, GuestRIP);
+    static void ThreadRemoveCodeEntryFromJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
+      auto Thread = Frame->Thread;
+      
+      LogMan::Throw::AFmt(Thread->ThreadManager.GetTID() == gettid(), "Must be called from owning thread {}, not {}", Thread->ThreadManager.GetTID(), gettid());
+
+      FHU::ScopedSignalMaskWithUniqueLock lk(Thread->CTX->CodeInvalidationMutex);
+
+      ThreadRemoveCodeEntry(Thread, GuestRIP);
     }
 
     // returns false if a handler was already registered
@@ -305,6 +322,8 @@ namespace FEXCore::Context {
       IRCaptureCache.SetAOTIRRenamer(CacheRenamer);
     }
 
+    void AppendThunkDefinitions(std::vector<FEXCore::IR::ThunkDefinition> const& Definitions);
+
     FEXCore::Utils::PooledAllocatorMMap OpDispatcherAllocator;
     FEXCore::Utils::PooledAllocatorMMap FrontendAllocator;
 
@@ -350,7 +369,7 @@ namespace FEXCore::Context {
     bool StartPaused = false;
     bool IsMemoryShared = false;
     FEX_CONFIG_OPT(AppFilename, APP_FILENAME);
-    
+
     std::shared_mutex CustomIRMutex;
     std::unordered_map<uint64_t, std::tuple<std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)>, void *, void *>> CustomIRHandlers;
     FEXCore::CPU::CPUBackendFeatures BackendFeatures;

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64.cpp

@@ -3,6 +3,7 @@
 
 #include <aarch64/cpu-aarch64.h>
 
+#include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Telemetry.h>
 
@@ -1986,7 +1987,8 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
         DesiredFunction = NEGDesired;
         break;
       default:
-        LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}", AtomicOp);
+        LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}",
+                          ToUnderlying(AtomicOp));
         return false;
     }
 
@@ -2039,7 +2041,8 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
         DesiredFunction = NEGDesired;
         break;
       default:
-        LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}", AtomicOp);
+        LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}",
+                          ToUnderlying(AtomicOp));
         return false;
     }
 
@@ -2092,7 +2095,8 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
         DesiredFunction = NEGDesired;
         break;
       default:
-        LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}", AtomicOp);
+        LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}",
+                          ToUnderlying(AtomicOp));
         return false;
     }
 

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp

@@ -209,19 +209,29 @@ void Arm64Emitter::SpillStaticRegs(bool FPRs, uint32_t GPRSpillMask, uint32_t FP
     }
 
     if (FPRs) {
-      for (size_t i = 0; i < SRAFPR.size(); i+=2) {
-        auto Reg1 = SRAFPR[i];
-        auto Reg2 = SRAFPR[i+1];
+      if (EmitterCTX->HostFeatures.SupportsAVX) {
+        for (size_t i = 0; i < SRAFPR.size(); i++) {
+          const auto Reg = SRAFPR[i];
 
-        if (((1U << Reg1.GetCode()) & FPRSpillMask) &&
-            ((1U << Reg2.GetCode()) & FPRSpillMask)) {
-          stp(Reg1.Q(), Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
+          if (((1U << Reg.GetCode()) & FPRSpillMask) != 0) {
+            str(Reg.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.avx.data[i][0])));
+          }
         }
-        else if (((1U << Reg1.GetCode()) & FPRSpillMask)) {
-          str(Reg1.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
-        }
-        else if (((1U << Reg2.GetCode()) & FPRSpillMask)) {
-          str(Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i+1][0])));
+      } else {
+        for (size_t i = 0; i < SRAFPR.size(); i += 2) {
+          const auto Reg1 = SRAFPR[i];
+          const auto Reg2 = SRAFPR[i + 1];
+
+          if (((1U << Reg1.GetCode()) & FPRSpillMask) &&
+              ((1U << Reg2.GetCode()) & FPRSpillMask)) {
+            stp(Reg1.Q(), Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0])));
+          }
+          else if (((1U << Reg1.GetCode()) & FPRSpillMask)) {
+            str(Reg1.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0])));
+          }
+          else if (((1U << Reg2.GetCode()) & FPRSpillMask)) {
+            str(Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i+1][0])));
+          }
         }
       }
     }
@@ -246,19 +256,29 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
     }
 
     if (FPRs) {
-      for (size_t i = 0; i < SRAFPR.size(); i+=2) {
-        auto Reg1 = SRAFPR[i];
-        auto Reg2 = SRAFPR[i+1];
+      if (EmitterCTX->HostFeatures.SupportsAVX) {
+        for (size_t i = 0; i < SRAFPR.size(); i++) {
+          const auto Reg = SRAFPR[i];
 
-        if (((1U << Reg1.GetCode()) & FPRFillMask) &&
-            ((1U << Reg2.GetCode()) & FPRFillMask)) {
-          ldp(Reg1.Q(), Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
+          if (((1U << Reg.GetCode()) & FPRFillMask) != 0) {
+            ldr(Reg.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.avx.data[i][0])));
+          }
         }
-        else if (((1U << Reg1.GetCode()) & FPRFillMask)) {
-          ldr(Reg1.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
-        }
-        else if (((1U << Reg2.GetCode()) & FPRFillMask)) {
-          ldr(Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i+1][0])));
+      } else {
+        for (size_t i = 0; i < SRAFPR.size(); i += 2) {
+          const auto Reg1 = SRAFPR[i];
+          const auto Reg2 = SRAFPR[i + 1];
+
+          if (((1U << Reg1.GetCode()) & FPRFillMask) &&
+              ((1U << Reg2.GetCode()) & FPRFillMask)) {
+            ldp(Reg1.Q(), Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0])));
+          }
+          else if (((1U << Reg1.GetCode()) & FPRFillMask)) {
+            ldr(Reg1.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0])));
+          }
+          else if (((1U << Reg2.GetCode()) & FPRFillMask)) {
+            ldr(Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i+1][0])));
+          }
         }
       }
     }

External/FEXCore/Source/Interface/Core/ArchHelpers/MContext.h

@@ -124,7 +124,7 @@ static inline void SetArmReg(void* ucontext, uint32_t id, uint64_t val) {
 static inline __uint128_t GetArmFPR(void* ucontext, uint32_t id) {
   auto MContext = GetMContext(ucontext);
   HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&MContext->__reserved[0]);
-  LOGMAN_THROW_A_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic);
+  LOGMAN_THROW_AA_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic);
 
   return HostState->FPRs[id];
 }
@@ -143,7 +143,7 @@ static inline void BackupContext(void* ucontext, T *Backup) {
 
     // Host FPR state starts at _mcontext->reserved[0];
     HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
-    LOGMAN_THROW_A_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic);
+    LOGMAN_THROW_AA_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic);
     Backup->FPSR = HostState->FPSR;
     Backup->FPCR = HostState->FPCR;
     memcpy(&Backup->FPRs[0], &HostState->FPRs[0], 32 * sizeof(__uint128_t));
@@ -163,7 +163,7 @@ static inline void RestoreContext(void* ucontext, T *Backup) {
    auto _mcontext = GetMContext(ucontext);
 
     HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
-    LOGMAN_THROW_A_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic);
+    LOGMAN_THROW_AA_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic);
     memcpy(&HostState->FPRs[0], &Backup->FPRs[0], 32 * sizeof(__uint128_t));
     HostState->FPCR = Backup->FPCR;
     HostState->FPSR = Backup->FPSR;

External/FEXCore/Source/Interface/Core/CPUBackend.cpp

@@ -58,8 +58,8 @@ auto CPUBackend::AllocateNewCodeBuffer(size_t Size) -> CodeBuffer {
   Buffer.Size = Size;
   Buffer.Ptr = static_cast<uint8_t *>(
       FEXCore::Allocator::mmap(nullptr, Buffer.Size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
-  LOGMAN_THROW_A_FMT(!!Buffer.Ptr, "Couldn't allocate code buffer");
-  
+  LOGMAN_THROW_AA_FMT(!!Buffer.Ptr, "Couldn't allocate code buffer");
+
   if (ThreadState->CTX->Config.GlobalJITNaming()) {
     ThreadState->CTX->Symbols.RegisterJITSpace(Buffer.Ptr, Buffer.Size);
   }
@@ -84,4 +84,4 @@ bool CPUBackend::IsAddressInCodeBuffer(uintptr_t Address) const {
 }
 
 }
-}
+}

External/FEXCore/Source/Interface/Core/CPUID.cpp

@@ -8,11 +8,11 @@ $end_info$
 #include "Common/StringConv.h"
 #include "Interface/Context/Context.h"
 #include "Interface/Core/CPUID.h"
-#include "Interface/Core/HostFeatures.h"
 #include "Utils/FileLoading.h"
 
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CPUID.h>
+#include <FEXCore/Core/HostFeatures.h>
 #include <FEXHeaderUtils/Syscalls.h>
 
 #include "git_version.h"
@@ -39,6 +39,7 @@ namespace ProductNames {
   static const char ARM_A78C[] = "Cortex-A78C";
   static const char ARM_A710[] = "Cortex-A710";
   static const char ARM_X1[] = "Cortex-X1";
+  static const char ARM_X1C[] = "Cortex-X1C";
   static const char ARM_X2[] = "Cortex-X2";
   static const char ARM_N1[] = "Neoverse N1";
   static const char ARM_N2[] = "Neoverse N2";
@@ -83,7 +84,10 @@ static uint32_t CalculateNumberOfCPUs() {
   return CPUs;
 }
 
+// TODO: Replace usages with CTX->HostFeatures.EnableAVX
+//       when AVX implementations are further along.
 constexpr uint32_t SUPPORTS_AVX = 0;
+
 // #define CPUID_AMD
 #ifdef CPUID_AMD
 constexpr uint32_t FAMILY_IDENTIFIER =
@@ -151,7 +155,7 @@ void CPUIDEmu::SetupHostHybridFlag() {
   // CPU priority order
   // This is mostly arbitrary but will sort by some sort of CPU priority by performance
   // Relative list so things they will commonly end up in big.little configurations sort of relate
-  static constexpr std::array<CPUMIDR, 35> CPUMIDRs = {{
+  static constexpr std::array<CPUMIDR, 36> CPUMIDRs = {{
     // Typically big CPU cores
     {0x61, 0x023, 1, ProductNames::ARM_Firestorm}, // Apple M1 Firestorm
 
@@ -161,6 +165,7 @@ void CPUIDEmu::SetupHostHybridFlag() {
     {0x41, 0xd49, 1, ProductNames::ARM_N2}, // N2
     {0x41, 0xd48, 1, ProductNames::ARM_X2}, // X2
     {0x41, 0xd47, 1, ProductNames::ARM_A710}, // A710
+    {0x41, 0xd4C, 1, ProductNames::ARM_X1C}, // X1C
     {0x41, 0xd44, 1, ProductNames::ARM_X1}, // X1
     {0x41, 0xd42, 1, ProductNames::ARM_A78AE}, // A78AE
     {0x41, 0xd41, 1, ProductNames::ARM_A78}, // A78

External/FEXCore/Source/Interface/Core/Core.cpp

@@ -154,6 +154,16 @@ namespace FEXCore::Context {
     if (Config.CacheObjectCodeCompilation() != FEXCore::Config::ConfigObjectCodeHandler::CONFIG_NONE) {
       CodeObjectCacheService = std::make_unique<FEXCore::CodeSerialize::CodeObjectSerializeService>(this);
     }
+    if (!Config.EnableAVX) {
+      HostFeatures.SupportsAVX = false;
+    }
+
+    if (Config.BlockJITNaming() ||
+        Config.GlobalJITNaming() ||
+        Config.LibraryJITNaming()) {
+      // Only initialize symbols file if enabled. Ensures we don't pollute /tmp with empty files.
+      Symbols.InitFile();
+    }
   }
 
   Context::~Context() {
@@ -184,9 +194,11 @@ namespace FEXCore::Context {
       greg = 0;
     }
 
-    for (auto& xmm : NewThreadState.xmm) {
+    for (auto& xmm : NewThreadState.xmm.avx.data) {
       xmm[0] = 0xDEADBEEFULL;
       xmm[1] = 0xBAD0DAD1ULL;
+      xmm[2] = 0xDEADCAFEULL;
+      xmm[3] = 0xBAD2CAD3ULL;
     }
     memset(NewThreadState.flags, 0, Core::CPUState::NUM_EFLAG_BITS);
     NewThreadState.flags[1] = 1;
@@ -495,10 +507,21 @@ namespace FEXCore::Context {
     ExecutionThreadHandler *Arg = reinterpret_cast<ExecutionThreadHandler*>(FEXCore::Allocator::malloc(sizeof(ExecutionThreadHandler)));
     Arg->This = this;
     Arg->Thread = Thread;
+    Thread->StartPaused = NeedToCheckXID;
     Thread->ExecutionThread = FEXCore::Threads::Thread::Create(ThreadHandler, Arg);
 
     // Wait for the thread to have started
     Thread->ThreadWaiting.Wait();
+
+    if (NeedToCheckXID) {
+      // The first time an application creates a thread, GLIBC installs their SETXID signal handler.
+      // FEX needs to capture all signals and defer them to the guest.
+      // Once FEX creates its first guest thread, overwrite the GLIBC SETXID handler *again* to ensure
+      // FEX maintains control of the signal handler on this signal.
+      NeedToCheckXID = false;
+      SignalDelegation->CheckXIDHandler();
+      Thread->StartRunning.NotifyAll();
+    }
   }
 
   void Context::InitializeThreadTLSData(FEXCore::Core::InternalThreadState *Thread) {
@@ -546,7 +569,7 @@ namespace FEXCore::Context {
       break;
 #endif
     case FEXCore::Config::CONFIG_IRJIT:
-      Thread->PassManager->InsertRegisterAllocationPass(DoSRA);
+      Thread->PassManager->InsertRegisterAllocationPass(DoSRA, HostFeatures.SupportsAVX);
 
 #if (_M_X86_64 && JIT_X86_64)
       Thread->CPUBackend = FEXCore::CPU::CreateX86JITCore(this, Thread);
@@ -762,6 +785,13 @@ namespace FEXCore::Context {
         // Reset any block-specific state
         Thread->OpDispatcher->StartNewBlock();
 
+        if (Config.x86dec_SynchronizeRIPOnAllBlocks) {
+          // Ensure the RIP is synchronized to the context on block entry.
+          // In the case of block linking, the RIP may not have synchronized.
+          auto NewRIP = Thread->OpDispatcher->_EntrypointOffset(Block.Entry - GuestRIP, GPRSize);
+          Thread->OpDispatcher->_StoreContext(GPRSize, IR::GPRClass, NewRIP, offsetof(FEXCore::Core::CPUState, rip));
+        }
+
         uint64_t InstsInBlock = Block.NumInstructions;
 
         for (size_t i = 0; i < InstsInBlock; ++i) {
@@ -775,7 +805,7 @@ namespace FEXCore::Context {
           if (ExtendedDebugInfo) {
             Thread->OpDispatcher->_GuestOpcode(Block.Entry + BlockInstructionsLength - GuestRIP);
           }
-          
+
           if (Config.SMCChecks == FEXCore::Config::CONFIG_SMC_FULL) {
             auto ExistingCodePtr = reinterpret_cast<uint64_t*>(Block.Entry + BlockInstructionsLength);
 
@@ -788,7 +818,7 @@ namespace FEXCore::Context {
             Thread->OpDispatcher->SetTrueJumpTarget(InvalidateCodeCond, CodeWasChangedBlock);
 
             Thread->OpDispatcher->SetCurrentCodeBlock(CodeWasChangedBlock);
-            Thread->OpDispatcher->_RemoveThreadCodeEntry();
+            Thread->OpDispatcher->_ThreadRemoveCodeEntry();
             Thread->OpDispatcher->_ExitFunction(Thread->OpDispatcher->_EntrypointOffset(Block.Entry + BlockInstructionsLength - GuestRIP, GPRSize));
 
             auto NextOpBlock = Thread->OpDispatcher->CreateNewCodeBlockAfter(CurrentBlock);
@@ -1090,7 +1120,7 @@ namespace FEXCore::Context {
     // Now notify the thread that we are initialized
     Thread->ThreadWaiting.NotifyAll();
 
-    if (Thread != Thread->CTX->ParentThread || StartPaused) {
+    if (Thread != Thread->CTX->ParentThread || StartPaused || Thread->StartPaused) {
       // Parent thread doesn't need to wait to run
       Thread->StartRunning.Wait();
     }
@@ -1144,13 +1174,13 @@ namespace FEXCore::Context {
 
     for (auto it = lower; it != upper; it++) {
       for (auto Address: it->second) {
-        Context::RemoveThreadCodeEntry(Thread, Address);
+        Context::ThreadRemoveCodeEntry(Thread, Address);
       }
       it->second.clear();
     }
   }
 
-  void InvalidateGuestCodeRange(FEXCore::Context::Context *CTX, uint64_t Start, uint64_t Length) {
+  static void InvalidateGuestCodeRangeInternal(FEXCore::Context::Context *CTX, uint64_t Start, uint64_t Length) {
     std::lock_guard lk(CTX->ThreadCreationMutex);
     
     for (auto &Thread : CTX->Threads) {
@@ -1158,10 +1188,16 @@ namespace FEXCore::Context {
     }
   }
 
-  void InvalidateGuestCodeRange(FEXCore::Context::Context *CTX, uint64_t Start, uint64_t Length, std::function<void(uint64_t start, uint64_t Length)> CallAfter) {
-    std::unique_lock CodeInvalidationLock(CTX->CodeInvalidationMutex);
+  void InvalidateGuestCodeRange(FEXCore::Context::Context *CTX, uint64_t Start, uint64_t Length) {
+    FHU::ScopedSignalMaskWithUniqueLock CodeInvalidationLock(CTX->CodeInvalidationMutex);
+    
+    InvalidateGuestCodeRangeInternal(CTX, Start, Length);
+  }
 
-    InvalidateGuestCodeRange(CTX, Start, Length);
+  void InvalidateGuestCodeRange(FEXCore::Context::Context *CTX, uint64_t Start, uint64_t Length, std::function<void(uint64_t start, uint64_t Length)> CallAfter) {
+    FHU::ScopedSignalMaskWithUniqueLock CodeInvalidationLock(CTX->CodeInvalidationMutex);
+
+    InvalidateGuestCodeRangeInternal(CTX, Start, Length);
     CallAfter(Start, Length);
   }
 
@@ -1191,7 +1227,15 @@ namespace FEXCore::Context {
     CTX->MarkMemoryShared();
   }
 
-  void Context::RemoveThreadCodeEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
+  void Context::ThreadAddBlockLink(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestDestination, uintptr_t HostLink, const std::function<void()> &delinker) {
+    std::shared_lock lk(Thread->CTX->CodeInvalidationMutex);
+
+    Thread->LookupCache->AddBlockLink(GuestDestination, HostLink, delinker);
+  }
+
+  void Context::ThreadRemoveCodeEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {   
+    LogMan::Throw::AFmt(Thread->CTX->CodeInvalidationMutex.try_lock() == false, "CodeInvalidationMutex needs to be unique_locked here");
+    
     std::lock_guard<std::recursive_mutex> lk(Thread->LookupCache->WriteLock);
 
     Thread->DebugStore.erase(GuestRIP);
@@ -1230,7 +1274,7 @@ namespace FEXCore::Context {
     Thread->CurrentFrame->State.rip = RIP;
 
     // Erase the RIP from all the storage backings if it exists
-    RemoveThreadCodeEntry(Thread, RIP);
+    ThreadRemoveCodeEntry(Thread, RIP);
 
     // We don't care if compilation passes or not
     CompileBlock(Thread->CurrentFrame, RIP);
@@ -1288,8 +1332,13 @@ namespace FEXCore::Context {
     }
   }
 
+
+  void Context::AppendThunkDefinitions(std::vector<FEXCore::IR::ThunkDefinition> const& Definitions) {
+    ThunkHandler->AppendThunkDefinitions(Definitions);
+  }
+
   void ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, std::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) {
     Thread->FrontendDecoder->SetExternalBranches(ExternalBranches);
     Thread->FrontendDecoder->SetSectionMaxAddress(SectionMaxAddress);
   }
-}
+}

External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp

@@ -42,8 +42,7 @@ static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
 #define STATE x28
 
 Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const DispatcherConfig &config)
-  : FEXCore::CPU::Dispatcher(ctx), Arm64Emitter(ctx, MAX_DISPATCHER_CODE_SIZE)
-  , config(config) {
+  : FEXCore::CPU::Dispatcher(ctx, config), Arm64Emitter(ctx, MAX_DISPATCHER_CODE_SIZE) {
   SetAllowAssembler(true);
 
   DispatchPtr = GetCursorAddress<AsmDispatch>();
@@ -301,7 +300,7 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
   {
     // Guest SIGILL handler
     // Needs to be distinct from the SignalHandlerReturnAddress
-    UnimplementedInstructionAddress = GetCursorAddress<uint64_t>();
+    GuestSignal_SIGILL  = GetCursorAddress<uint64_t>();
 
     if (config.StaticRegisterAllocation)
       SpillStaticRegs();
@@ -310,26 +309,29 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
   }
 
   {
-    // Guest Overflow handler
+    // Guest SIGTRAP handler
     // Needs to be distinct from the SignalHandlerReturnAddress
-    OverflowExceptionInstructionAddress = GetCursorAddress<uint64_t>();
+    GuestSignal_SIGTRAP  = GetCursorAddress<uint64_t>();
 
     if (config.StaticRegisterAllocation)
       SpillStaticRegs();
 
-    LoadConstant(w1, 1);
-    strb(w1, STATE_PTR(CpuStateFrame, SynchronousFaultData.FaultToTopAndGeneratedException));
-    LoadConstant(w1, X86State::X86_TRAPNO_OF);
-    str(w1, STATE_PTR(CpuStateFrame, SynchronousFaultData.TrapNo));
-    LoadConstant(w1, 0x80);
-    str(w1, STATE_PTR(CpuStateFrame, SynchronousFaultData.si_code));
-    LoadConstant(x1, 0);
-    str(w1, STATE_PTR(CpuStateFrame, SynchronousFaultData.err_code));
+    brk(0);
+  }
+
+  {
+    // Guest Overflow handler
+    // Needs to be distinct from the SignalHandlerReturnAddress
+    GuestSignal_SIGSEGV = GetCursorAddress<uint64_t>();
+
+    if (config.StaticRegisterAllocation)
+      SpillStaticRegs();
 
     // hlt/udf = SIGILL
     // brk = SIGTRAP
     // ??? = SIGSEGV
     // Force a SIGSEGV by loading zero
+    LoadConstant(x1, 0);
     ldr(x1, MemOperand(x1));
   }
 
@@ -543,7 +545,7 @@ size_t Arm64Dispatcher::GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t Gues
 }
 
 size_t Arm64Dispatcher::GenerateInterpreterTrampoline(uint8_t *CodeBuffer) {
-  LOGMAN_THROW_A_FMT(!config.StaticRegisterAllocation, "GenerateInterpreterTrampoline dispatcher does not support SRA");
+  LOGMAN_THROW_AA_FMT(!config.StaticRegisterAllocation, "GenerateInterpreterTrampoline dispatcher does not support SRA");
   
   *emit.GetBuffer() = vixl::CodeBuffer(CodeBuffer, MaxInterpreterTrampolineSize);
 
@@ -570,7 +572,7 @@ size_t Arm64Dispatcher::GenerateInterpreterTrampoline(uint8_t *CodeBuffer) {
 }
 
 void Arm64Dispatcher::SpillSRA(FEXCore::Core::InternalThreadState *Thread, void *ucontext, uint32_t IgnoreMask) {
-  for(int i = 0; i < SRA64.size(); i++) {
+  for (size_t i = 0; i < SRA64.size(); i++) {
     if (IgnoreMask & (1U << SRA64[i].GetCode())) {
       // Skip this one, it's already spilled
       continue;
@@ -578,9 +580,16 @@ void Arm64Dispatcher::SpillSRA(FEXCore::Core::InternalThreadState *Thread, void
     Thread->CurrentFrame->State.gregs[i] = ArchHelpers::Context::GetArmReg(ucontext, SRA64[i].GetCode());
   }
 
-  for(int i = 0; i < SRAFPR.size(); i++) {
-    auto FPR = ArchHelpers::Context::GetArmFPR(ucontext, SRAFPR[i].GetCode());
-    memcpy(&Thread->CurrentFrame->State.xmm[i][0], &FPR, sizeof(__uint128_t));
+  if (EmitterCTX->HostFeatures.SupportsAVX) {
+    for (size_t i = 0; i < SRAFPR.size(); i++) {
+      auto FPR = ArchHelpers::Context::GetArmFPR(ucontext, SRAFPR[i].GetCode());
+      memcpy(&Thread->CurrentFrame->State.xmm.avx.data[i][0], &FPR, sizeof(__uint128_t));
+    }
+  } else {
+    for (size_t i = 0; i < SRAFPR.size(); i++) {
+      auto FPR = ArchHelpers::Context::GetArmFPR(ucontext, SRAFPR[i].GetCode());
+      memcpy(&Thread->CurrentFrame->State.xmm.sse.data[i][0], &FPR, sizeof(__uint128_t));
+    }
   }
 }
 
@@ -594,8 +603,9 @@ void Arm64Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thr
     Common.ExitFunctionLinker = ExitFunctionLinkerAddress;
     Common.ThreadStopHandlerSpillSRA = ThreadStopHandlerAddressSpillSRA;
     Common.ThreadPauseHandlerSpillSRA = ThreadPauseHandlerAddressSpillSRA;
-    Common.UnimplementedInstructionHandler = UnimplementedInstructionAddress;
-    Common.OverflowExceptionHandler = OverflowExceptionInstructionAddress;
+    Common.GuestSignal_SIGILL = GuestSignal_SIGILL;
+    Common.GuestSignal_SIGTRAP = GuestSignal_SIGTRAP;
+    Common.GuestSignal_SIGSEGV = GuestSignal_SIGSEGV;
     Common.SignalReturnHandler = SignalHandlerReturnAddress;
 
     auto &AArch64 = Thread->CurrentFrame->Pointers.AArch64;
@@ -610,4 +620,4 @@ std::unique_ptr<Dispatcher> Dispatcher::CreateArm64(FEXCore::Context::Context *C
   return std::make_unique<Arm64Dispatcher>(CTX, Config);
 }
 
-}
+}

External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.h

@@ -29,7 +29,6 @@ class Arm64Dispatcher final : public Dispatcher, public Arm64Emitter {
     uint64_t LDIVHandlerAddress{};
     uint64_t LUREMHandlerAddress{};
     uint64_t LREMHandlerAddress{};
-    DispatcherConfig config;
 };
 
 }

External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp

@@ -99,6 +99,7 @@ void Dispatcher::RestoreThreadState(FEXCore::Core::InternalThreadState *Thread,
     SignalFrames.pop();
   }
 
+  const bool IsAVXEnabled = CTX->Config.EnableAVX;
   uintptr_t NewSP = OldSP;
   auto Context = reinterpret_cast<ArchHelpers::Context::ContextBackup*>(NewSP);
 
@@ -159,10 +160,22 @@ void Dispatcher::RestoreThreadState(FEXCore::Core::InternalThreadState *Thread,
             COPY_REG(RCX);
             COPY_REG(RSP);
 #undef COPY_REG
-        FEXCore::x86_64::_libc_fpstate *fpstate = reinterpret_cast<FEXCore::x86_64::_libc_fpstate*>(guest_uctx->uc_mcontext.fpregs);
+        auto *xstate = reinterpret_cast<x86_64::xstate*>(guest_uctx->uc_mcontext.fpregs);
+        auto *fpstate = &xstate->fpstate;
+
         // Copy float registers
         memcpy(Frame->State.mm, fpstate->_st, sizeof(Frame->State.mm));
-        memcpy(Frame->State.xmm, fpstate->_xmm, sizeof(Frame->State.xmm));
+
+        if (IsAVXEnabled) {
+          for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
+            memcpy(&Frame->State.xmm.avx.data[i][0], &fpstate->_xmm[i], sizeof(__uint128_t));
+          }
+          for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
+            memcpy(&Frame->State.xmm.avx.data[i][2], &xstate->ymmh.ymmh_space[i], sizeof(__uint128_t));
+          }
+        } else {
+          memcpy(Frame->State.xmm.sse.data, fpstate->_xmm, sizeof(Frame->State.xmm.sse.data));
+        }
 
         // FCW store default
         Frame->State.FCW = fpstate->fcw;
@@ -216,7 +229,8 @@ void Dispatcher::RestoreThreadState(FEXCore::Core::InternalThreadState *Thread,
         COPY_REG(RCX);
         COPY_REG(RSP);
 #undef COPY_REG
-        FEXCore::x86::_libc_fpstate *fpstate = reinterpret_cast<FEXCore::x86::_libc_fpstate*>(guest_uctx->uc_mcontext.fpregs);
+        auto *xstate = reinterpret_cast<x86::xstate*>(guest_uctx->uc_mcontext.fpregs);
+        auto *fpstate = &xstate->fpstate;
 
         // Copy float registers
         for (size_t i = 0; i < Core::CPUState::NUM_MMS; ++i) {
@@ -225,7 +239,16 @@ void Dispatcher::RestoreThreadState(FEXCore::Core::InternalThreadState *Thread,
         }
 
         // Extended XMM state
-        memcpy(fpstate->_xmm, Frame->State.xmm, sizeof(Frame->State.xmm));
+        if (IsAVXEnabled) {
+          for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
+            memcpy(&fpstate->_xmm[i], &Frame->State.xmm.avx.data[i][0], sizeof(__uint128_t));
+          }
+          for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
+            memcpy(&xstate->ymmh.ymmh_space[i], &Frame->State.xmm.avx.data[i][2], sizeof(__uint128_t));
+          }
+        } else {
+          memcpy(Frame->State.xmm.sse.data, fpstate->_xmm, sizeof(Frame->State.xmm.sse.data));
+        }
 
         // FCW store default
         Frame->State.FCW = fpstate->fcw;
@@ -274,6 +297,26 @@ static uint32_t ConvertSignalToError(int Signal, siginfo_t *HostSigInfo) {
   return 0;
 }
 
+template <typename T>
+static void SetXStateInfo(T* xstate, bool is_avx_enabled) {
+  auto* fpstate = &xstate->fpstate;
+
+  fpstate->sw_reserved.magic1 = x86_64::fpx_sw_bytes::FP_XSTATE_MAGIC;
+  fpstate->sw_reserved.extended_size = is_avx_enabled ? sizeof(T) : 0;
+
+  fpstate->sw_reserved.xfeatures |= x86_64::fpx_sw_bytes::FEATURE_FP |
+                                    x86_64::fpx_sw_bytes::FEATURE_SSE;
+  if (is_avx_enabled) {
+    fpstate->sw_reserved.xfeatures |= x86_64::fpx_sw_bytes::FEATURE_YMM;
+  }
+
+  fpstate->sw_reserved.xstate_size = fpstate->sw_reserved.extended_size;
+
+  if (is_avx_enabled) {
+    xstate->xstate_hdr.xfeatures = 0;
+  }
+}
+
 bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
   auto ContextBackup = StoreThreadState(Thread, Signal, ucontext);
 
@@ -293,13 +336,14 @@ bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, i
   uint64_t NewGuestSP = OldGuestSP;
 
   // Pulling from context here
-  bool Is64BitMode = CTX->Config.Is64BitMode;
-  uint64_t SignalReturn = CTX->X86CodeGen.SignalReturn;
+  const bool Is64BitMode = CTX->Config.Is64BitMode;
+  const bool IsAVXEnabled = CTX->Config.EnableAVX;
+  const uint64_t SignalReturn = CTX->X86CodeGen.SignalReturn;
 
   // Spill the SRA regardless of signal handler type
   // We are going to be returning to the top of the dispatcher which will fill again
   // Otherwise we might load garbage
-  if (SRAEnabled) {
+  if (config.StaticRegisterAllocation) {
     if (Thread->CPUBackend->IsAddressInCodeBuffer(OldPC)) {
       uint32_t IgnoreMask{};
 #ifdef _M_ARM_64
@@ -374,8 +418,13 @@ bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, i
   if (GuestAction->sa_flags & SA_SIGINFO) {
     // Setup ucontext a bit
     if (Is64BitMode) {
-      NewGuestSP -= sizeof(FEXCore::x86_64::_libc_fpstate);
-      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86_64::_libc_fpstate));
+      if (IsAVXEnabled) {
+        NewGuestSP -= sizeof(x86_64::xstate);
+        NewGuestSP = AlignDown(NewGuestSP, alignof(x86_64::xstate));
+      } else {
+        NewGuestSP -= sizeof(x86_64::_libc_fpstate);
+        NewGuestSP = AlignDown(NewGuestSP, alignof(x86_64::_libc_fpstate));
+      }
       uint64_t FPStateLocation = NewGuestSP;
 
       NewGuestSP -= sizeof(FEXCore::x86_64::ucontext_t);
@@ -397,8 +446,9 @@ bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, i
       guest_uctx->uc_flags = FEXCore::x86_64::UC_FP_XSTATE;
 
       // Pointer to where the fpreg memory is
-      guest_uctx->uc_mcontext.fpregs = reinterpret_cast<FEXCore::x86_64::_libc_fpstate*>(FPStateLocation);
-      FEXCore::x86_64::_libc_fpstate *fpstate = reinterpret_cast<FEXCore::x86_64::_libc_fpstate*>(FPStateLocation);
+      guest_uctx->uc_mcontext.fpregs = reinterpret_cast<x86_64::_libc_fpstate*>(FPStateLocation);
+      auto *xstate = reinterpret_cast<x86_64::xstate*>(FPStateLocation);
+      SetXStateInfo(xstate, IsAVXEnabled);
 
       guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP] = Frame->State.rip;
       guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_EFL] = 0;
@@ -415,6 +465,7 @@ bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, i
 
         // Overwrite si_code
         guest_siginfo->si_code = Thread->CurrentFrame->SynchronousFaultData.si_code;
+        Signal = Frame->SynchronousFaultData.Signal;
       }
       else {
         guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_TRAPNO] = ConvertSignalToTrapNo(Signal, HostSigInfo);
@@ -443,9 +494,21 @@ bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, i
       COPY_REG(RSP);
 #undef COPY_REG
 
+      auto* fpstate = &xstate->fpstate;
+
       // Copy float registers
       memcpy(fpstate->_st, Frame->State.mm, sizeof(Frame->State.mm));
-      memcpy(fpstate->_xmm, Frame->State.xmm, sizeof(Frame->State.xmm));
+
+      if (IsAVXEnabled) {
+        for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
+          memcpy(&fpstate->_xmm[i], &Frame->State.xmm.avx.data[i][0], sizeof(__uint128_t));
+        }
+        for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
+          memcpy(&xstate->ymmh.ymmh_space[i], &Frame->State.xmm.avx.data[i][2], sizeof(__uint128_t));
+        }
+      } else {
+        memcpy(fpstate->_xmm, Frame->State.xmm.sse.data, sizeof(Frame->State.xmm.sse.data));
+      }
 
       // FCW store default
       fpstate->fcw = Frame->State.FCW;
@@ -470,8 +533,13 @@ bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, i
     else {
       ContextBackup->Flags |= ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_32BIT;
 
-      NewGuestSP -= sizeof(FEXCore::x86::_libc_fpstate);
-      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86::_libc_fpstate));
+      if (IsAVXEnabled) {
+        NewGuestSP -= sizeof(x86::xstate);
+        NewGuestSP = AlignDown(NewGuestSP, alignof(x86::xstate));
+      } else {
+        NewGuestSP -= sizeof(x86::_libc_fpstate);
+        NewGuestSP = AlignDown(NewGuestSP, alignof(x86::_libc_fpstate));
+      }
       uint64_t FPStateLocation = NewGuestSP;
 
       NewGuestSP -= sizeof(FEXCore::x86::ucontext_t);
@@ -494,7 +562,8 @@ bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, i
 
       // Pointer to where the fpreg memory is
       guest_uctx->uc_mcontext.fpregs = static_cast<uint32_t>(FPStateLocation);
-      FEXCore::x86::_libc_fpstate *fpstate = reinterpret_cast<FEXCore::x86::_libc_fpstate*>(FPStateLocation);
+      auto *xstate = reinterpret_cast<x86::xstate*>(FPStateLocation);
+      SetXStateInfo(xstate, IsAVXEnabled);
 
       guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_GS] = Frame->State.gs;
       guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_FS] = Frame->State.fs;
@@ -504,11 +573,12 @@ bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, i
         guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_TRAPNO] = Frame->SynchronousFaultData.TrapNo;
         guest_siginfo->si_code = Frame->SynchronousFaultData.si_code;
         guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ERR] = Frame->SynchronousFaultData.err_code;
+        Signal = Frame->SynchronousFaultData.Signal;
       }
       else {
         guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_TRAPNO] = ConvertSignalToTrapNo(Signal, HostSigInfo);
         guest_siginfo->si_code = HostSigInfo->si_code;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ERR] = ConvertSignalToError(Signal, HostSigInfo);
+        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ERR] = ConvertSignalToError(Signal, HostSigInfo);
       }
       guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP] = Frame->State.rip;
       guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_CS] = Frame->State.cs;
@@ -528,6 +598,8 @@ bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, i
       COPY_REG(RSP);
 #undef COPY_REG
 
+      auto *fpstate = &xstate->fpstate;
+
       // Copy float registers
       for (size_t i = 0; i < Core::CPUState::NUM_MMS; ++i) {
         // 32-bit st register size is only 10 bytes. Not padded to 16byte like x86-64
@@ -536,7 +608,16 @@ bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, i
 
       // Extended XMM state
       fpstate->status = FEXCore::x86::fpstate_magic::MAGIC_XFPSTATE;
-      memcpy(fpstate->_xmm, Frame->State.xmm, sizeof(Frame->State.xmm));
+      if (IsAVXEnabled) {
+        for (size_t i = 0; i < std::size(Frame->State.xmm.avx.data); i++) {
+          memcpy(&fpstate->_xmm[i], &Frame->State.xmm.avx.data[i][0], sizeof(__uint128_t));
+        }
+        for (size_t i = 0; i < std::size(Frame->State.xmm.avx.data); i++) {
+          memcpy(&xstate->ymmh.ymmh_space[i], &Frame->State.xmm.avx.data[i][2], sizeof(__uint128_t));
+        }
+      } else {
+        memcpy(fpstate->_xmm, Frame->State.xmm.sse.data, sizeof(Frame->State.xmm.sse.data));
+      }
 
       // FCW store default
       fpstate->fcw = Frame->State.FCW;
@@ -619,14 +700,14 @@ bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, i
   else {
     NewGuestSP -= 4;
     *(uint32_t*)NewGuestSP = SignalReturn;
-    LOGMAN_THROW_A_FMT(SignalReturn < 0x1'0000'0000ULL, "This needs to be below 4GB");
+    LOGMAN_THROW_AA_FMT(SignalReturn < 0x1'0000'0000ULL, "This needs to be below 4GB");
     Frame->State.gregs[FEXCore::X86State::REG_RSP] = NewGuestSP;
   }
 
   // The guest starts its signal frame with a zero initialized FPU
   // Set that up now. Little bit costly but it's a requirement
   // This state will be restored on rt_sigreturn
-  memset(Frame->State.xmm, 0, sizeof(Frame->State.xmm));
+  memset(Frame->State.xmm.avx.data, 0, sizeof(Frame->State.xmm));
   memset(Frame->State.mm, 0, sizeof(Frame->State.mm));
   Frame->State.FCW = 0x37F;
   Frame->State.FTW = 0xFFFF;
@@ -665,11 +746,11 @@ bool Dispatcher::HandleSignalPause(FEXCore::Core::InternalThreadState *Thread, i
     // Store our thread state so we can come back to this
     StoreThreadState(Thread, Signal, ucontext);
 
-    if (SRAEnabled && Thread->CPUBackend->IsAddressInCodeBuffer(ArchHelpers::Context::GetPc(ucontext))) {
+    if (config.StaticRegisterAllocation && Thread->CPUBackend->IsAddressInCodeBuffer(ArchHelpers::Context::GetPc(ucontext))) {
       // We are in jit, SRA must be spilled
       ArchHelpers::Context::SetPc(ucontext, ThreadPauseHandlerAddressSpillSRA);
     } else {
-      if (SRAEnabled) {
+      if (config.StaticRegisterAllocation) {
         // We are in non-jit, SRA is already spilled
         LOGMAN_THROW_A_FMT(!IsAddressInDispatcher(ArchHelpers::Context::GetPc(ucontext)),
                            "Signals in dispatcher have unsynchronized context");
@@ -698,11 +779,11 @@ bool Dispatcher::HandleSignalPause(FEXCore::Core::InternalThreadState *Thread, i
     Thread->CurrentFrame->SignalHandlerRefCounter = 0;
 
     // Set the new PC
-    if (SRAEnabled && Thread->CPUBackend->IsAddressInCodeBuffer(ArchHelpers::Context::GetPc(ucontext))) {
+    if (config.StaticRegisterAllocation && Thread->CPUBackend->IsAddressInCodeBuffer(ArchHelpers::Context::GetPc(ucontext))) {
       // We are in jit, SRA must be spilled
       ArchHelpers::Context::SetPc(ucontext, ThreadStopHandlerAddressSpillSRA);
     } else {
-      if (SRAEnabled) {
+      if (config.StaticRegisterAllocation) {
         // We are in non-jit, SRA is already spilled
         LOGMAN_THROW_A_FMT(!IsAddressInDispatcher(ArchHelpers::Context::GetPc(ucontext)),
                            "Signals in dispatcher have unsynchronized context");

External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h

@@ -44,8 +44,9 @@ public:
   uint64_t ThreadPauseHandlerAddressSpillSRA{};
   uint64_t ExitFunctionLinkerAddress{};
   uint64_t SignalHandlerReturnAddress{};
-  uint64_t UnimplementedInstructionAddress{};
-  uint64_t OverflowExceptionInstructionAddress{};
+  uint64_t GuestSignal_SIGILL{};
+  uint64_t GuestSignal_SIGTRAP{};
+  uint64_t GuestSignal_SIGSEGV{};
   uint64_t IntCallbackReturnAddress{};
 
   uint64_t PauseReturnInstruction{};
@@ -84,18 +85,19 @@ public:
   }
 
 protected:
-  Dispatcher(FEXCore::Context::Context *ctx)
+  Dispatcher(FEXCore::Context::Context *ctx, const DispatcherConfig &Config)
     : CTX {ctx}
+    , config {Config}
     {}
 
   ArchHelpers::Context::ContextBackup* StoreThreadState(FEXCore::Core::InternalThreadState *Thread, int Signal, void *ucontext);
   void RestoreThreadState(FEXCore::Core::InternalThreadState *Thread, void *ucontext);
   std::stack<uint64_t, std::vector<uint64_t>> SignalFrames;
 
-  bool SRAEnabled = false;
   virtual void SpillSRA(FEXCore::Core::InternalThreadState *Thread, void *ucontext, uint32_t IgnoreMask) {}
 
   FEXCore::Context::Context *CTX;
+  DispatcherConfig config;
 
   static void SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::CpuStateFrame *Frame);
 

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.cpp

@@ -28,12 +28,12 @@ static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
 #define STATE r14
 
 X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, const DispatcherConfig &config)
-  : Dispatcher(ctx)
+  : Dispatcher(ctx, config)
   , Xbyak::CodeGenerator(MAX_DISPATCHER_CODE_SIZE,
       FEXCore::Allocator::mmap(nullptr, MAX_DISPATCHER_CODE_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0),
       nullptr) {
 
-  LOGMAN_THROW_A_FMT(!config.StaticRegisterAllocation, "X86 dispatcher does not support SRA");
+  LOGMAN_THROW_AA_FMT(!config.StaticRegisterAllocation, "X86 dispatcher does not support SRA");
 
   using namespace Xbyak;
   using namespace Xbyak::util;
@@ -347,24 +347,29 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, const DispatcherCon
   {
     // Guest SIGILL handler
     // Needs to be distinct from the SignalHandlerReturnAddress
-    UnimplementedInstructionAddress = getCurr<uint64_t>();
+    GuestSignal_SIGILL = getCurr<uint64_t>();
     ud2();
   }
 
   {
-    // Guest Overflow handler
+    // Guest SIGTRAP handler
     // Needs to be distinct from the SignalHandlerReturnAddress
-    OverflowExceptionInstructionAddress = getCurr<uint64_t>();
+    GuestSignal_SIGTRAP = getCurr<uint64_t>();
 
     // ud2 = SIGILL
     // int3 = SIGTRAP
     // hlt = SIGSEGV
-  
-    add(byte STATE_PTR(CpuStateFrame, SynchronousFaultData.FaultToTopAndGeneratedException), 1);
-    mov(dword STATE_PTR(CpuStateFrame, SynchronousFaultData.TrapNo), X86State::X86_TRAPNO_OF);
-    mov(dword STATE_PTR(CpuStateFrame, SynchronousFaultData.err_code), 0);
-    mov(dword STATE_PTR(CpuStateFrame, SynchronousFaultData.si_code), 0x80);
+    int3();
+  }
 
+  {
+    // Guest SIGSEGV handler
+    // Needs to be distinct from the SignalHandlerReturnAddress
+    GuestSignal_SIGSEGV = getCurr<uint64_t>();
+
+    // ud2 = SIGILL
+    // int3 = SIGTRAP
+    // hlt = SIGSEGV
     hlt();
   }
 
@@ -477,8 +482,9 @@ void X86Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Threa
     Common.ExitFunctionLinker = ExitFunctionLinkerAddress;
     Common.ThreadStopHandlerSpillSRA = ThreadStopHandlerAddress;
     Common.ThreadPauseHandlerSpillSRA = ThreadPauseHandlerAddress;
-    Common.UnimplementedInstructionHandler = UnimplementedInstructionAddress;
-    Common.OverflowExceptionHandler = OverflowExceptionInstructionAddress;
+    Common.GuestSignal_SIGILL = GuestSignal_SIGILL;
+    Common.GuestSignal_SIGTRAP = GuestSignal_SIGTRAP;
+    Common.GuestSignal_SIGSEGV = GuestSignal_SIGSEGV;
     Common.SignalReturnHandler = SignalHandlerReturnAddress;
 
     auto &Interpreter = Thread->CurrentFrame->Pointers.Interpreter;

External/FEXCore/Source/Interface/Core/Frontend.cpp

@@ -188,7 +188,7 @@ Decoder::~Decoder() {
 
 uint8_t Decoder::ReadByte() {
   uint8_t Byte = InstStream[InstructionSize];
-  LOGMAN_THROW_A_FMT(InstructionSize < MAX_INST_SIZE, "Max instruction size exceeded!");
+  LOGMAN_THROW_AA_FMT(InstructionSize < MAX_INST_SIZE, "Max instruction size exceeded!");
   Instruction[InstructionSize] = Byte;
   InstructionSize++;
   return Byte;
@@ -200,14 +200,7 @@ uint8_t Decoder::PeekByte(uint8_t Offset) const {
 }
 
 uint64_t Decoder::ReadData(uint8_t Size) {
-  if (Size == 0) {
-    return 0;
-  }
-
-  if (Size > sizeof(uint64_t)) {
-    LOGMAN_MSG_A_FMT("Unknown data size to read");
-    return 0;
-  }
+  LOGMAN_THROW_AA_FMT(Size != 0 && Size <= sizeof(uint64_t), "Unknown data size to read");
 
   uint64_t Res = 0;
   std::memcpy(&Res, &InstStream[InstructionSize], Size);
@@ -347,13 +340,15 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR
     Operand->Data.SIB.Index = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_X ? 1 : 0, SIB.index, false, false, false, false, 0b100);
     Operand->Data.SIB.Base  = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, SIB.base, false, false, false, false, ModRM.mod == 0 ? 0b101 : 16);
 
-    LOGMAN_THROW_A_FMT(Displacement <= 4, "Number of bytes should be <= 4 for literal src");
+    LOGMAN_THROW_AA_FMT(Displacement <= 4, "Number of bytes should be <= 4 for literal src");
 
-    uint64_t Literal = ReadData(Displacement);
-    if (Displacement == 1) {
-      Literal = static_cast<int8_t>(Literal);
+    if (Displacement) {
+      uint64_t Literal = ReadData(Displacement);
+      if (Displacement == 1) {
+        Literal = static_cast<int8_t>(Literal);
+      }
+      Operand->Data.SIB.Offset = Literal;
     }
-    Operand->Data.SIB.Offset = Literal;
   }
   else if (ModRM.mod == 0) {
     // Explained in Table 1-14. "Operand Addressing Using ModRM and SIB Bytes"
@@ -404,7 +399,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
     return false;
   }
 
-  LOGMAN_THROW_A_FMT(!(Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 && Info->Type <= FEXCore::X86Tables::TYPE_GROUP_P),
+  LOGMAN_THROW_AA_FMT(!(Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 && Info->Type <= FEXCore::X86Tables::TYPE_GROUP_P),
                      "Group Ops should have been decoded before this!");
 
   uint8_t DestSize{};
@@ -528,7 +523,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
   }
 
   if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_REX_IN_BYTE)) {
-    LOGMAN_THROW_A_FMT(!HasMODRM, "This instruction shouldn't have ModRM!");
+    LOGMAN_THROW_AA_FMT(!HasMODRM, "This instruction shouldn't have ModRM!");
 
     // If the REX is in the byte that means the lower nibble of the OP contains the destination GPR
     // This also means that the destination is always a GPR on these ones
@@ -637,7 +632,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
   }
 
   if (Bytes != 0) {
-    LOGMAN_THROW_A_FMT(Bytes <= 8, "Number of bytes should be <= 8 for literal src");
+    LOGMAN_THROW_AA_FMT(Bytes <= 8, "Number of bytes should be <= 8 for literal src");
 
     DecodeInst->Src[CurrentSrc].Data.Literal.Size = Bytes;
 
@@ -662,7 +657,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
     DecodeInst->Src[CurrentSrc].Data.Literal.Value = Literal;
   }
 
-  LOGMAN_THROW_A_FMT(Bytes == 0, "Inst at 0x{:x}: 0x{:04x} '{}' Had an instruction of size {} with {} remaining",
+  LOGMAN_THROW_AA_FMT(Bytes == 0, "Inst at 0x{:x}: 0x{:04x} '{}' Had an instruction of size {} with {} remaining",
                      DecodeInst->PC, DecodeInst->OP, DecodeInst->TableInfo->Name ?: "UND", InstructionSize, Bytes);
   DecodeInst->InstSize = InstructionSize;
   return true;
@@ -688,7 +683,7 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
     return false;
   }
 
-  LOGMAN_THROW_A_FMT(Info->Type != FEXCore::X86Tables::TYPE_REX_PREFIX,
+  LOGMAN_THROW_AA_FMT(Info->Type != FEXCore::X86Tables::TYPE_REX_PREFIX,
                      "REX PREFIX should have been decoded before this!");
 
   if (Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 &&
@@ -745,7 +740,7 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
         3,
       };
       uint8_t Field = RegToField[ModRM.reg];
-      LOGMAN_THROW_A_FMT(Field != 255, "Invalid field selected!");
+      LOGMAN_THROW_AA_FMT(Field != 255, "Invalid field selected!");
 
       LocalOp = (Field << 3) | ModRM.rm;
       return NormalOp(&SecondModRMTableOps[LocalOp], LocalOp);

External/FEXCore/Source/Interface/Core/GdbServer.cpp

@@ -259,7 +259,7 @@ struct FEX_PACKED GDBContextDefinition {
   uint32_t fctrl;
   uint32_t fstat;
   uint32_t dummies[6];
-  uint64_t xmm[Core::CPUState::NUM_XMMS][2];
+  uint64_t xmm[Core::CPUState::NUM_XMMS][4];
   uint32_t mxcsr;
 };
 
@@ -306,7 +306,7 @@ std::string GdbServer::readRegs() {
   GDB.fstat |= static_cast<uint32_t>(state.flags[FEXCore::X86State::X87FLAG_C2_LOC]) << 10;
   GDB.fstat |= static_cast<uint32_t>(state.flags[FEXCore::X86State::X87FLAG_C3_LOC]) << 14;
 
-  memcpy(&GDB.xmm[0], &state.xmm[0], sizeof(GDB.xmm));
+  memcpy(&GDB.xmm[0], &state.xmm.avx.data[0], sizeof(GDB.xmm));
 
   return encodeHex((unsigned char *)&GDB, sizeof(GDBContextDefinition));
 }
@@ -382,9 +382,9 @@ GdbServer::HandledPacketType GdbServer::readReg(const std::string& packet) {
   }
   else if (addr >= offsetof(GDBContextDefinition, xmm[0][0]) &&
            addr < offsetof(GDBContextDefinition, xmm[16][0])) {
-    const auto XmmIndex = (addr - offsetof(GDBContextDefinition, xmm[0][0])) / Core::CPUState::XMM_REG_SIZE;
-    const auto *Data = (unsigned char *)&state.xmm[XmmIndex][0];
-    return {encodeHex(Data, Core::CPUState::XMM_REG_SIZE), HandledPacketType::TYPE_ACK};
+    const auto XmmIndex = (addr - offsetof(GDBContextDefinition, xmm[0][0])) / Core::CPUState::XMM_AVX_REG_SIZE;
+    const auto *Data = (unsigned char *)&state.xmm.avx.data[XmmIndex][0];
+    return {encodeHex(Data, Core::CPUState::XMM_AVX_REG_SIZE), HandledPacketType::TYPE_ACK};
   }
   else if (addr == offsetof(GDBContextDefinition, mxcsr)) {
     uint32_t Empty{};
@@ -490,6 +490,30 @@ std::string buildTargetXML() {
       reg("mxcsr", "int", 32);
 
     xml << "</feature>\n";
+
+    xml << "<feature name='org.gnu.gdb.i386.avx'>";
+    xml <<
+        R"(<vector id="v4f" type="ieee_single" count="4"/>
+        <vector id="v2d" type="ieee_double" count="2"/>
+        <vector id="v16i8" type="int8" count="16"/>
+        <vector id="v8i16" type="int16" count="8"/>
+        <vector id="v4i32" type="int32" count="4"/>
+        <vector id="v2i64" type="int64" count="2"/>
+        <union id="vec128">
+          <field name="v4_float" type="v4f"/>
+          <field name="v2_double" type="v2d"/>
+          <field name="v16_int8" type="v16i8"/>
+          <field name="v8_int16" type="v8i16"/>
+          <field name="v4_int32" type="v4i32"/>
+          <field name="v2_int64" type="v2i64"/>
+          <field name="uint128" type="uint128"/>
+        </union>
+        )";
+    for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
+        reg(fmt::format("ymm{}h", i), "vec128", 128);
+    }
+    xml << "</feature>\n";
+
   xml << "</target>";
   xml << std::flush;
 

External/FEXCore/Source/Interface/Core/HostFeatures.cpp

@@ -1,5 +1,5 @@
 #include "Interface/Core/CPUID.h"
-#include "Interface/Core/HostFeatures.h"
+#include <FEXCore/Core/HostFeatures.h>
 
 #ifdef _M_ARM_64
 #include "aarch64/assembler-aarch64.h"
@@ -62,6 +62,14 @@ HostFeatures::HostFeatures() {
   SupportsRCPC = Features.Has(vixl::CPUFeatures::Feature::kRCpc);
   SupportsTSOImm9 = Features.Has(vixl::CPUFeatures::Feature::kRCpcImm);
 
+  Supports3DNow = true;
+  SupportsSSE4A = true;
+  SupportsAVX = Features.Has(vixl::CPUFeatures::Feature::kSVE2) &&
+                vixl::aarch64::CPU::ReadSVEVectorLengthInBits() >= 256;
+  SupportsSHA = true;
+  SupportsBMI1 = true;
+  SupportsBMI2 = true;
+
   // We need to get the CPU's cache line size
   // We expect sane targets that have correct cacheline sizes across clusters
   uint64_t CTR;
@@ -82,6 +90,12 @@ HostFeatures::HostFeatures() {
   SupportsRAND = Features.has(Xbyak::util::Cpu::tRDRAND) && Features.has(Xbyak::util::Cpu::tRDSEED);
   SupportsRCPC = true;
   SupportsTSOImm9 = true;
+  Supports3DNow = Features.has(Xbyak::util::Cpu::t3DN) && Features.has(Xbyak::util::Cpu::tE3DN);
+  SupportsSSE4A = Features.has(Xbyak::util::Cpu::tSSE4a);
+  SupportsAVX = true;
+  SupportsSHA = Features.has(Xbyak::util::Cpu::tSHA);
+  SupportsBMI1 = Features.has(Xbyak::util::Cpu::tBMI1);
+  SupportsBMI2 = Features.has(Xbyak::util::Cpu::tBMI2);
 
   // xbyak doesn't know how to check for CLZero
   uint32_t eax, ebx, ecx, edx;

External/FEXCore/Source/Interface/Core/Interpreter/ALUOps.cpp

@@ -20,7 +20,7 @@ DEF_OP(TruncElementPair) {
 
   switch (IROp->Size) {
     case 4: {
-      uint64_t *Src = GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
+      uint64_t *Src = GetSrc<uint64_t*>(Data->SSAData, Op->Pair);
       uint64_t Result{};
       Result = Src[0] & ~0U;
       Result |= Src[1] << 32;
@@ -69,11 +69,11 @@ DEF_OP(CycleCounter) {
 
 DEF_OP(Add) {
   auto Op = IROp->C<IR::IROp_Add>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  void *Src1 = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
-  void *Src2 = GetSrc<void*>(Data->SSAData, Op->Header.Args[1]);
-  auto Func = [](auto a, auto b) { return a + b; };
+  auto *Src1 = GetSrc<void*>(Data->SSAData, Op->Src1);
+  auto *Src2 = GetSrc<void*>(Data->SSAData, Op->Src2);
+  const auto Func = [](auto a, auto b) { return a + b; };
 
   switch (OpSize) {
     DO_OP(4, uint32_t, Func)
@@ -84,11 +84,11 @@ DEF_OP(Add) {
 
 DEF_OP(Sub) {
   auto Op = IROp->C<IR::IROp_Sub>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  void *Src1 = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
-  void *Src2 = GetSrc<void*>(Data->SSAData, Op->Header.Args[1]);
-  auto Func = [](auto a, auto b) { return a - b; };
+  void *Src1 = GetSrc<void*>(Data->SSAData, Op->Src1);
+  void *Src2 = GetSrc<void*>(Data->SSAData, Op->Src2);
+  const auto Func = [](auto a, auto b) { return a - b; };
 
   switch (OpSize) {
     DO_OP(4, uint32_t, Func)
@@ -99,9 +99,9 @@ DEF_OP(Sub) {
 
 DEF_OP(Neg) {
   auto Op = IROp->C<IR::IROp_Neg>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src = *GetSrc<int64_t*>(Data->SSAData, Op->Header.Args[0]);
+  const uint64_t Src = *GetSrc<int64_t*>(Data->SSAData, Op->Src);
   switch (OpSize) {
     case 4:
       GD = -static_cast<int32_t>(Src);
@@ -115,10 +115,10 @@ DEF_OP(Neg) {
 
 DEF_OP(Mul) {
   auto Op = IROp->C<IR::IROp_Mul>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src1);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src2);
 
   switch (OpSize) {
     case 4:
@@ -138,10 +138,10 @@ DEF_OP(Mul) {
 
 DEF_OP(UMul) {
   auto Op = IROp->C<IR::IROp_UMul>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src1);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src2);
 
   switch (OpSize) {
     case 4:
@@ -161,9 +161,9 @@ DEF_OP(UMul) {
 
 DEF_OP(Div) {
   auto Op = IROp->C<IR::IROp_Div>();
-  uint8_t OpSize = IROp->Size;
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+  const uint8_t OpSize = IROp->Size;
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src1);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src2);
 
   switch (OpSize) {
     case 1:
@@ -179,7 +179,7 @@ DEF_OP(Div) {
       GD = static_cast<int64_t>(Src1) / static_cast<int64_t>(Src2);
       break;
     case 16: {
-      __int128_t Tmp = *GetSrc<__int128_t*>(Data->SSAData, Op->Header.Args[0]) / *GetSrc<__int128_t*>(Data->SSAData, Op->Header.Args[1]);
+      __int128_t Tmp = *GetSrc<__int128_t*>(Data->SSAData, Op->Src1) / *GetSrc<__int128_t*>(Data->SSAData, Op->Src2);
       memcpy(GDP, &Tmp, 16);
       break;
     }
@@ -189,10 +189,10 @@ DEF_OP(Div) {
 
 DEF_OP(UDiv) {
   auto Op = IROp->C<IR::IROp_UDiv>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src1);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src2);
 
   switch (OpSize) {
     case 1:
@@ -208,7 +208,7 @@ DEF_OP(UDiv) {
       GD = static_cast<uint64_t>(Src1) / static_cast<uint64_t>(Src2);
       break;
     case 16: {
-      __uint128_t Tmp = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]) / *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);
+      __uint128_t Tmp = *GetSrc<__uint128_t*>(Data->SSAData, Op->Src1) / *GetSrc<__uint128_t*>(Data->SSAData, Op->Src2);
       memcpy(GDP, &Tmp, 16);
       break;
     }
@@ -218,10 +218,10 @@ DEF_OP(UDiv) {
 
 DEF_OP(Rem) {
   auto Op = IROp->C<IR::IROp_Rem>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src1);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src2);
 
   switch (OpSize) {
     case 1:
@@ -237,7 +237,7 @@ DEF_OP(Rem) {
       GD = static_cast<int64_t>(Src1) % static_cast<int64_t>(Src2);
       break;
     case 16: {
-      __int128_t Tmp = *GetSrc<__int128_t*>(Data->SSAData, Op->Header.Args[0]) % *GetSrc<__int128_t*>(Data->SSAData, Op->Header.Args[1]);
+      __int128_t Tmp = *GetSrc<__int128_t*>(Data->SSAData, Op->Src1) % *GetSrc<__int128_t*>(Data->SSAData, Op->Src2);
       memcpy(GDP, &Tmp, 16);
       break;
     }
@@ -247,10 +247,10 @@ DEF_OP(Rem) {
 
 DEF_OP(URem) {
   auto Op = IROp->C<IR::IROp_URem>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src1);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src2);
 
   switch (OpSize) {
     case 1:
@@ -266,7 +266,7 @@ DEF_OP(URem) {
       GD = static_cast<uint64_t>(Src1) % static_cast<uint64_t>(Src2);
       break;
     case 16: {
-      __uint128_t Tmp = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]) % *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);
+      __uint128_t Tmp = *GetSrc<__uint128_t*>(Data->SSAData, Op->Src1) % *GetSrc<__uint128_t*>(Data->SSAData, Op->Src2);
       memcpy(GDP, &Tmp, 16);
       break;
     }
@@ -276,10 +276,10 @@ DEF_OP(URem) {
 
 DEF_OP(MulH) {
   auto Op = IROp->C<IR::IROp_MulH>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src1);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src2);
 
   switch (OpSize) {
     case 4: {
@@ -298,10 +298,10 @@ DEF_OP(MulH) {
 
 DEF_OP(UMulH) {
   auto Op = IROp->C<IR::IROp_UMulH>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src1);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src2);
   switch (OpSize) {
     case 4:
       GD = static_cast<uint64_t>(Src1) * static_cast<uint64_t>(Src2);
@@ -324,11 +324,11 @@ DEF_OP(UMulH) {
 
 DEF_OP(Or) {
   auto Op = IROp->C<IR::IROp_Or>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  void *Src1 = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
-  void *Src2 = GetSrc<void*>(Data->SSAData, Op->Header.Args[1]);
-  auto Func = [](auto a, auto b) { return a | b; };
+  void *Src1 = GetSrc<void*>(Data->SSAData, Op->Src1);
+  void *Src2 = GetSrc<void*>(Data->SSAData, Op->Src2);
+  const auto Func = [](auto a, auto b) { return a | b; };
 
   switch (OpSize) {
     DO_OP(1, uint8_t,  Func)
@@ -342,11 +342,11 @@ DEF_OP(Or) {
 
 DEF_OP(And) {
   auto Op = IROp->C<IR::IROp_And>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  void *Src1 = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
-  void *Src2 = GetSrc<void*>(Data->SSAData, Op->Header.Args[1]);
-  auto Func = [](auto a, auto b) { return a & b; };
+  void *Src1 = GetSrc<void*>(Data->SSAData, Op->Src1);
+  void *Src2 = GetSrc<void*>(Data->SSAData, Op->Src2);
+  const auto Func = [](auto a, auto b) { return a & b; };
 
   switch (OpSize) {
     DO_OP(1, uint8_t,  Func)
@@ -361,8 +361,8 @@ DEF_OP(Andn) {
   auto Op = IROp->C<IR::IROp_Andn>();
   const uint8_t OpSize = IROp->Size;
 
-  void *Src1 = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
-  void *Src2 = GetSrc<void*>(Data->SSAData, Op->Header.Args[1]);
+  void *Src1 = GetSrc<void*>(Data->SSAData, Op->Src1);
+  void *Src2 = GetSrc<void*>(Data->SSAData, Op->Src2);
   constexpr auto Func = [](auto a, auto b) {
     using Type = decltype(a);
     return static_cast<Type>(a & static_cast<Type>(~b));
@@ -379,11 +379,11 @@ DEF_OP(Andn) {
 
 DEF_OP(Xor) {
   auto Op = IROp->C<IR::IROp_Xor>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  void *Src1 = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
-  void *Src2 = GetSrc<void*>(Data->SSAData, Op->Header.Args[1]);
-  auto Func = [](auto a, auto b) { return a ^ b; };
+  void *Src1 = GetSrc<void*>(Data->SSAData, Op->Src1);
+  void *Src2 = GetSrc<void*>(Data->SSAData, Op->Src2);
+  const auto Func = [](auto a, auto b) { return a ^ b; };
 
   switch (OpSize) {
     DO_OP(1, uint8_t,  Func)
@@ -396,11 +396,11 @@ DEF_OP(Xor) {
 
 DEF_OP(Lshl) {
   auto Op = IROp->C<IR::IROp_Lshl>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
-  uint8_t Mask = OpSize * 8 - 1;
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src1);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src2);
+  const uint8_t Mask = OpSize * 8 - 1;
   switch (OpSize) {
     case 4:
       GD = static_cast<uint32_t>(Src1) << (Src2 & Mask);
@@ -414,11 +414,11 @@ DEF_OP(Lshl) {
 
 DEF_OP(Lshr) {
   auto Op = IROp->C<IR::IROp_Lshr>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
-  uint8_t Mask = OpSize * 8 - 1;
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src1);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src2);
+  const uint8_t Mask = OpSize * 8 - 1;
   switch (OpSize) {
     case 4:
       GD = static_cast<uint32_t>(Src1) >> (Src2 & Mask);
@@ -432,11 +432,11 @@ DEF_OP(Lshr) {
 
 DEF_OP(Ashr) {
   auto Op = IROp->C<IR::IROp_Ashr>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
-  uint8_t Mask = OpSize * 8 - 1;
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src1);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src2);
+  const uint8_t Mask = OpSize * 8 - 1;
   switch (OpSize) {
     case 4:
       GD = (uint32_t)(static_cast<int32_t>(Src1) >> (Src2 & Mask));
@@ -450,12 +450,12 @@ DEF_OP(Ashr) {
 
 DEF_OP(Ror) {
   auto Op = IROp->C<IR::IROp_Ror>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
-  auto Ror = [] (auto In, auto R) {
-    auto RotateMask = sizeof(In) * 8 - 1;
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src1);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src2);
+  const auto Ror = [] (auto In, auto R) {
+    const auto RotateMask = sizeof(In) * 8 - 1;
     R &= RotateMask;
     return (In >> R) | (In << (sizeof(In) * 8 - R));
   };
@@ -474,11 +474,11 @@ DEF_OP(Ror) {
 
 DEF_OP(Extr) {
   auto Op = IROp->C<IR::IROp_Extr>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
-  auto Extr = [] (auto Src1, auto Src2, uint8_t lsb) -> decltype(Src1) {
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Upper);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Lower);
+  const auto Extr = [] (auto Src1, auto Src2, uint8_t lsb) -> decltype(Src1) {
     __uint128_t Result{};
     Result = Src1;
     Result <<= sizeof(Src1) * 8;
@@ -500,7 +500,7 @@ DEF_OP(Extr) {
 }
 
 DEF_OP(PDep) {
-  const auto Op = IROp->C<IR::IROp_PExt>();
+  const auto Op = IROp->C<IR::IROp_PDep>();
   const auto OpSize = IROp->Size;
 
   if (OpSize != 4 && OpSize != 8) {
@@ -508,10 +508,10 @@ DEF_OP(PDep) {
     return;
   }
 
-  const uint64_t Input = OpSize == 4 ? *GetSrc<uint32_t*>(Data->SSAData, Op->Args(0))
-                                     : *GetSrc<uint64_t*>(Data->SSAData, Op->Args(0));
-  uint64_t Mask = OpSize == 4 ? *GetSrc<uint32_t*>(Data->SSAData, Op->Args(1))
-                              : *GetSrc<uint64_t*>(Data->SSAData, Op->Args(1));
+  const uint64_t Input = OpSize == 4 ? *GetSrc<uint32_t*>(Data->SSAData, Op->Input)
+                                     : *GetSrc<uint64_t*>(Data->SSAData, Op->Input);
+  uint64_t Mask = OpSize == 4 ? *GetSrc<uint32_t*>(Data->SSAData, Op->Mask)
+                              : *GetSrc<uint64_t*>(Data->SSAData, Op->Mask);
 
   uint64_t Result = 0;
   for (uint64_t Index = 0; Mask > 0; Index++) {
@@ -532,10 +532,10 @@ DEF_OP(PExt) {
     return;
   }
 
-  const uint64_t Input = OpSize == 4 ? *GetSrc<uint32_t*>(Data->SSAData, Op->Args(0))
-                                     : *GetSrc<uint64_t*>(Data->SSAData, Op->Args(0));
-  uint64_t Mask = OpSize == 4 ? *GetSrc<uint32_t*>(Data->SSAData, Op->Args(1))
-                              : *GetSrc<uint64_t*>(Data->SSAData, Op->Args(1));
+  const uint64_t Input = OpSize == 4 ? *GetSrc<uint32_t*>(Data->SSAData, Op->Input)
+                                     : *GetSrc<uint64_t*>(Data->SSAData, Op->Input);
+  uint64_t Mask = OpSize == 4 ? *GetSrc<uint32_t*>(Data->SSAData, Op->Mask)
+                              : *GetSrc<uint64_t*>(Data->SSAData, Op->Mask);
 
   uint64_t Result = 0;
   for (uint64_t Offset = 0; Mask > 0; Offset++) {
@@ -549,39 +549,39 @@ DEF_OP(PExt) {
 
 DEF_OP(LDiv) {
   auto Op = IROp->C<IR::IROp_LDiv>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
   // Each source is OpSize in size
   // So you can have up to a 128bit divide from x86-64
   switch (OpSize) {
     case 2: {
-      uint16_t SrcLow = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t SrcHigh = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
-      int16_t Divisor = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[2]);
-      int32_t Source = (static_cast<uint32_t>(SrcHigh) << 16) | SrcLow;
-      int32_t Res = Source / Divisor;
+      const uint16_t SrcLow = *GetSrc<uint16_t*>(Data->SSAData, Op->Lower);
+      const uint16_t SrcHigh = *GetSrc<uint16_t*>(Data->SSAData, Op->Upper);
+      const int16_t Divisor = *GetSrc<uint16_t*>(Data->SSAData, Op->Divisor);
+      const int32_t Source = (static_cast<uint32_t>(SrcHigh) << 16) | SrcLow;
+      const int32_t Res = Source / Divisor;
 
       // We only store the lower bits of the result
       GD = static_cast<int16_t>(Res);
       break;
     }
     case 4: {
-      uint32_t SrcLow = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t SrcHigh = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
-      int32_t Divisor = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[2]);
-      int64_t Source = (static_cast<uint64_t>(SrcHigh) << 32) | SrcLow;
-      int64_t Res = Source / Divisor;
+      const uint32_t SrcLow = *GetSrc<uint32_t*>(Data->SSAData, Op->Lower);
+      const uint32_t SrcHigh = *GetSrc<uint32_t*>(Data->SSAData, Op->Upper);
+      const int32_t Divisor = *GetSrc<uint32_t*>(Data->SSAData, Op->Divisor);
+      const int64_t Source = (static_cast<uint64_t>(SrcHigh) << 32) | SrcLow;
+      const int64_t Res = Source / Divisor;
 
       // We only store the lower bits of the result
       GD = static_cast<int32_t>(Res);
       break;
     }
     case 8: {
-      uint64_t SrcLow = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t SrcHigh = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
-      int64_t Divisor = *GetSrc<int64_t*>(Data->SSAData, Op->Header.Args[2]);
-      __int128_t Source = (static_cast<__int128_t>(SrcHigh) << 64) | SrcLow;
-      __int128_t Res = Source / Divisor;
+      const uint64_t SrcLow = *GetSrc<uint64_t*>(Data->SSAData, Op->Lower);
+      const uint64_t SrcHigh = *GetSrc<uint64_t*>(Data->SSAData, Op->Upper);
+      const int64_t Divisor = *GetSrc<int64_t*>(Data->SSAData, Op->Divisor);
+      const __int128_t Source = (static_cast<__int128_t>(SrcHigh) << 64) | SrcLow;
+      const __int128_t Res = Source / Divisor;
 
       // We only store the lower bits of the result
       memcpy(GDP, &Res, OpSize);
@@ -593,39 +593,39 @@ DEF_OP(LDiv) {
 
 DEF_OP(LUDiv) {
   auto Op = IROp->C<IR::IROp_LUDiv>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
   // Each source is OpSize in size
   // So you can have up to a 128bit divide from x86-64
   switch (OpSize) {
     case 2: {
-      uint16_t SrcLow = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t SrcHigh = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
-      uint16_t Divisor = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[2]);
-      uint32_t Source = (static_cast<uint32_t>(SrcHigh) << 16) | SrcLow;
-      uint32_t Res = Source / Divisor;
+      const uint16_t SrcLow = *GetSrc<uint16_t*>(Data->SSAData, Op->Lower);
+      const uint16_t SrcHigh = *GetSrc<uint16_t*>(Data->SSAData, Op->Upper);
+      const uint16_t Divisor = *GetSrc<uint16_t*>(Data->SSAData, Op->Divisor);
+      const uint32_t Source = (static_cast<uint32_t>(SrcHigh) << 16) | SrcLow;
+      const uint32_t Res = Source / Divisor;
 
       // We only store the lower bits of the result
       GD = static_cast<uint16_t>(Res);
       break;
     }
     case 4: {
-      uint32_t SrcLow = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t SrcHigh = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
-      uint32_t Divisor = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[2]);
-      uint64_t Source = (static_cast<uint64_t>(SrcHigh) << 32) | SrcLow;
-      uint64_t Res = Source / Divisor;
+      const uint32_t SrcLow = *GetSrc<uint32_t*>(Data->SSAData, Op->Lower);
+      const uint32_t SrcHigh = *GetSrc<uint32_t*>(Data->SSAData, Op->Upper);
+      const uint32_t Divisor = *GetSrc<uint32_t*>(Data->SSAData, Op->Divisor);
+      const uint64_t Source = (static_cast<uint64_t>(SrcHigh) << 32) | SrcLow;
+      const uint64_t Res = Source / Divisor;
 
       // We only store the lower bits of the result
       GD = static_cast<uint32_t>(Res);
       break;
     }
     case 8: {
-      uint64_t SrcLow = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t SrcHigh = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
-      uint64_t Divisor = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[2]);
-      __uint128_t Source = (static_cast<__uint128_t>(SrcHigh) << 64) | SrcLow;
-      __uint128_t Res = Source / Divisor;
+      const uint64_t SrcLow = *GetSrc<uint64_t*>(Data->SSAData, Op->Lower);
+      const uint64_t SrcHigh = *GetSrc<uint64_t*>(Data->SSAData, Op->Upper);
+      const uint64_t Divisor = *GetSrc<uint64_t*>(Data->SSAData, Op->Divisor);
+      const __uint128_t Source = (static_cast<__uint128_t>(SrcHigh) << 64) | SrcLow;
+      const __uint128_t Res = Source / Divisor;
 
       // We only store the lower bits of the result
       memcpy(GDP, &Res, OpSize);
@@ -637,39 +637,39 @@ DEF_OP(LUDiv) {
 
 DEF_OP(LRem) {
   auto Op = IROp->C<IR::IROp_LRem>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
   // Each source is OpSize in size
   // So you can have up to a 128bit Remainder from x86-64
   switch (OpSize) {
     case 2: {
-      uint16_t SrcLow = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t SrcHigh = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
-      int16_t Divisor = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[2]);
-      int32_t Source = (static_cast<uint32_t>(SrcHigh) << 16) | SrcLow;
-      int32_t Res = Source % Divisor;
+      const uint16_t SrcLow = *GetSrc<uint16_t*>(Data->SSAData, Op->Lower);
+      const uint16_t SrcHigh = *GetSrc<uint16_t*>(Data->SSAData, Op->Upper);
+      const int16_t Divisor = *GetSrc<uint16_t*>(Data->SSAData, Op->Divisor);
+      const int32_t Source = (static_cast<uint32_t>(SrcHigh) << 16) | SrcLow;
+      const int32_t Res = Source % Divisor;
 
       // We only store the lower bits of the result
       GD = static_cast<int16_t>(Res);
       break;
     }
     case 4: {
-      uint32_t SrcLow = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t SrcHigh = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
-      int32_t Divisor = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[2]);
-      int64_t Source = (static_cast<uint64_t>(SrcHigh) << 32) | SrcLow;
-      int64_t Res = Source % Divisor;
+      const uint32_t SrcLow = *GetSrc<uint32_t*>(Data->SSAData, Op->Lower);
+      const uint32_t SrcHigh = *GetSrc<uint32_t*>(Data->SSAData, Op->Upper);
+      const int32_t Divisor = *GetSrc<uint32_t*>(Data->SSAData, Op->Divisor);
+      const int64_t Source = (static_cast<uint64_t>(SrcHigh) << 32) | SrcLow;
+      const int64_t Res = Source % Divisor;
 
       // We only store the lower bits of the result
       GD = static_cast<int32_t>(Res);
       break;
     }
     case 8: {
-      uint64_t SrcLow = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t SrcHigh = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
-      int64_t Divisor = *GetSrc<int64_t*>(Data->SSAData, Op->Header.Args[2]);
-      __int128_t Source = (static_cast<__int128_t>(SrcHigh) << 64) | SrcLow;
-      __int128_t Res = Source % Divisor;
+      const uint64_t SrcLow = *GetSrc<uint64_t*>(Data->SSAData, Op->Lower);
+      const uint64_t SrcHigh = *GetSrc<uint64_t*>(Data->SSAData, Op->Upper);
+      const int64_t Divisor = *GetSrc<int64_t*>(Data->SSAData, Op->Divisor);
+      const __int128_t Source = (static_cast<__int128_t>(SrcHigh) << 64) | SrcLow;
+      const __int128_t Res = Source % Divisor;
       // We only store the lower bits of the result
       memcpy(GDP, &Res, OpSize);
       break;
@@ -680,39 +680,39 @@ DEF_OP(LRem) {
 
 DEF_OP(LURem) {
   auto Op = IROp->C<IR::IROp_LURem>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
   // Each source is OpSize in size
   // So you can have up to a 128bit Remainder from x86-64
   switch (OpSize) {
     case 2: {
-      uint16_t SrcLow = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[0]);
-      uint16_t SrcHigh = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[1]);
-      uint16_t Divisor = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[2]);
-      uint32_t Source = (static_cast<uint32_t>(SrcHigh) << 16) | SrcLow;
-      uint32_t Res = Source % Divisor;
+      const uint16_t SrcLow = *GetSrc<uint16_t*>(Data->SSAData, Op->Lower);
+      const uint16_t SrcHigh = *GetSrc<uint16_t*>(Data->SSAData, Op->Upper);
+      const uint16_t Divisor = *GetSrc<uint16_t*>(Data->SSAData, Op->Divisor);
+      const uint32_t Source = (static_cast<uint32_t>(SrcHigh) << 16) | SrcLow;
+      const uint32_t Res = Source % Divisor;
 
       // We only store the lower bits of the result
       GD = static_cast<uint16_t>(Res);
       break;
     }
     case 4: {
-      uint32_t SrcLow = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[0]);
-      uint32_t SrcHigh = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[1]);
-      uint32_t Divisor = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[2]);
-      uint64_t Source = (static_cast<uint64_t>(SrcHigh) << 32) | SrcLow;
-      uint64_t Res = Source % Divisor;
+      const uint32_t SrcLow = *GetSrc<uint32_t*>(Data->SSAData, Op->Lower);
+      const uint32_t SrcHigh = *GetSrc<uint32_t*>(Data->SSAData, Op->Upper);
+      const uint32_t Divisor = *GetSrc<uint32_t*>(Data->SSAData, Op->Divisor);
+      const uint64_t Source = (static_cast<uint64_t>(SrcHigh) << 32) | SrcLow;
+      const uint64_t Res = Source % Divisor;
 
       // We only store the lower bits of the result
       GD = static_cast<uint32_t>(Res);
       break;
     }
     case 8: {
-      uint64_t SrcLow = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-      uint64_t SrcHigh = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
-      uint64_t Divisor = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[2]);
-      __uint128_t Source = (static_cast<__uint128_t>(SrcHigh) << 64) | SrcLow;
-      __uint128_t Res = Source % Divisor;
+      const uint64_t SrcLow = *GetSrc<uint64_t*>(Data->SSAData, Op->Lower);
+      const uint64_t SrcHigh = *GetSrc<uint64_t*>(Data->SSAData, Op->Upper);
+      const uint64_t Divisor = *GetSrc<uint64_t*>(Data->SSAData, Op->Divisor);
+      const __uint128_t Source = (static_cast<__uint128_t>(SrcHigh) << 64) | SrcLow;
+      const __uint128_t Res = Source % Divisor;
       // We only store the lower bits of the result
       memcpy(GDP, &Res, OpSize);
       break;
@@ -723,62 +723,62 @@ DEF_OP(LURem) {
 
 DEF_OP(Not) {
   auto Op = IROp->C<IR::IROp_Not>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
+  const uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Src);
   const uint64_t mask[9]= { 0, 0xFF, 0xFFFF, 0, 0xFFFFFFFF, 0, 0, 0, 0xFFFFFFFFFFFFFFFFULL };
-  uint64_t Mask = mask[OpSize];
+  const uint64_t Mask = mask[OpSize];
   GD = (~Src) & Mask;
 }
 
 DEF_OP(Popcount) {
   auto Op = IROp->C<IR::IROp_Popcount>();
-  uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
+  const uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Src);
   GD = std::popcount(Src);
 }
 
 DEF_OP(FindLSB) {
   auto Op = IROp->C<IR::IROp_FindLSB>();
-  uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Result = FindFirstSetBit(Src);
+  const uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Src);
+  const uint64_t Result = FindFirstSetBit(Src);
   GD = Result - 1;
 }
 
 DEF_OP(FindMSB) {
   auto Op = IROp->C<IR::IROp_FindMSB>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
   switch (OpSize) {
-    case 1: GD = (OpSize * 8 - std::countl_zero(*GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[0]))) - 1; break;
-    case 2: GD = (OpSize * 8 - std::countl_zero(*GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[0]))) - 1; break;
-    case 4: GD = (OpSize * 8 - std::countl_zero(*GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[0]))) - 1; break;
-    case 8: GD = (OpSize * 8 - std::countl_zero(*GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]))) - 1; break;
+    case 1: GD = (OpSize * 8 - std::countl_zero(*GetSrc<uint8_t*>(Data->SSAData, Op->Src))) - 1; break;
+    case 2: GD = (OpSize * 8 - std::countl_zero(*GetSrc<uint16_t*>(Data->SSAData, Op->Src))) - 1; break;
+    case 4: GD = (OpSize * 8 - std::countl_zero(*GetSrc<uint32_t*>(Data->SSAData, Op->Src))) - 1; break;
+    case 8: GD = (OpSize * 8 - std::countl_zero(*GetSrc<uint64_t*>(Data->SSAData, Op->Src))) - 1; break;
     default: LOGMAN_MSG_A_FMT("Unknown FindMSB size: {}", OpSize); break;
   }
 }
 
 DEF_OP(FindTrailingZeros) {
   auto Op = IROp->C<IR::IROp_FindTrailingZeros>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
   switch (OpSize) {
     case 1: {
-      auto Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[0]);
+      const auto Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Src);
       GD = std::countr_zero(Src);
       break;
     }
     case 2: {
-      auto Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[0]);
+      const auto Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Src);
       GD = std::countr_zero(Src);
       break;
     }
     case 4: {
-      auto Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[0]);
+      const auto Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Src);
       GD = std::countr_zero(Src);
       break;
     }
     case 8: {
-      auto Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
+      const auto Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Src);
       GD = std::countr_zero(Src);
       break;
     }
@@ -788,26 +788,26 @@ DEF_OP(FindTrailingZeros) {
 
 DEF_OP(CountLeadingZeroes) {
   auto Op = IROp->C<IR::IROp_CountLeadingZeroes>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
   switch (OpSize) {
     case 1: {
-      auto Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[0]);
+      const auto Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Src);
       GD = std::countl_zero(Src);
       break;
     }
     case 2: {
-      auto Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[0]);
+      const auto Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Src);
       GD = std::countl_zero(Src);
       break;
     }
     case 4: {
-      auto Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[0]);
+      const auto Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Src);
       GD = std::countl_zero(Src);
       break;
     }
     case 8: {
-      auto Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
+      const auto Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Src);
       GD = std::countl_zero(Src);
       break;
     }
@@ -817,12 +817,12 @@ DEF_OP(CountLeadingZeroes) {
 
 DEF_OP(Rev) {
   auto Op = IROp->C<IR::IROp_Rev>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
   switch (OpSize) {
-    case 2: GD = BSwap16(*GetSrc<uint16_t*>(Data->SSAData, Op->Header.Args[0])); break;
-    case 4: GD = BSwap32(*GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[0])); break;
-    case 8: GD = BSwap64(*GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0])); break;
+    case 2: GD = BSwap16(*GetSrc<uint16_t*>(Data->SSAData, Op->Src)); break;
+    case 4: GD = BSwap32(*GetSrc<uint32_t*>(Data->SSAData, Op->Src)); break;
+    case 8: GD = BSwap64(*GetSrc<uint64_t*>(Data->SSAData, Op->Src)); break;
     default: LOGMAN_MSG_A_FMT("Unknown REV size: {}", OpSize); break;
   }
 }
@@ -830,34 +830,36 @@ DEF_OP(Rev) {
 DEF_OP(Bfi) {
   auto Op = IROp->C<IR::IROp_Bfi>();
   uint64_t SourceMask = (1ULL << Op->Width) - 1;
-  if (Op->Width == 64)
+  if (Op->Width == 64) {
     SourceMask = ~0ULL;
-  uint64_t DestMask = ~(SourceMask << Op->lsb);
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
-  uint64_t Res = (Src1 & DestMask) | ((Src2 & SourceMask) << Op->lsb);
+  }
+  const uint64_t DestMask = ~(SourceMask << Op->lsb);
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Dest);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Src);
+  const uint64_t Res = (Src1 & DestMask) | ((Src2 & SourceMask) << Op->lsb);
   GD = Res;
 }
 
 DEF_OP(Bfe) {
   auto Op = IROp->C<IR::IROp_Bfe>();
 
-  LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size);
+  LOGMAN_THROW_AA_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size);
   uint64_t SourceMask = (1ULL << Op->Width) - 1;
-  if (Op->Width == 64)
+  if (Op->Width == 64) {
     SourceMask = ~0ULL;
+  }
   SourceMask <<= Op->lsb;
-  uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
+  const uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Src);
   GD = (Src & SourceMask) >> Op->lsb;
 }
 
 DEF_OP(Sbfe) {
   auto Op = IROp->C<IR::IROp_Sbfe>();
 
-  LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for SBFE: {}", IROp->Size);
-  int64_t Src = *GetSrc<int64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t ShiftLeftAmount = (64 - (Op->Width + Op->lsb));
-  uint64_t ShiftRightAmount = ShiftLeftAmount + Op->lsb;
+  LOGMAN_THROW_AA_FMT(IROp->Size <= 8, "OpSize is too large for SBFE: {}", IROp->Size);
+  int64_t Src = *GetSrc<int64_t*>(Data->SSAData, Op->Src);
+  const uint64_t ShiftLeftAmount = (64 - (Op->Width + Op->lsb));
+  const uint64_t ShiftRightAmount = ShiftLeftAmount + Op->lsb;
   Src <<= ShiftLeftAmount;
   Src >>= ShiftRightAmount;
   GD = Src;
@@ -865,20 +867,20 @@ DEF_OP(Sbfe) {
 
 DEF_OP(Select) {
   auto Op = IROp->C<IR::IROp_Select>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Cmp1);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Cmp2);
 
   uint64_t ArgTrue;
   uint64_t ArgFalse;
 
   if (OpSize == 4) {
-    ArgTrue = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[2]);
-    ArgFalse = *GetSrc<uint32_t*>(Data->SSAData, Op->Header.Args[3]);
+    ArgTrue = *GetSrc<uint32_t*>(Data->SSAData, Op->TrueVal);
+    ArgFalse = *GetSrc<uint32_t*>(Data->SSAData, Op->FalseVal);
   } else {
-    ArgTrue = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[2]);
-    ArgFalse = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[3]);
+    ArgTrue = *GetSrc<uint64_t*>(Data->SSAData, Op->TrueVal);
+    ArgFalse = *GetSrc<uint64_t*>(Data->SSAData, Op->FalseVal);
   }
 
   bool CompResult;
@@ -894,9 +896,9 @@ DEF_OP(Select) {
 DEF_OP(VExtractToGPR) {
   auto Op = IROp->C<IR::IROp_VExtractToGPR>();
 
-  uint32_t SourceSize = GetOpSize(Data->CurrentIR, Op->Header.Args[0]);
+  const uint32_t SourceSize = GetOpSize(Data->CurrentIR, Op->Vector);
 
-  LOGMAN_THROW_A_FMT(IROp->Size <= 16, "OpSize is too large for VExtractToGPR: {}", IROp->Size);
+  LOGMAN_THROW_AA_FMT(IROp->Size <= 16, "OpSize is too large for VExtractToGPR: {}", IROp->Size);
 
   if (SourceSize == 16) {
     __uint128_t SourceMask = (1ULL << (Op->Header.ElementSize * 8)) - 1;
@@ -904,7 +906,7 @@ DEF_OP(VExtractToGPR) {
     if (Op->Header.ElementSize == 8)
       SourceMask = ~0ULL;
 
-    __uint128_t Src = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
+    __uint128_t Src = *GetSrc<__uint128_t*>(Data->SSAData, Op->Vector);
     Src >>= Shift;
     Src &= SourceMask;
     memcpy(GDP, &Src, Op->Header.ElementSize);
@@ -915,7 +917,7 @@ DEF_OP(VExtractToGPR) {
     if (Op->Header.ElementSize == 8)
       SourceMask = ~0ULL;
 
-    uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
+    uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Vector);
     Src >>= Shift;
     Src &= SourceMask;
     GD = Src;
@@ -924,25 +926,25 @@ DEF_OP(VExtractToGPR) {
 
 DEF_OP(Float_ToGPR_ZS) {
   auto Op = IROp->C<IR::IROp_Float_ToGPR_ZS>();
-  uint16_t Conv = (IROp->Size << 8) | Op->SrcElementSize;
+  const uint16_t Conv = (IROp->Size << 8) | Op->SrcElementSize;
   switch (Conv) {
     case 0x0804: { // int64_t <- float
-      int64_t Dst = (int64_t)std::trunc(*GetSrc<float*>(Data->SSAData, Op->Header.Args[0]));
+      const int64_t Dst = (int64_t)std::trunc(*GetSrc<float*>(Data->SSAData, Op->Scalar));
       memcpy(GDP, &Dst, IROp->Size);
       break;
     }
     case 0x0808: { // int64_t <- double
-      int64_t Dst = (int64_t)std::trunc(*GetSrc<double*>(Data->SSAData, Op->Header.Args[0]));
+      const int64_t Dst = (int64_t)std::trunc(*GetSrc<double*>(Data->SSAData, Op->Scalar));
       memcpy(GDP, &Dst, IROp->Size);
       break;
     }
     case 0x0404: { // int32_t <- float
-      int32_t Dst = (int32_t)std::trunc(*GetSrc<float*>(Data->SSAData, Op->Header.Args[0]));
+      const int32_t Dst = (int32_t)std::trunc(*GetSrc<float*>(Data->SSAData, Op->Scalar));
       memcpy(GDP, &Dst, IROp->Size);
       break;
     }
     case 0x0408: { // int32_t <- double
-      int32_t Dst = (int32_t)std::trunc(*GetSrc<double*>(Data->SSAData, Op->Header.Args[0]));
+      const int32_t Dst = (int32_t)std::trunc(*GetSrc<double*>(Data->SSAData, Op->Scalar));
       memcpy(GDP, &Dst, IROp->Size);
       break;
     }
@@ -951,25 +953,25 @@ DEF_OP(Float_ToGPR_ZS) {
 
 DEF_OP(Float_ToGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_ToGPR_S>();
-  uint16_t Conv = (IROp->Size << 8) | Op->SrcElementSize;
+  const uint16_t Conv = (IROp->Size << 8) | Op->SrcElementSize;
   switch (Conv) {
     case 0x0804: { // int64_t <- float
-      int64_t Dst = (int64_t)std::nearbyint(*GetSrc<float*>(Data->SSAData, Op->Header.Args[0]));
+      const int64_t Dst = (int64_t)std::nearbyint(*GetSrc<float*>(Data->SSAData, Op->Scalar));
       memcpy(GDP, &Dst, IROp->Size);
       break;
     }
     case 0x0808: { // int64_t <- double
-      int64_t Dst = (int64_t)std::nearbyint(*GetSrc<double*>(Data->SSAData, Op->Header.Args[0]));
+      const int64_t Dst = (int64_t)std::nearbyint(*GetSrc<double*>(Data->SSAData, Op->Scalar));
       memcpy(GDP, &Dst, IROp->Size);
       break;
     }
     case 0x0404: { // int32_t <- float
-      int32_t Dst = (int32_t)std::nearbyint(*GetSrc<float*>(Data->SSAData, Op->Header.Args[0]));
+      const int32_t Dst = (int32_t)std::nearbyint(*GetSrc<float*>(Data->SSAData, Op->Scalar));
       memcpy(GDP, &Dst, IROp->Size);
       break;
     }
     case 0x0408: { // int32_t <- double
-      int32_t Dst = (int32_t)std::nearbyint(*GetSrc<double*>(Data->SSAData, Op->Header.Args[0]));
+      const int32_t Dst = (int32_t)std::nearbyint(*GetSrc<double*>(Data->SSAData, Op->Scalar));
       memcpy(GDP, &Dst, IROp->Size);
       break;
     }
@@ -980,9 +982,9 @@ DEF_OP(FCmp) {
   auto Op = IROp->C<IR::IROp_FCmp>();
   uint32_t ResultFlags{};
   if (Op->ElementSize == 4) {
-    float Src1 = *GetSrc<float*>(Data->SSAData, Op->Header.Args[0]);
-    float Src2 = *GetSrc<float*>(Data->SSAData, Op->Header.Args[1]);
-    bool Unordered = std::isnan(Src1) || std::isnan(Src2);
+    const float Src1 = *GetSrc<float*>(Data->SSAData, Op->Scalar1);
+    const float Src2 = *GetSrc<float*>(Data->SSAData, Op->Scalar2);
+    const bool Unordered = std::isnan(Src1) || std::isnan(Src2);
     if (Op->Flags & (1 << IR::FCMP_FLAG_LT)) {
       if (Unordered || (Src1 < Src2)) {
         ResultFlags |= (1 << IR::FCMP_FLAG_LT);
@@ -1000,9 +1002,9 @@ DEF_OP(FCmp) {
     }
   }
   else {
-    double Src1 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
-    double Src2 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[1]);
-    bool Unordered = std::isnan(Src1) || std::isnan(Src2);
+    const double Src1 = *GetSrc<double*>(Data->SSAData, Op->Scalar1);
+    const double Src2 = *GetSrc<double*>(Data->SSAData, Op->Scalar2);
+    const bool Unordered = std::isnan(Src1) || std::isnan(Src2);
     if (Op->Flags & (1 << IR::FCMP_FLAG_LT)) {
       if (Unordered || (Src1 < Src2)) {
         ResultFlags |= (1 << IR::FCMP_FLAG_LT);

External/FEXCore/Source/Interface/Core/Interpreter/BranchOps.cpp

@@ -42,7 +42,7 @@ DEF_OP(ExitFunction) {
   uintptr_t* ContextPtr = reinterpret_cast<uintptr_t*>(Data->State->CurrentFrame);
 
   void *ContextData = reinterpret_cast<void*>(ContextPtr);
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  void *Src = GetSrc<void*>(Data->SSAData, Op->NewRIP);
 
   memcpy(ContextData, Src, OpSize);
 
@@ -51,22 +51,22 @@ DEF_OP(ExitFunction) {
 
 DEF_OP(Jump) {
   auto Op = IROp->C<IR::IROp_Jump>();
-  uintptr_t ListBegin = Data->CurrentIR->GetListData();
-  uintptr_t DataBegin = Data->CurrentIR->GetData();
+  const uintptr_t ListBegin = Data->CurrentIR->GetListData();
+  const uintptr_t DataBegin = Data->CurrentIR->GetData();
 
-  Data->BlockIterator = IR::NodeIterator(ListBegin, DataBegin, Op->Header.Args[0]);
+  Data->BlockIterator = IR::NodeIterator(ListBegin, DataBegin, Op->TargetBlock);
   Data->BlockResults.Redo = true;
 }
 
 DEF_OP(CondJump) {
   auto Op = IROp->C<IR::IROp_CondJump>();
-  uintptr_t ListBegin = Data->CurrentIR->GetListData();
-  uintptr_t DataBegin = Data->CurrentIR->GetData();
+  const uintptr_t ListBegin = Data->CurrentIR->GetListData();
+  const uintptr_t DataBegin = Data->CurrentIR->GetData();
 
   bool CompResult;
 
-  uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Cmp1);
-  uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Cmp2);
+  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Cmp1);
+  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Cmp2);
 
   if (Op->CompareSize == 4)
     CompResult = IsConditionTrue<uint32_t, int32_t, float>(Op->Cond.Val, Src1, Src2);
@@ -127,7 +127,7 @@ DEF_OP(Thunk) {
   auto Op = IROp->C<IR::IROp_Thunk>();
 
   auto thunkFn = Data->State->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
-  thunkFn(*GetSrc<void**>(Data->SSAData, Op->Header.Args[0]));
+  thunkFn(*GetSrc<void**>(Data->SSAData, Op->ArgPtr));
 }
 
 DEF_OP(ValidateCode) {
@@ -141,15 +141,15 @@ DEF_OP(ValidateCode) {
   }
 }
 
-DEF_OP(RemoveThreadCodeEntry) {
-  Data->State->CTX->RemoveThreadCodeEntry(Data->State, Data->CurrentEntry);
+DEF_OP(ThreadRemoveCodeEntry) {
+  Data->State->CTX->ThreadRemoveCodeEntryFromJit(Data->State->CurrentFrame, Data->CurrentEntry);
 }
 
 DEF_OP(CPUID) {
   auto Op = IROp->C<IR::IROp_CPUID>();
   uint64_t *DstPtr = GetDest<uint64_t*>(Data->SSAData, Node);
-  uint64_t Arg = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
-  uint64_t Leaf = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+  const uint64_t Arg = *GetSrc<uint64_t*>(Data->SSAData, Op->Function);
+  const uint64_t Leaf = *GetSrc<uint64_t*>(Data->SSAData, Op->Leaf);
 
   auto Results = Data->State->CTX->CPUID.RunFunction(Arg, Leaf);
   memcpy(DstPtr, &Results, sizeof(uint32_t) * 4);

External/FEXCore/Source/Interface/Core/Interpreter/ConversionOps.cpp

@@ -14,10 +14,10 @@ namespace FEXCore::CPU {
 #define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
 DEF_OP(VInsGPR) {
   auto Op = IROp->C<IR::IROp_VInsGPR>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
-  __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);
+  auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->DestVector);
+  auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Src);
 
   uint64_t Offset = Op->DestIdx * Op->Header.ElementSize * 8;
   __uint128_t Mask = (1ULL << (Op->Header.ElementSize * 8)) - 1;
@@ -35,31 +35,31 @@ DEF_OP(VInsGPR) {
 
 DEF_OP(VCastFromGPR) {
   auto Op = IROp->C<IR::IROp_VCastFromGPR>();
-  memcpy(GDP, GetSrc<void*>(Data->SSAData, Op->Header.Args[0]), Op->Header.ElementSize);
+  memcpy(GDP, GetSrc<void*>(Data->SSAData, Op->Src), Op->Header.ElementSize);
 }
 
 DEF_OP(Float_FromGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
 
-  uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
+  const uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
   switch (Conv) {
     case 0x0404: { // Float <- int32_t
-      float Dst = (float)*GetSrc<int32_t*>(Data->SSAData, Op->Header.Args[0]);
+      const float Dst = (float)*GetSrc<int32_t*>(Data->SSAData, Op->Src);
       memcpy(GDP, &Dst, Op->Header.ElementSize);
       break;
     }
     case 0x0408: { // Float <- int64_t
-      float Dst = (float)*GetSrc<int64_t*>(Data->SSAData, Op->Header.Args[0]);
+      const float Dst = (float)*GetSrc<int64_t*>(Data->SSAData, Op->Src);
       memcpy(GDP, &Dst, Op->Header.ElementSize);
       break;
     }
     case 0x0804: { // Double <- int32_t
-      double Dst = (double)*GetSrc<int32_t*>(Data->SSAData, Op->Header.Args[0]);
+      const double Dst = (double)*GetSrc<int32_t*>(Data->SSAData, Op->Src);
       memcpy(GDP, &Dst, Op->Header.ElementSize);
       break;
     }
     case 0x0808: { // Double <- int64_t
-      double Dst = (double)*GetSrc<int64_t*>(Data->SSAData, Op->Header.Args[0]);
+      const double Dst = (double)*GetSrc<int64_t*>(Data->SSAData, Op->Src);
       memcpy(GDP, &Dst, Op->Header.ElementSize);
       break;
     }
@@ -68,15 +68,15 @@ DEF_OP(Float_FromGPR_S) {
 
 DEF_OP(Float_FToF) {
   auto Op = IROp->C<IR::IROp_Float_FToF>();
-  uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
+  const uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
   switch (Conv) {
     case 0x0804: { // Double <- Float
-      double Dst = (double)*GetSrc<float*>(Data->SSAData, Op->Header.Args[0]);
+      const double Dst = (double)*GetSrc<float*>(Data->SSAData, Op->Scalar);
       memcpy(GDP, &Dst, 8);
       break;
     }
     case 0x0408: { // Float <- Double
-      float Dst = (float)*GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
+      const float Dst = (float)*GetSrc<double*>(Data->SSAData, Op->Scalar);
       memcpy(GDP, &Dst, 4);
       break;
     }
@@ -86,14 +86,14 @@ DEF_OP(Float_FToF) {
 
 DEF_OP(Vector_SToF) {
   auto Op = IROp->C<IR::IROp_Vector_SToF>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Vector);
   uint8_t Tmp[16]{};
 
-  uint8_t Elements = OpSize / Op->Header.ElementSize;
+  const uint8_t Elements = OpSize / Op->Header.ElementSize;
 
-  auto Func = [](auto a, auto min, auto max) { return a; };
+  const auto Func = [](auto a, auto min, auto max) { return a; };
   switch (Op->Header.ElementSize) {
     DO_VECTOR_1SRC_2TYPE_OP(4, float, int32_t, Func, 0, 0)
     DO_VECTOR_1SRC_2TYPE_OP(8, double, int64_t, Func, 0, 0)
@@ -104,14 +104,14 @@ DEF_OP(Vector_SToF) {
 
 DEF_OP(Vector_FToZS) {
   auto Op = IROp->C<IR::IROp_Vector_FToZS>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Vector);
   uint8_t Tmp[16]{};
 
-  uint8_t Elements = OpSize / Op->Header.ElementSize;
+  const uint8_t Elements = OpSize / Op->Header.ElementSize;
 
-  auto Func = [](auto a, auto min, auto max) { return std::trunc(a); };
+  const auto Func = [](auto a, auto min, auto max) { return std::trunc(a); };
   switch (Op->Header.ElementSize) {
     DO_VECTOR_1SRC_2TYPE_OP(4, int32_t, float, Func, 0, 0)
     DO_VECTOR_1SRC_2TYPE_OP(8, int64_t, double, Func, 0, 0)
@@ -122,14 +122,14 @@ DEF_OP(Vector_FToZS) {
 
 DEF_OP(Vector_FToS) {
   auto Op = IROp->C<IR::IROp_Vector_FToS>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Vector);
   uint8_t Tmp[16]{};
 
-  uint8_t Elements = OpSize / Op->Header.ElementSize;
+  const uint8_t Elements = OpSize / Op->Header.ElementSize;
 
-  auto Func = [](auto a, auto min, auto max) { return std::nearbyint(a); };
+  const auto Func = [](auto a, auto min, auto max) { return std::nearbyint(a); };
   switch (Op->Header.ElementSize) {
     DO_VECTOR_1SRC_2TYPE_OP(4, int32_t, float, Func, 0, 0)
     DO_VECTOR_1SRC_2TYPE_OP(8, int64_t, double, Func, 0, 0)
@@ -140,14 +140,14 @@ DEF_OP(Vector_FToS) {
 
 DEF_OP(Vector_FToF) {
   auto Op = IROp->C<IR::IROp_Vector_FToF>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Vector);
   uint8_t Tmp[16]{};
 
-  uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
+  const uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
 
-  auto Func = [](auto a, auto min, auto max) { return a; };
+  const auto Func = [](auto a, auto min, auto max) { return a; };
   switch (Conv) {
     case 0x0804: { // Double <- float
       // Only the lower elements from the source
@@ -172,17 +172,17 @@ DEF_OP(Vector_FToF) {
 
 DEF_OP(Vector_FToI) {
   auto Op = IROp->C<IR::IROp_Vector_FToI>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Vector);
   uint8_t Tmp[16]{};
 
-  uint8_t Elements = OpSize / Op->Header.ElementSize;
-  auto Func_Nearest = [](auto a) { return std::rint(a); };
-  auto Func_Neg = [](auto a) { return std::floor(a); };
-  auto Func_Pos = [](auto a) { return std::ceil(a); };
-  auto Func_Trunc = [](auto a) { return std::trunc(a); };
-  auto Func_Host = [](auto a) { return std::rint(a); };
+  const uint8_t Elements = OpSize / Op->Header.ElementSize;
+  const auto Func_Nearest = [](auto a) { return std::rint(a); };
+  const auto Func_Neg = [](auto a) { return std::floor(a); };
+  const auto Func_Pos = [](auto a) { return std::ceil(a); };
+  const auto Func_Trunc = [](auto a) { return std::trunc(a); };
+  const auto Func_Host = [](auto a) { return std::rint(a); };
 
   switch (Op->Round) {
     case FEXCore::IR::Round_Nearest.Val:

External/FEXCore/Source/Interface/Core/Interpreter/EncryptionOps.cpp

@@ -360,7 +360,7 @@ namespace FEXCore::CPU {
 
 DEF_OP(AESImc) {
   auto Op = IROp->C<IR::IROp_VAESImc>();
-  __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
+  auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Vector);
 
   // Pseudo-code
   // Dst = InvMixColumns(STATE)
@@ -371,8 +371,8 @@ DEF_OP(AESImc) {
 
 DEF_OP(AESEnc) {
   auto Op = IROp->C<IR::IROp_VAESEnc>();
-  __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
-  __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);
+  auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->State);
+  auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Key);
 
   // Pseudo-code
   // STATE = Src1
@@ -391,8 +391,8 @@ DEF_OP(AESEnc) {
 
 DEF_OP(AESEncLast) {
   auto Op = IROp->C<IR::IROp_VAESEncLast>();
-  __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
-  __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);
+  auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->State);
+  auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Key);
 
   // Pseudo-code
   // STATE = Src1
@@ -409,8 +409,8 @@ DEF_OP(AESEncLast) {
 
 DEF_OP(AESDec) {
   auto Op = IROp->C<IR::IROp_VAESDec>();
-  __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
-  __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);
+  auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->State);
+  auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Key);
 
   // Pseudo-code
   // STATE = Src1
@@ -429,8 +429,8 @@ DEF_OP(AESDec) {
 
 DEF_OP(AESDecLast) {
   auto Op = IROp->C<IR::IROp_VAESDecLast>();
-  __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
-  __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[1]);
+  auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->State);
+  auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Key);
 
   // Pseudo-code
   // STATE = Src1
@@ -447,7 +447,7 @@ DEF_OP(AESDecLast) {
 
 DEF_OP(AESKeyGenAssist) {
   auto Op = IROp->C<IR::IROp_VAESKeyGenAssist>();
-  uint8_t *Src1 = GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[0]);
+  const uint8_t *Src1 = GetSrc<uint8_t*>(Data->SSAData, Op->Src);
 
   // Pseudo-code
   // X3 = Src1[127:96]

External/FEXCore/Source/Interface/Core/Interpreter/F80Ops.cpp

@@ -20,99 +20,90 @@ DEF_OP(F80LOADFCW) {
 
 DEF_OP(F80ADD) {
   auto Op = IROp->C<IR::IROp_F80Add>();
-  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FADD(Src1, Src2);
+  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
+  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
+  const auto Tmp = X80SoftFloat::FADD(Src1, Src2);
 
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80SUB) {
   auto Op = IROp->C<IR::IROp_F80Sub>();
-  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FSUB(Src1, Src2);
+  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
+  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
+  const auto Tmp = X80SoftFloat::FSUB(Src1, Src2);
 
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80MUL) {
   auto Op = IROp->C<IR::IROp_F80Mul>();
-  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FMUL(Src1, Src2);
+  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
+  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
+  const auto Tmp = X80SoftFloat::FMUL(Src1, Src2);
 
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80DIV) {
   auto Op = IROp->C<IR::IROp_F80Div>();
-  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FDIV(Src1, Src2);
+  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
+  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
+  const auto Tmp = X80SoftFloat::FDIV(Src1, Src2);
 
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80FYL2X) {
   auto Op = IROp->C<IR::IROp_F80FYL2X>();
-  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FYL2X(Src1, Src2);
+  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
+  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
+  const auto Tmp = X80SoftFloat::FYL2X(Src1, Src2);
 
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80ATAN) {
   auto Op = IROp->C<IR::IROp_F80ATAN>();
-  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FATAN(Src1, Src2);
+  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
+  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
+  const auto Tmp = X80SoftFloat::FATAN(Src1, Src2);
 
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80FPREM1) {
   auto Op = IROp->C<IR::IROp_F80FPREM1>();
-  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FREM1(Src1, Src2);
+  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
+  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
+  const auto Tmp = X80SoftFloat::FREM1(Src1, Src2);
 
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80FPREM) {
   auto Op = IROp->C<IR::IROp_F80FPREM>();
-  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FREM(Src1, Src2);
+  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
+  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
+  const auto Tmp = X80SoftFloat::FREM(Src1, Src2);
 
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80SCALE) {
   auto Op = IROp->C<IR::IROp_F80SCALE>();
-  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FSCALE(Src1, Src2);
+  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
+  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
+  const auto Tmp = X80SoftFloat::FSCALE(Src1, Src2);
 
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80CVT) {
   auto Op = IROp->C<IR::IROp_F80CVT>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
 
   switch (OpSize) {
     case 4: {
@@ -131,9 +122,9 @@ DEF_OP(F80CVT) {
 
 DEF_OP(F80CVTINT) {
   auto Op = IROp->C<IR::IROp_F80CVTInt>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
+  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
 
   switch (OpSize) {
     case 2: {
@@ -160,13 +151,13 @@ DEF_OP(F80CVTTO) {
 
   switch (Op->SrcSize) {
     case 4: {
-      float Src = *GetSrc<float *>(Data->SSAData, Op->Header.Args[0]);
+      float Src = *GetSrc<float *>(Data->SSAData, Op->X80Src);
       X80SoftFloat Tmp = Src;
       memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
       break;
     }
     case 8: {
-      double Src = *GetSrc<double *>(Data->SSAData, Op->Header.Args[0]);
+      double Src = *GetSrc<double *>(Data->SSAData, Op->X80Src);
       X80SoftFloat Tmp = Src;
       memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
       break;
@@ -180,13 +171,13 @@ DEF_OP(F80CVTTOINT) {
 
   switch (Op->SrcSize) {
     case 2: {
-      int16_t Src = *GetSrc<int16_t*>(Data->SSAData, Op->Header.Args[0]);
+      int16_t Src = *GetSrc<int16_t*>(Data->SSAData, Op->Src);
       X80SoftFloat Tmp = Src;
       memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
       break;
     }
     case 4: {
-      int32_t Src = *GetSrc<int32_t*>(Data->SSAData, Op->Header.Args[0]);
+      int32_t Src = *GetSrc<int32_t*>(Data->SSAData, Op->Src);
       X80SoftFloat Tmp = Src;
       memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
       break;
@@ -197,77 +188,73 @@ DEF_OP(F80CVTTOINT) {
 
 DEF_OP(F80ROUND) {
   auto Op = IROp->C<IR::IROp_F80Round>();
-  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FRNDINT(Src);
+  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
+  const auto Tmp = X80SoftFloat::FRNDINT(Src);
 
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80F2XM1) {
   auto Op = IROp->C<IR::IROp_F80F2XM1>();
-  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::F2XM1(Src);
+  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
+  const auto Tmp = X80SoftFloat::F2XM1(Src);
 
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80TAN) {
   auto Op = IROp->C<IR::IROp_F80TAN>();
-  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FTAN(Src);
+  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
+  const auto Tmp = X80SoftFloat::FTAN(Src);
 
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80SQRT) {
   auto Op = IROp->C<IR::IROp_F80SQRT>();
-  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FSQRT(Src);
+  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
+  const auto Tmp = X80SoftFloat::FSQRT(Src);
 
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80SIN) {
   auto Op = IROp->C<IR::IROp_F80SIN>();
-  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FSIN(Src);
+  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
+  const auto Tmp = X80SoftFloat::FSIN(Src);
+
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80COS) {
   auto Op = IROp->C<IR::IROp_F80COS>();
-  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FCOS(Src);
+  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
+  const auto Tmp = X80SoftFloat::FCOS(Src);
+
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80XTRACT_EXP) {
   auto Op = IROp->C<IR::IROp_F80XTRACT_EXP>();
-  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FXTRACT_EXP(Src);
+  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
+  const auto Tmp = X80SoftFloat::FXTRACT_EXP(Src);
+
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80XTRACT_SIG) {
   auto Op = IROp->C<IR::IROp_F80XTRACT_SIG>();
-  X80SoftFloat Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Tmp;
-  Tmp = X80SoftFloat::FXTRACT_SIG(Src);
+  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
+  const auto Tmp = X80SoftFloat::FXTRACT_SIG(Src);
+
   memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
 }
 
 DEF_OP(F80CMP) {
   auto Op = IROp->C<IR::IROp_F80Cmp>();
   uint32_t ResultFlags{};
-  X80SoftFloat Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]);
-  X80SoftFloat Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[1]);
+  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
+  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
   bool eq, lt, nan;
   X80SoftFloat::FCMP(Src1, Src2, &eq, &lt, &nan);
   if (Op->Flags & (1 << IR::FCMP_FLAG_LT) &&
@@ -288,7 +275,7 @@ DEF_OP(F80CMP) {
 
 DEF_OP(F80BCDLOAD) {
   auto Op = IROp->C<IR::IROp_F80BCDLoad>();
-  uint8_t *Src1 = GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[0]);
+  const uint8_t *Src1 = GetSrc<uint8_t*>(Data->SSAData, Op->X80Src);
   uint64_t BCD{};
   // We walk through each uint8_t and pull out the BCD encoding
   // Each 4bit split is a digit
@@ -323,7 +310,7 @@ DEF_OP(F80BCDLOAD) {
 
 DEF_OP(F80BCDSTORE) {
   auto Op = IROp->C<IR::IROp_F80BCDStore>();
-  X80SoftFloat Src1 = X80SoftFloat::FRNDINT(*GetSrc<X80SoftFloat*>(Data->SSAData, Op->Header.Args[0]));
+  X80SoftFloat Src1 = X80SoftFloat::FRNDINT(*GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src));
   bool Negative = Src1.Sign;
 
   // Clear the Sign bit
@@ -358,74 +345,74 @@ DEF_OP(F80BCDSTORE) {
 
 DEF_OP(F64SIN) {
   auto Op = IROp->C<IR::IROp_F64SIN>();
-  double Src = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
-  double Tmp = sin(Src);
+  const double Src = *GetSrc<double*>(Data->SSAData, Op->Src);
+  const double Tmp = sin(Src);
   memcpy(GDP, &Tmp, sizeof(double));
 }
 
 DEF_OP(F64COS) {
   auto Op = IROp->C<IR::IROp_F64COS>();
-  double Src = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
-  double Tmp = cos(Src);
+  const double Src = *GetSrc<double*>(Data->SSAData, Op->Src);
+  const double Tmp = cos(Src);
   memcpy(GDP, &Tmp, sizeof(double));
 }
 
 DEF_OP(F64TAN) {
   auto Op = IROp->C<IR::IROp_F64TAN>();
-  double Src = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
-  double Tmp = tan(Src);
+  const double Src = *GetSrc<double*>(Data->SSAData, Op->Src);
+  const double Tmp = tan(Src);
   memcpy(GDP, &Tmp, sizeof(double));
 }
 
 DEF_OP(F64F2XM1) {
   auto Op = IROp->C<IR::IROp_F64F2XM1>();
-  double Src = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
-  double Tmp = exp2(Src) - 1.0;
+  const double Src = *GetSrc<double*>(Data->SSAData, Op->Src);
+  const double Tmp = exp2(Src) - 1.0;
   memcpy(GDP, &Tmp, sizeof(double));
 }
 
 DEF_OP(F64ATAN) {
   auto Op = IROp->C<IR::IROp_F64ATAN>();
-  double Src1 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
-  double Src2 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[1]);
-  double Tmp = atan2(Src1, Src2);
+  const double Src1 = *GetSrc<double*>(Data->SSAData, Op->Src1);
+  const double Src2 = *GetSrc<double*>(Data->SSAData, Op->Src2);
+  const double Tmp = atan2(Src1, Src2);
 
   memcpy(GDP, &Tmp, sizeof(double));
 }
 
 DEF_OP(F64FPREM) {
   auto Op = IROp->C<IR::IROp_F64FPREM>();
-  double Src1 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
-  double Src2 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[1]);
-  double Tmp = fmod(Src1, Src2);
+  const double Src1 = *GetSrc<double*>(Data->SSAData, Op->Src1);
+  const double Src2 = *GetSrc<double*>(Data->SSAData, Op->Src2);
+  const double Tmp = fmod(Src1, Src2);
 
   memcpy(GDP, &Tmp, sizeof(double));
 }
 
 DEF_OP(F64FPREM1) {
   auto Op = IROp->C<IR::IROp_F64FPREM1>();
-  double Src1 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
-  double Src2 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[1]);
-  double Tmp = remainder(Src1, Src2);
+  const double Src1 = *GetSrc<double*>(Data->SSAData, Op->Src1);
+  const double Src2 = *GetSrc<double*>(Data->SSAData, Op->Src2);
+  const double Tmp = remainder(Src1, Src2);
 
   memcpy(GDP, &Tmp, sizeof(double));
 }
 
 DEF_OP(F64FYL2X) {
   auto Op = IROp->C<IR::IROp_F64FYL2X>();
-  double Src1 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
-  double Src2 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[1]);
-  double Tmp = Src2 * log2(Src1);
+  const double Src1 = *GetSrc<double*>(Data->SSAData, Op->Src);
+  const double Src2 = *GetSrc<double*>(Data->SSAData, Op->Src2);
+  const double Tmp = Src2 * log2(Src1);
 
   memcpy(GDP, &Tmp, sizeof(double));
 }
 
 DEF_OP(F64SCALE) {
   auto Op = IROp->C<IR::IROp_F64SCALE>();
-  double Src1 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
-  double Src2 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[1]);
-  double trunc = (double)(int64_t)(Src2); //truncate
-  double Tmp = Src1 * exp2(trunc);
+  const double Src1 = *GetSrc<double*>(Data->SSAData, Op->Src1);
+  const double Src2 = *GetSrc<double*>(Data->SSAData, Op->Src2);
+  const double trunc = (double)(int64_t)(Src2); //truncate
+  const double Tmp = Src1 * exp2(trunc);
 
   memcpy(GDP, &Tmp, sizeof(double));
 }

External/FEXCore/Source/Interface/Core/Interpreter/FlagOps.cpp

@@ -14,7 +14,7 @@ namespace FEXCore::CPU {
 #define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
 DEF_OP(GetHostFlag) {
   auto Op = IROp->C<IR::IROp_GetHostFlag>();
-  GD = (*GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]) >> Op->Flag) & 1;
+  GD = (*GetSrc<uint64_t*>(Data->SSAData, Op->Value) >> Op->Flag) & 1;
 }
 #undef DEF_OP
 

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterDefines.h

@@ -159,21 +159,26 @@
   break;                                            \
   }
 
+struct InterpVector256 {
+  __uint128_t Lower;
+  __uint128_t Upper;
+};
+
 template<typename Res>
 Res GetDest(void* SSAData, FEXCore::IR::OrderedNodeWrapper Op) {
-  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Op.ID().Value];
+  auto DstPtr = &reinterpret_cast<InterpVector256*>(SSAData)[Op.ID().Value];
   return reinterpret_cast<Res>(DstPtr);
 }
 
 template<typename Res>
 Res GetDest(void* SSAData, FEXCore::IR::NodeID Op) {
-  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Op.Value];
+  auto DstPtr = &reinterpret_cast<InterpVector256*>(SSAData)[Op.Value];
   return reinterpret_cast<Res>(DstPtr);
 }
 
 
 template<typename Res>
 Res GetSrc(void* SSAData, FEXCore::IR::OrderedNodeWrapper Src) {
-  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Src.ID().Value];
+  auto DstPtr = &reinterpret_cast<InterpVector256*>(SSAData)[Src.ID().Value];
   return reinterpret_cast<Res>(DstPtr);
 }

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp

@@ -1,5 +1,6 @@
 #include "Interface/Context/Context.h"
 #include "Interface/Core/CPUID.h"
+#include "InterpreterDefines.h"
 #include "InterpreterOps.h"
 #include "F80Ops.h"
 
@@ -121,7 +122,7 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] {
   REGISTER_OP(INLINESYSCALL,          InlineSyscall);
   REGISTER_OP(THUNK,                  Thunk);
   REGISTER_OP(VALIDATECODE,           ValidateCode);
-  REGISTER_OP(REMOVETHREADCODEENTRY,        RemoveThreadCodeEntry);
+  REGISTER_OP(THREADREMOVECODEENTRY,        ThreadRemoveCodeEntry);
   REGISTER_OP(CPUID,                  CPUID);
 
   // Conversion ops
@@ -336,29 +337,34 @@ void InterpreterOps::Op_NoOp(FEXCore::IR::IROp_Header *IROp, IROpData *Data, IR:
 void InterpreterOps::InterpretIR(FEXCore::Core::CpuStateFrame *Frame, FEXCore::IR::IRListView const *CurrentIR) {
   volatile void *StackEntry = alloca(0);
 
-  uintptr_t ListSize = CurrentIR->GetSSACount();
+  const uintptr_t ListSize = CurrentIR->GetSSACount();
 
   static_assert(sizeof(FEXCore::IR::IROp_Header) == 4);
   static_assert(sizeof(FEXCore::IR::OrderedNode) == 16);
 
   auto BlockEnd = CurrentIR->GetBlocks().end();
 
-  InterpreterOps::IROpData OpData{};
-  OpData.State = Frame->Thread;
-  OpData.SSAData = alloca(ListSize * 16);
-  OpData.CurrentEntry = Frame->State.rip;
-  OpData.CurrentIR = CurrentIR;
-  OpData.StackEntry = StackEntry;
-  OpData.BlockIterator = CurrentIR->GetBlocks().begin();
+  constexpr size_t ListEntrySizeInBytes = sizeof(InterpVector256);
+  const size_t SSADataSize = ListSize * ListEntrySizeInBytes;
 
-  // Clear them all to zero. Required for Zero-extend semantics
-  memset(OpData.SSAData, 0, ListSize * 16);
+  InterpreterOps::IROpData OpData{
+    .State = Frame->Thread,
+    .CurrentEntry = Frame->State.rip,
+    .CurrentIR = CurrentIR,
+    .StackEntry = StackEntry,
+    .SSAData = alloca(SSADataSize),
+    .BlockResults = {},
+    .BlockIterator = CurrentIR->GetBlocks().begin(),
+  };
+
+  // Clear all SSAData entries to zero. Required for Zero-extend semantics
+  memset(OpData.SSAData, 0, SSADataSize);
 
   while (1) {
     using namespace FEXCore::IR;
     auto [BlockNode, BlockHeader] = OpData.BlockIterator();
     auto BlockIROp = BlockHeader->CW<IROp_CodeBlock>();
-    LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
+    LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
 
     // Reset the block results per block
     memset(&OpData.BlockResults, 0, sizeof(OpData.BlockResults));

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h

@@ -151,7 +151,7 @@ namespace FEXCore::CPU {
   DEF_OP(InlineSyscall);
   DEF_OP(Thunk);
   DEF_OP(ValidateCode);
-  DEF_OP(RemoveThreadCodeEntry);
+  DEF_OP(ThreadRemoveCodeEntry);
   DEF_OP(CPUID);
 
   ///< Conversion ops

External/FEXCore/Source/Interface/Core/Interpreter/MemoryOps.cpp

@@ -59,7 +59,7 @@ DEF_OP(StoreContext) {
   ContextPtr += Op->Offset;
 
   void *MemData = reinterpret_cast<void*>(ContextPtr);
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Value);
   memcpy(MemData, Src, OpSize);
 }
 
@@ -73,7 +73,7 @@ DEF_OP(StoreRegister) {
 
 DEF_OP(LoadContextIndexed) {
   auto Op = IROp->C<IR::IROp_LoadContextIndexed>();
-  uint64_t Index = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
+  uint64_t Index = *GetSrc<uint64_t*>(Data->SSAData, Op->Index);
 
   uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
 
@@ -103,14 +103,14 @@ DEF_OP(LoadContextIndexed) {
 
 DEF_OP(StoreContextIndexed) {
   auto Op = IROp->C<IR::IROp_StoreContextIndexed>();
-  uint64_t Index = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[1]);
+  uint64_t Index = *GetSrc<uint64_t*>(Data->SSAData, Op->Index);
 
   uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
   ContextPtr += Op->BaseOffset;
   ContextPtr += Index * Op->Stride;
 
   void *MemData = reinterpret_cast<void*>(ContextPtr);
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
+  void *Src = GetSrc<void*>(Data->SSAData, Op->Value);
   memcpy(MemData, Src, IROp->Size);
 }
 
@@ -134,7 +134,7 @@ DEF_OP(LoadFlag) {
 
 DEF_OP(StoreFlag) {
   auto Op = IROp->C<IR::IROp_StoreFlag>();
-  uint8_t Arg = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[0]);
+  uint8_t Arg = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
 
   uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
   ContextPtr += offsetof(FEXCore::Core::CPUState, flags[0]);
@@ -228,9 +228,9 @@ DEF_OP(StoreMem) {
 
 DEF_OP(VLoadMemElement) {
   auto Op = IROp->C<IR::IROp_VLoadMemElement>();
-  void const *MemData = *GetSrc<void const**>(Data->SSAData, Op->Header.Args[0]);
+  void const *MemData = *GetSrc<void const**>(Data->SSAData, Op->Value);
 
-  memcpy(GDP, GetSrc<void*>(Data->SSAData, Op->Header.Args[1]), 16);
+  memcpy(GDP, GetSrc<void*>(Data->SSAData, Op->Addr), 16);
   memcpy(reinterpret_cast<void*>(reinterpret_cast<uintptr_t>(GDP) + (Op->Header.ElementSize * Op->Index)),
     MemData, Op->Header.ElementSize);
 }
@@ -238,8 +238,8 @@ DEF_OP(VLoadMemElement) {
 DEF_OP(VStoreMemElement) {
   #define STORE_DATA(x, y) \
     case x: { \
-      y *MemData = *GetSrc<y**>(Data->SSAData, Op->Header.Args[0]); \
-      memcpy(MemData, &GetSrc<y*>(Data->SSAData, Op->Header.Args[1])[Op->Index], sizeof(y)); \
+      y *MemData = *GetSrc<y**>(Data->SSAData, Op->Value); \
+      memcpy(MemData, &GetSrc<y*>(Data->SSAData, Op->Addr)[Op->Index], sizeof(y)); \
       break; \
     }
 

External/FEXCore/Source/Interface/Core/Interpreter/MiscOps.cpp

@@ -46,14 +46,26 @@ DEF_OP(Fence) {
 
 DEF_OP(Break) {
   auto Op = IROp->C<IR::IROp_Break>();
-  switch (Op->Reason) {
-    case FEXCore::IR::Break_Halt: // HLT
-      StopThread(Data->State);
+
+  Data->State->CurrentFrame->SynchronousFaultData.FaultToTopAndGeneratedException = 1;
+  Data->State->CurrentFrame->SynchronousFaultData.Signal = Op->Reason.Signal;
+  Data->State->CurrentFrame->SynchronousFaultData.TrapNo = Op->Reason.TrapNumber;
+  Data->State->CurrentFrame->SynchronousFaultData.err_code = Op->Reason.ErrorRegister;
+  Data->State->CurrentFrame->SynchronousFaultData.si_code = Op->Reason.si_code;
+
+  switch (Op->Reason.Signal) {
+  case SIGILL:
+    FHU::Syscalls::tgkill(Data->State->ThreadManager.PID, Data->State->ThreadManager.TID, SIGILL);
     break;
-    case FEXCore::IR::Break_InvalidInstruction:
-      FHU::Syscalls::tgkill(Data->State->ThreadManager.PID, Data->State->ThreadManager.TID, SIGILL);
+  case SIGTRAP:
+    FHU::Syscalls::tgkill(Data->State->ThreadManager.PID, Data->State->ThreadManager.TID, SIGTRAP);
+    break;
+  case SIGSEGV:
+    FHU::Syscalls::tgkill(Data->State->ThreadManager.PID, Data->State->ThreadManager.TID, SIGSEGV);
+    break;
+  default:
+    FHU::Syscalls::tgkill(Data->State->ThreadManager.PID, Data->State->ThreadManager.TID, SIGTRAP);
     break;
-  default: LOGMAN_MSG_A_FMT("Unknown Break Reason: {}", Op->Reason); break;
   }
 }
 
@@ -88,7 +100,7 @@ DEF_OP(GetRoundingMode) {
 
 DEF_OP(SetRoundingMode) {
   auto Op = IROp->C<IR::IROp_SetRoundingMode>();
-  uint8_t GuestRounding = *GetSrc<uint8_t*>(Data->SSAData, Op->Header.Args[0]);
+  const auto GuestRounding = *GetSrc<uint8_t*>(Data->SSAData, Op->RoundMode);
 #ifdef _M_ARM_64
   uint64_t HostRounding{};
   __asm volatile(R"(
@@ -128,16 +140,16 @@ DEF_OP(SetRoundingMode) {
 
 DEF_OP(Print) {
   auto Op = IROp->C<IR::IROp_Print>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
   if (OpSize <= 8) {
-    uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[0]);
+    const auto Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
     LogMan::Msg::IFmt(">>>> Value in Arg: 0x{:x}, {}", Src, Src);
   }
   else if (OpSize == 16) {
-    __uint128_t Src = *GetSrc<__uint128_t*>(Data->SSAData, Op->Header.Args[0]);
-    uint64_t Src0 = Src;
-    uint64_t Src1 = Src >> 64;
+    const auto Src = *GetSrc<__uint128_t*>(Data->SSAData, Op->Value);
+    const uint64_t Src0 = Src;
+    const uint64_t Src1 = Src >> 64;
     LogMan::Msg::IFmt(">>>> Value[0] in Arg: 0x{:x}, {}", Src0, Src0);
     LogMan::Msg::IFmt("     Value[1] in Arg: 0x{:x}, {}", Src1, Src1);
   }

External/FEXCore/Source/Interface/Core/Interpreter/MoveOps.cpp

@@ -14,15 +14,15 @@ namespace FEXCore::CPU {
 #define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
 DEF_OP(ExtractElementPair) {
   auto Op = IROp->C<IR::IROp_ExtractElementPair>();
-  uintptr_t Src = GetSrc<uintptr_t>(Data->SSAData, Op->Header.Args[0]);
+  const auto Src = GetSrc<uintptr_t>(Data->SSAData, Op->Pair);
   memcpy(GDP,
     reinterpret_cast<void*>(Src + Op->Header.Size * Op->Element), Op->Header.Size);
 }
 
 DEF_OP(CreateElementPair) {
   auto Op = IROp->C<IR::IROp_CreateElementPair>();
-  void *Src_Lower = GetSrc<void*>(Data->SSAData, Op->Header.Args[0]);
-  void *Src_Upper = GetSrc<void*>(Data->SSAData, Op->Header.Args[1]);
+  const void *Src_Lower = GetSrc<void*>(Data->SSAData, Op->Lower);
+  const void *Src_Upper = GetSrc<void*>(Data->SSAData, Op->Upper);
 
   uint8_t *Dst = GetDest<uint8_t*>(Data->SSAData, Node);
 
@@ -32,9 +32,9 @@ DEF_OP(CreateElementPair) {
 
 DEF_OP(Mov) {
   auto Op = IROp->C<IR::IROp_Mov>();
-  uint8_t OpSize = IROp->Size;
+  const uint8_t OpSize = IROp->Size;
 
-  memcpy(GDP, GetSrc<void*>(Data->SSAData, Op->Header.Args[0]), OpSize);
+  memcpy(GDP, GetSrc<void*>(Data->SSAData, Op->Value), OpSize);
 }
 
 #undef DEF_OP

External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp

@@ -1084,8 +1084,8 @@ DEF_OP(Bfi) {
 
 DEF_OP(Bfe) {
   auto Op = IROp->C<IR::IROp_Bfe>();
-  LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size);
-  LOGMAN_THROW_A_FMT(Op->Width != 0, "Invalid BFE width of 0");
+  LOGMAN_THROW_AA_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size);
+  LOGMAN_THROW_AA_FMT(Op->Width != 0, "Invalid BFE width of 0");
 
   auto Dst = GetReg<RA_64>(Node);
   ubfx(Dst, GetReg<RA_64>(Op->Src.ID()), Op->lsb, Op->Width);
@@ -1249,7 +1249,7 @@ DEF_OP(FCmp) {
   bool set = false;
 
   if (Op->Flags & (1 << IR::FCMP_FLAG_EQ)) {
-    LOGMAN_THROW_A_FMT(IR::FCMP_FLAG_EQ == 0, "IR::FCMP_FLAG_EQ must equal 0");
+    LOGMAN_THROW_AA_FMT(IR::FCMP_FLAG_EQ == 0, "IR::FCMP_FLAG_EQ must equal 0");
     // EQ or unordered
     cset(Dst, Condition::eq); // Z = 1
     csinc(Dst, Dst, xzr, Condition::vc); // IF !V ? Z : 1

External/FEXCore/Source/Interface/Core/JIT/Arm64/Arm64Relocations.cpp

@@ -81,7 +81,7 @@ bool Arm64JITCore::ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uin
   size_t DataIndex{};
   for (size_t j = 0; j < NumRelocations; ++j) {
     const FEXCore::CPU::Relocation *Reloc = reinterpret_cast<const FEXCore::CPU::Relocation *>(&EntryRelocations[DataIndex]);
-    LOGMAN_THROW_A_FMT((DataIndex % alignof(Relocation)) == 0, "Alignment of relocation wasn't adhered to");
+    LOGMAN_THROW_AA_FMT((DataIndex % alignof(Relocation)) == 0, "Alignment of relocation wasn't adhered to");
 
     switch (Reloc->Header.Type) {
       case FEXCore::CPU::RelocationTypes::RELOC_NAMED_SYMBOL_LITERAL: {

External/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp

@@ -436,7 +436,7 @@ DEF_OP(ValidateCode) {
   }
 }
 
-DEF_OP(RemoveThreadCodeEntry) {
+DEF_OP(ThreadRemoveCodeEntry) {
   // Arguments are passed as follows:
   // X0: Thread
   // X1: RIP
@@ -446,7 +446,7 @@ DEF_OP(RemoveThreadCodeEntry) {
   mov(x0, STATE);
   LoadConstant(x1, Entry);
 
-  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.RemoveThreadCodeEntryFromJIT)));
+  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadRemoveCodeEntryFromJIT)));
   SpillStaticRegs();
   blr(x2);
   FillStaticRegs();
@@ -492,7 +492,7 @@ void Arm64JITCore::RegisterBranchHandlers() {
   REGISTER_OP(INLINESYSCALL,     InlineSyscall);
   REGISTER_OP(THUNK,             Thunk);
   REGISTER_OP(VALIDATECODE,      ValidateCode);
-  REGISTER_OP(REMOVETHREADCODEENTRY,   RemoveThreadCodeEntry);
+  REGISTER_OP(THREADREMOVECODEENTRY,   ThreadRemoveCodeEntry);
   REGISTER_OP(CPUID,             CPUID);
 #undef REGISTER_OP
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp

@@ -27,6 +27,7 @@ $end_info$
 #include <FEXCore/Core/UContext.h>
 #include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/CompilerDefs.h>
+#include <FEXCore/Utils/EnumUtils.h>
 
 #include "Interface/Core/Interpreter/InterpreterOps.h"
 
@@ -361,7 +362,8 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) {
       case FABI_UNKNOWN:
       default:
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
-        LOGMAN_MSG_A_FMT("Unhandled IR Fallback ABI: {} {}", FEXCore::IR::GetName(IROp->Op), Info.ABI);
+        LOGMAN_MSG_A_FMT("Unhandled IR Fallback ABI: {} {}",
+                         FEXCore::IR::GetName(IROp->Op), ToUnderlying(Info.ABI));
 #endif
       break;
     }
@@ -395,7 +397,7 @@ static uint64_t Arm64JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame *Fram
     vixl::aarch64::CPU::EnsureIAndDCacheCoherency((void*)branch, 24);
 
     // Add de-linking handler
-    Thread->LookupCache->AddBlockLink(GuestRip, (uintptr_t)record, [branch, LinkerAddress]{
+    Context::Context::ThreadAddBlockLink(Thread, GuestRip, (uintptr_t)record, [branch, LinkerAddress]{
       vixl::aarch64::Assembler emit((uint8_t*)(branch), 24);
       vixl::CodeBufferCheckScope scope(&emit, 24, vixl::CodeBufferCheckScope::kDontReserveBufferSpace, vixl::CodeBufferCheckScope::kNoAssert);
       Literal l_BranchHost{LinkerAddress};
@@ -410,7 +412,7 @@ static uint64_t Arm64JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame *Fram
     record[0] = HostCode;
 
     // Add de-linking handler
-    Thread->LookupCache->AddBlockLink(GuestRip, (uintptr_t)record, [record, LinkerAddress]{
+    Context::Context::ThreadAddBlockLink(Thread, GuestRip, (uintptr_t)record, [record, LinkerAddress]{
       record[0] = LinkerAddress;
     });
   }
@@ -424,6 +426,7 @@ void Arm64JITCore::Op_NoOp(IR::IROp_Header *IROp, IR::NodeID Node) {
 Arm64JITCore::Arm64JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
   : CPUBackend(Thread, INITIAL_CODE_SIZE, MAX_CODE_SIZE)
   , Arm64Emitter(ctx, 0)
+  , HostSupportsSVE{ctx->HostFeatures.SupportsAVX}
   , CTX {ctx} {
 
   RAPass = Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA");
@@ -473,7 +476,7 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::Intern
     
     Common.PrintValue = reinterpret_cast<uint64_t>(PrintValue);
     Common.PrintVectorValue = reinterpret_cast<uint64_t>(PrintVectorValue);
-    Common.RemoveThreadCodeEntryFromJIT = reinterpret_cast<uintptr_t>(&Context::Context::RemoveThreadCodeEntryFromJit);
+    Common.ThreadRemoveCodeEntryFromJIT = reinterpret_cast<uintptr_t>(&Context::Context::ThreadRemoveCodeEntryFromJit);
     Common.CPUIDObj = reinterpret_cast<uint64_t>(&CTX->CPUID);
 
     {
@@ -483,7 +486,7 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::Intern
 
     Common.SyscallHandlerObj = reinterpret_cast<uint64_t>(CTX->SyscallHandler);
     Common.SyscallHandlerFunc = reinterpret_cast<uint64_t>(FEXCore::Context::HandleSyscall);
-    Common.ExitFunctionLink = reinterpret_cast<uintptr_t>(&Arm64JITCore_ExitFunctionLink);
+    Common.ExitFunctionLink = reinterpret_cast<uintptr_t>(&Context::Context::ThreadExitFunctionLink<Arm64JITCore_ExitFunctionLink>);
 
 
     // Fill in the fallback handlers
@@ -549,12 +552,12 @@ template<>
 aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_32>(IR::NodeID Node) const {
   auto Reg = GetPhys(Node);
 
+  LOGMAN_THROW_AA_FMT(Reg.Class == IR::GPRFixedClass.Val || Reg.Class == IR::GPRClass.Val, "Unexpected Class: {}", Reg.Class);
+
   if (Reg.Class == IR::GPRFixedClass.Val) {
     return SRA64[Reg.Reg].W();
   } else if (Reg.Class == IR::GPRClass.Val) {
     return RA64[Reg.Reg].W();
-  } else {
-    LOGMAN_THROW_A_FMT(false, "Unexpected Class: {}", Reg.Class);
   }
 
   FEX_UNREACHABLE;
@@ -564,12 +567,12 @@ template<>
 aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_64>(IR::NodeID Node) const {
   auto Reg = GetPhys(Node);
 
+  LOGMAN_THROW_AA_FMT(Reg.Class == IR::GPRFixedClass.Val || Reg.Class == IR::GPRClass.Val, "Unexpected Class: {}", Reg.Class);
+
   if (Reg.Class == IR::GPRFixedClass.Val) {
     return SRA64[Reg.Reg];
   } else if (Reg.Class == IR::GPRClass.Val) {
     return RA64[Reg.Reg];
-  } else {
-    LOGMAN_THROW_A_FMT(false, "Unexpected Class: {}", Reg.Class);
   }
 
   FEX_UNREACHABLE;
@@ -590,12 +593,12 @@ std::pair<aarch64::Register, aarch64::Register> Arm64JITCore::GetSrcPair<Arm64JI
 aarch64::VRegister Arm64JITCore::GetSrc(IR::NodeID Node) const {
   auto Reg = GetPhys(Node);
 
+  LOGMAN_THROW_AA_FMT(Reg.Class == IR::FPRFixedClass.Val || Reg.Class == IR::FPRClass.Val, "Unexpected Class: {}", Reg.Class);
+
   if (Reg.Class == IR::FPRFixedClass.Val) {
     return SRAFPR[Reg.Reg];
   } else if (Reg.Class == IR::FPRClass.Val) {
     return RAFPR[Reg.Reg];
-  } else {
-    LOGMAN_THROW_A_FMT(false, "Unexpected Class: {}", Reg.Class);
   }
 
   FEX_UNREACHABLE;
@@ -604,12 +607,12 @@ aarch64::VRegister Arm64JITCore::GetSrc(IR::NodeID Node) const {
 aarch64::VRegister Arm64JITCore::GetDst(IR::NodeID Node) const {
   auto Reg = GetPhys(Node);
 
+  LOGMAN_THROW_AA_FMT(Reg.Class == IR::FPRFixedClass.Val || Reg.Class == IR::FPRClass.Val, "Unexpected Class: {}", Reg.Class);
+
   if (Reg.Class == IR::FPRFixedClass.Val) {
     return SRAFPR[Reg.Reg];
   } else if (Reg.Class == IR::FPRClass.Val) {
     return RAFPR[Reg.Reg];
-  } else {
-    LOGMAN_THROW_A_FMT(false, "Unexpected Class: {}", Reg.Class);
   }
 
   FEX_UNREACHABLE;
@@ -665,7 +668,11 @@ bool Arm64JITCore::IsGPR(IR::NodeID Node) const {
   return Class == IR::GPRClass || Class == IR::GPRFixedClass;
 }
 
-void *Arm64JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData, bool GDBEnabled) {
+void *Arm64JITCore::CompileCode(uint64_t Entry,
+                                FEXCore::IR::IRListView const *IR,
+                                FEXCore::Core::DebugData *DebugData,
+                                FEXCore::IR::RegisterAllocationData *RAData,
+                                bool GDBEnabled) {
   using namespace aarch64;
   JumpTargets.clear();
   uint32_t SSACount = IR->GetSSACount();
@@ -732,7 +739,7 @@ void *Arm64JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IR
     using namespace FEXCore::IR;
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
     auto BlockIROp = BlockHeader->CW<FEXCore::IR::IROp_CodeBlock>();
-    LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
+    LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
 #endif
 
     auto BlockStartHostCode = GetCursorAddress<uint8_t *>();

External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h

@@ -66,6 +66,7 @@ public:
 
 private:
   FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
+  const bool HostSupportsSVE{};
 
   Label *PendingTargetLabel;
   FEXCore::Context::Context *CTX;
@@ -309,7 +310,7 @@ private:
   DEF_OP(InlineSyscall);
   DEF_OP(Thunk);
   DEF_OP(ValidateCode);
-  DEF_OP(RemoveThreadCodeEntry);
+  DEF_OP(ThreadRemoveCodeEntry);
   DEF_OP(CPUID);
 
   ///< Conversion ops

External/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp

@@ -115,30 +115,32 @@ DEF_OP(LoadRegister) {
 
     switch(Op->Header.Size) {
       case 1:
-        LOGMAN_THROW_A_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
         ubfx(GetReg<RA_64>(Node), reg, regOffs * 8, 8);
         break;
 
       case 2:
-        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
         ubfx(GetReg<RA_64>(Node), reg, 0, 16);
         break;
 
       case 4:
-        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Node).GetCode() != reg.GetCode())
           mov(GetReg<RA_32>(Node), reg.W());
         break;
 
       case 8:
-        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Node).GetCode() != reg.GetCode())
           mov(GetReg<RA_64>(Node), reg);
         break;
     }
   } else if (Op->Class == IR::FPRClass) {
-    auto regId = (Op->Offset - offsetof(Core::CpuStateFrame, State.xmm[0][0])) / Core::CPUState::XMM_REG_SIZE;
-    auto regOffs = Op->Offset & 15;
+    const auto regSize = CTX->HostFeatures.SupportsAVX ? Core::CPUState::XMM_AVX_REG_SIZE
+                                                       : Core::CPUState::XMM_SSE_REG_SIZE;
+    const auto regId = (Op->Offset - offsetof(Core::CpuStateFrame, State.xmm.avx.data[0][0])) / regSize;
+    const auto regOffs = Op->Offset & 15;
 
     LOGMAN_THROW_A_FMT(regId < SRAFPR.size(), "out of range regId");
 
@@ -147,17 +149,17 @@ DEF_OP(LoadRegister) {
 
     switch(Op->Header.Size) {
       case 1:
-        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
         mov(host.B(), guest.B());
         break;
 
       case 2:
-        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
         fmov(host.H(), guest.H());
         break;
 
       case 4:
-        LOGMAN_THROW_A_FMT((regOffs & 3) == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT((regOffs & 3) == 0, "unexpected regOffs");
         if (regOffs == 0) {
           if (host.GetCode() != guest.GetCode())
             fmov(host.S(), guest.S());
@@ -167,7 +169,7 @@ DEF_OP(LoadRegister) {
         break;
 
       case 8:
-        LOGMAN_THROW_A_FMT((regOffs & 7) == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT((regOffs & 7) == 0, "unexpected regOffs");
         if (regOffs == 0) {
           if (host.GetCode() != guest.GetCode())
             mov(host.D(), guest.D());
@@ -177,13 +179,13 @@ DEF_OP(LoadRegister) {
         break;
 
       case 16:
-        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
         if (host.GetCode() != guest.GetCode())
           mov(host.Q(), guest.Q());
         break;
     }
   } else {
-    LOGMAN_THROW_A_FMT(false, "Unhandled Op->Class {}", Op->Class);
+    LOGMAN_THROW_AA_FMT(false, "Unhandled Op->Class {}", Op->Class);
   }
 }
 
@@ -200,29 +202,31 @@ DEF_OP(StoreRegister) {
 
     switch(Op->Header.Size) {
       case 1:
-        LOGMAN_THROW_A_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), regOffs * 8, 8);
         break;
 
       case 2:
-        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), 0, 16);
         break;
 
       case 4:
-        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), 0, 32);
         break;
 
       case 8:
-        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Op->Value.ID()).GetCode() != reg.GetCode())
           mov(reg, GetReg<RA_64>(Op->Value.ID()));
         break;
     }
   } else if (Op->Class == IR::FPRClass) {
-    auto regId = (Op->Offset - offsetof(Core::CpuStateFrame, State.xmm[0][0])) / Core::CPUState::XMM_REG_SIZE;
-    auto regOffs = Op->Offset & 15;
+    const auto regSize = CTX->HostFeatures.SupportsAVX ? Core::CPUState::XMM_AVX_REG_SIZE
+                                                       : Core::CPUState::XMM_SSE_REG_SIZE;
+    const auto regId = (Op->Offset - offsetof(Core::CpuStateFrame, State.xmm.avx.data[0][0])) / regSize;
+    const auto regOffs = Op->Offset & 15;
 
     LOGMAN_THROW_A_FMT(regId < SRAFPR.size(), "regId out of range");
 
@@ -235,28 +239,28 @@ DEF_OP(StoreRegister) {
         break;
 
       case 2:
-        LOGMAN_THROW_A_FMT((regOffs & 1) == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT((regOffs & 1) == 0, "unexpected regOffs");
         ins(guest.V8H(), regOffs/2, host.V8H(), 0);
         break;
 
       case 4:
-        LOGMAN_THROW_A_FMT((regOffs & 3) == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT((regOffs & 3) == 0, "unexpected regOffs");
         ins(guest.V4S(), regOffs/4, host.V4S(), 0);
         break;
 
       case 8:
-        LOGMAN_THROW_A_FMT((regOffs & 7) == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT((regOffs & 7) == 0, "unexpected regOffs");
         ins(guest.V2D(), regOffs / 8, host.V2D(), 0);
         break;
 
       case 16:
-        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
         if (guest.GetCode() != host.GetCode())
           mov(guest.Q(), host.Q());
         break;
     }
   } else {
-    LOGMAN_THROW_A_FMT(false, "Unhandled Op->Class {}", Op->Class);
+    LOGMAN_THROW_AA_FMT(false, "Unhandled Op->Class {}", Op->Class);
   }
 }
 

External/FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp

@@ -37,43 +37,38 @@ DEF_OP(Fence) {
 
 DEF_OP(Break) {
   auto Op = IROp->C<IR::IROp_Break>();
-  switch (Op->Reason) {
-    case FEXCore::IR::Break_Unimplemented: // Hard fault
-    case FEXCore::IR::Break_Interrupt: // Guest ud2
-      hlt(4);
-      break;
-    case FEXCore::IR::Break_Overflow: // overflow
-      ResetStack();
-      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.OverflowExceptionHandler)));
-      br(TMP1);
-      break;
-    case FEXCore::IR::Break_Halt: { // HLT
-      // Time to quit
-      // Set our stack to the starting stack location
-      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)));
-      add(sp, TMP1, 0);
 
-      // Now we need to jump to the thread stop handler
-      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadStopHandlerSpillSRA)));
-      br(TMP1);
-      break;
-    }
-    case FEXCore::IR::Break_Interrupt3: { // INT3
-      ResetStack();
-      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadPauseHandlerSpillSRA)));
-      br(TMP1);
-      break;
-    }
-    case FEXCore::IR::Break_InvalidInstruction:
-    {
-      ResetStack();
+  // First we must reset the stack
+  ResetStack();
 
-      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.UnimplementedInstructionHandler)));
-      br(TMP1);
+  LoadConstant(w1, 1);
+  strb(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.FaultToTopAndGeneratedException)));
+  LoadConstant(w1, Op->Reason.Signal);
+  strb(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.Signal)));
+  LoadConstant(w1, Op->Reason.TrapNumber);
+  str(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.TrapNo)));
+  LoadConstant(w1, Op->Reason.si_code);
+  str(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.si_code)));
+  LoadConstant(x1, Op->Reason.ErrorRegister);
+  str(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.err_code)));
 
-      break;
-    }
-    default: LOGMAN_MSG_A_FMT("Unknown Break reason: {}", Op->Reason);
+  switch (Op->Reason.Signal) {
+  case SIGILL:
+    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGILL)));
+    br(TMP1);
+    break;
+  case SIGTRAP:
+    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP)));
+    br(TMP1);
+    break;
+  case SIGSEGV:
+    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGSEGV)));
+    br(TMP1);
+    break;
+  default:
+    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP)));
+    br(TMP1);
+    break;
   }
 }
 

External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp

@@ -12,17 +12,27 @@ using namespace vixl;
 using namespace vixl::aarch64;
 #define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
 DEF_OP(VectorZero) {
-  uint8_t OpSize = IROp->Size;
-  switch (OpSize) {
-    case 8: {
-      eor(GetDst(Node).V8B(), GetDst(Node).V8B(), GetDst(Node).V8B());
-      break;
+  if (HostSupportsSVE) {
+    const auto Dst = GetDst(Node).Z().VnD();
+    eor(Dst, Dst, Dst);
+  } else {
+    const uint8_t OpSize = IROp->Size;
+
+    switch (OpSize) {
+      case 8: {
+        const auto Dst = GetDst(Node).V8B();
+        eor(Dst, Dst, Dst);
+        break;
+      }
+      case 16: {
+        const auto Dst = GetDst(Node).V16B();
+        eor(Dst, Dst, Dst);
+        break;
+      }
+      default:
+        LOGMAN_MSG_A_FMT("Unknown Op Size: {}", OpSize);
+        break;
     }
-    case 16: {
-       eor(GetDst(Node).V16B(), GetDst(Node).V16B(), GetDst(Node).V16B());
-       break;
-     }
-    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", OpSize); break;
   }
 }
 
@@ -30,22 +40,44 @@ DEF_OP(VectorImm) {
   auto Op = IROp->C<IR::IROp_VectorImm>();
 
   const uint8_t OpSize = IROp->Size;
-  const uint8_t Elements = OpSize / Op->Header.ElementSize;
+  const uint8_t ElementSize = Op->Header.ElementSize;
+  const uint8_t Elements = OpSize / ElementSize;
 
-  if (Op->Header.ElementSize == 8) {
-    // movi with 64bit element size doesn't do what we want here
-    LoadConstant(TMP1.X(), Op->Immediate);
-    dup(GetDst(Node).V2D(), TMP1.X());
-  }
-  else {
-    movi(GetDst(Node).VCast(OpSize * 8, Elements), Op->Immediate);
+  if (HostSupportsSVE) {
+    const auto Dst = [&] {
+      const auto Tmp = GetDst(Node).Z();
+      switch (ElementSize) {
+      case 1:
+        return Tmp.VnB();
+      case 2:
+        return Tmp.VnH();
+      case 4:
+        return Tmp.VnS();
+      case 8:
+        return Tmp.VnD();
+      default:
+        LOGMAN_MSG_A_FMT("Unhandled element size: {}", ElementSize);
+        return Tmp;
+      }
+    }();
+
+    dup(Dst, Op->Immediate);
+  } else {
+    if (ElementSize == 8) {
+      // movi with 64bit element size doesn't do what we want here
+      LoadConstant(TMP1.X(), Op->Immediate);
+      dup(GetDst(Node).V2D(), TMP1.X());
+    }
+    else {
+      movi(GetDst(Node).VCast(OpSize * 8, Elements), Op->Immediate);
+    }
   }
 }
 
 DEF_OP(SplatVector2) {
   auto Op = IROp->C<IR::IROp_SplatVector2>();
   const uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_A_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize);
+  LOGMAN_THROW_AA_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize);
 
   const uint8_t ElementSize = OpSize / 2;
 
@@ -63,7 +95,7 @@ DEF_OP(SplatVector2) {
 DEF_OP(SplatVector4) {
   auto Op = IROp->C<IR::IROp_SplatVector4>();
   const uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_A_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize);
+  LOGMAN_THROW_AA_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize);
 
   const uint8_t ElementSize = OpSize / 4;
 
@@ -79,59 +111,149 @@ DEF_OP(SplatVector4) {
 }
 
 DEF_OP(VMov) {
-	auto Op = IROp->C<IR::IROp_VMov>();
-	const uint8_t OpSize = IROp->Size;
+  auto Op = IROp->C<IR::IROp_VMov>();
+  const uint8_t OpSize = IROp->Size;
 
-	switch (OpSize) {
-		case 1: {
-			eor(VTMP1.V16B(), VTMP1.V16B(), VTMP1.V16B());
-			mov(VTMP1.V16B(), 0, GetSrc(Op->Source.ID()).V16B(), 0);
-			mov(GetDst(Node), VTMP1);
-			break;
-		}
-		case 2: {
-			eor(VTMP1.V16B(), VTMP1.V16B(), VTMP1.V16B());
-			mov(VTMP1.V8H(), 0, GetSrc(Op->Source.ID()).V8H(), 0);
-			mov(GetDst(Node), VTMP1);
-			break;
-		}
-		case 4: {
-			eor(VTMP1.V16B(), VTMP1.V16B(), VTMP1.V16B());
-			mov(VTMP1.V4S(), 0, GetSrc(Op->Source.ID()).V4S(), 0);
-			mov(GetDst(Node), VTMP1);
-			break;
-		}
-		case 8: {
-			mov(GetDst(Node).V8B(), GetSrc(Op->Source.ID()).V8B());
-			break;
-		}
-		case 16: {
-			if (GetDst(Node).GetCode() != GetSrc(Op->Source.ID()).GetCode())
-			  mov(GetDst(Node).V16B(), GetSrc(Op->Source.ID()).V16B());
-			break;
-		}
-		default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", OpSize); break;
-	}
+  const auto Dst = GetDst(Node);
+  const auto Source = GetSrc(Op->Source.ID());
+
+  switch (OpSize) {
+    case 1: {
+      if (HostSupportsSVE) {
+        eor(VTMP1.Z().VnD(), VTMP1.Z().VnD(), VTMP1.Z().VnD());
+      } else {
+        eor(VTMP1.V16B(), VTMP1.V16B(), VTMP1.V16B());
+      }
+
+      mov(VTMP1.V16B(), 0, Source.V16B(), 0);
+
+      if (HostSupportsSVE) {
+        mov(Dst.Z().VnD(), VTMP1.Z().VnD());
+      } else {
+        mov(Dst, VTMP1);
+      }
+      break;
+    }
+    case 2: {
+      if (HostSupportsSVE) {
+        eor(VTMP1.Z().VnD(), VTMP1.Z().VnD(), VTMP1.Z().VnD());
+      } else {
+        eor(VTMP1.V16B(), VTMP1.V16B(), VTMP1.V16B());
+      }
+
+      mov(VTMP1.V8H(), 0, Source.V8H(), 0);
+
+      if (HostSupportsSVE) {
+        mov(Dst.Z().VnD(), VTMP1.Z().VnD());
+      } else {
+        mov(Dst, VTMP1);
+      }
+      break;
+    }
+    case 4: {
+      if (HostSupportsSVE) {
+        eor(VTMP1.Z().VnD(), VTMP1.Z().VnD(), VTMP1.Z().VnD());
+      } else {
+        eor(VTMP1.V16B(), VTMP1.V16B(), VTMP1.V16B());
+      }
+
+      mov(VTMP1.V4S(), 0, Source.V4S(), 0);
+
+      if (HostSupportsSVE) {
+        mov(Dst.Z().VnD(), VTMP1.Z().VnD());
+      } else {
+        mov(Dst, VTMP1);
+      }
+      break;
+    }
+    case 8: {
+      if (HostSupportsSVE) {
+        eor(VTMP1.Z().VnD(), VTMP1.Z().VnD(), VTMP1.Z().VnD());
+        mov(VTMP1.V8B(), Source.V8B());
+        mov(Dst.Z().VnB(), VTMP1.Z().VnB());
+      } else {
+        mov(Dst.V8B(), Source.V8B());
+      }
+      break;
+    }
+    case 16: {
+      if (HostSupportsSVE) {
+        eor(VTMP1.Z().VnD(), VTMP1.Z().VnD(), VTMP1.Z().VnD());
+        mov(VTMP1.V16B(), Source.V16B());
+        mov(Dst.Z().VnB(), VTMP1.Z().VnB());
+      } else {
+        if (Dst.GetCode() != Source.GetCode()) {
+          mov(Dst.V16B(), Source.V16B());
+        }
+      }
+      break;
+    }
+    case 32: {
+      if (Dst.GetCode() != Source.GetCode()) {
+        mov(Dst.Z().VnD(), Source.Z().VnD());
+      }
+      break;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unknown Op Size: {}", OpSize);
+      break;
+  }
 }
 
 DEF_OP(VAnd) {
   auto Op = IROp->C<IR::IROp_VAnd>();
-  and_(GetDst(Node).V16B(), GetSrc(Op->Vector1.ID()).V16B(), GetSrc(Op->Vector2.ID()).V16B());
+
+  const auto Dst = GetDst(Node);
+  const auto Vector1 = GetSrc(Op->Vector1.ID());
+  const auto Vector2 = GetSrc(Op->Vector2.ID());
+
+  if (HostSupportsSVE) {
+    and_(Dst.Z().VnD(), Vector1.Z().VnD(), Vector2.Z().VnD());
+  } else {
+    and_(Dst.V16B(), Vector1.V16B(), Vector2.V16B());
+  }
 }
 
 DEF_OP(VBic) {
   auto Op = IROp->C<IR::IROp_VBic>();
-  bic(GetDst(Node).V16B(), GetSrc(Op->Vector1.ID()).V16B(), GetSrc(Op->Vector2.ID()).V16B());
+
+  const auto Dst = GetDst(Node);
+  const auto Vector1 = GetSrc(Op->Vector1.ID());
+  const auto Vector2 = GetSrc(Op->Vector2.ID());
+
+  if (HostSupportsSVE) {
+    bic(Dst.Z().VnD(), Vector1.Z().VnD(), Vector2.Z().VnD());
+  } else {
+    bic(Dst.V16B(), Vector1.V16B(), Vector2.V16B());
+  }
 }
 
 DEF_OP(VOr) {
   auto Op = IROp->C<IR::IROp_VOr>();
-  orr(GetDst(Node).V16B(), GetSrc(Op->Vector1.ID()).V16B(), GetSrc(Op->Vector2.ID()).V16B());
+
+  const auto Dst = GetDst(Node);
+  const auto Vector1 = GetSrc(Op->Vector1.ID());
+  const auto Vector2 = GetSrc(Op->Vector2.ID());
+
+  if (HostSupportsSVE) {
+    orr(Dst.Z().VnD(), Vector1.Z().VnD(), Vector2.Z().VnD());
+  } else {
+    orr(Dst.V16B(), Vector1.V16B(), Vector2.V16B());
+  }
 }
 
 DEF_OP(VXor) {
   auto Op = IROp->C<IR::IROp_VXor>();
-  eor(GetDst(Node).V16B(), GetSrc(Op->Vector1.ID()).V16B(), GetSrc(Op->Vector2.ID()).V16B());
+
+  const auto Dst = GetDst(Node);
+  const auto Vector1 = GetSrc(Op->Vector1.ID());
+  const auto Vector2 = GetSrc(Op->Vector2.ID());
+
+  if (HostSupportsSVE) {
+    eor(Dst.Z().VnD(), Vector1.Z().VnD(), Vector2.Z().VnD());
+  } else {
+    eor(Dst.V16B(), Vector1.V16B(), Vector2.V16B());
+  }
 }
 
 DEF_OP(VAdd) {

External/FEXCore/Source/Interface/Core/JIT/x86_64/BranchOps.cpp

@@ -117,9 +117,9 @@ DEF_OP(ExitFunction) {
 
 DEF_OP(Jump) {
   const auto Op = IROp->C<IR::IROp_Jump>();
-  const auto ArgID = Op->Args(0).ID();
+  const auto Target = Op->TargetBlock.ID();
 
-  PendingTargetLabel = &JumpTargets.try_emplace(ArgID).first->second;
+  PendingTargetLabel = &JumpTargets.try_emplace(Target).first->second;
 }
 
 #define GRCMP(Node) (Op->CompareSize == 4 ? GetSrc<RA_32>(Node) : GetSrc<RA_64>(Node))
@@ -209,7 +209,7 @@ DEF_OP(Thunk) {
   if (NumPush & 1)
     sub(rsp, 8); // Align
 
-  mov(rdi, GetSrc<RA_64>(Op->Header.Args[0].ID()));
+  mov(rdi, GetSrc<RA_64>(Op->ArgPtr.ID()));
 
   auto thunkFn = ThreadState->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
 
@@ -253,7 +253,7 @@ DEF_OP(ValidateCode) {
   }
 }
 
-DEF_OP(RemoveThreadCodeEntry) {
+DEF_OP(ThreadRemoveCodeEntry) {
   auto NumPush = RA64.size();
 
   for (auto &Reg : RA64)
@@ -266,7 +266,7 @@ DEF_OP(RemoveThreadCodeEntry) {
   mov(rax, Entry); // imm64 move
   mov(rsi, rax);
 
-  call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.RemoveThreadCodeEntryFromJIT)]);
+  call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadRemoveCodeEntryFromJIT)]);
 
   if (NumPush & 1)
     add(rsp, 8); // Align
@@ -288,8 +288,8 @@ DEF_OP(CPUID) {
   // Result: RAX, RDX. 4xi32
 
   // rsi can be in the source registers, so copy argument to edx first
-  mov (edx, GetSrc<RA_32>(Op->Header.Args[1].ID()));
-  mov (esi, GetSrc<RA_32>(Op->Header.Args[0].ID()));
+  mov (edx, GetSrc<RA_32>(Op->Leaf.ID()));
+  mov (esi, GetSrc<RA_32>(Op->Function.ID()));
   mov (rdi, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj)]);
 
   auto NumPush = RA64.size();
@@ -322,7 +322,7 @@ void X86JITCore::RegisterBranchHandlers() {
   REGISTER_OP(SYSCALL,           Syscall);
   REGISTER_OP(THUNK,             Thunk);
   REGISTER_OP(VALIDATECODE,      ValidateCode);
-  REGISTER_OP(REMOVETHREADCODEENTRY,   RemoveThreadCodeEntry);
+  REGISTER_OP(THREADREMOVECODEENTRY,   ThreadRemoveCodeEntry);
   REGISTER_OP(CPUID,             CPUID);
 #undef REGISTER_OP
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/ConversionOps.cpp

@@ -45,18 +45,18 @@ DEF_OP(VCastFromGPR) {
   auto Op = IROp->C<IR::IROp_VCastFromGPR>();
   switch (Op->Header.ElementSize) {
     case 1:
-      movzx(rax, GetSrc<RA_8>(Op->Header.Args[0].ID()));
+      movzx(rax, GetSrc<RA_8>(Op->Src.ID()));
       vmovq(GetDst(Node), rax);
       break;
     case 2:
-      movzx(rax, GetSrc<RA_16>(Op->Header.Args[0].ID()));
+      movzx(rax, GetSrc<RA_16>(Op->Src.ID()));
       vmovq(GetDst(Node), rax);
       break;
     case 4:
-      vmovd(GetDst(Node), GetSrc<RA_32>(Op->Header.Args[0].ID()).cvt32());
+      vmovd(GetDst(Node), GetSrc<RA_32>(Op->Src.ID()).cvt32());
       break;
     case 8:
-      vmovq(GetDst(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()).cvt64());
+      vmovq(GetDst(Node), GetSrc<RA_64>(Op->Src.ID()).cvt64());
       break;
     default: LOGMAN_MSG_A_FMT("Unknown VCastFromGPR element size: {}", Op->Header.ElementSize);
   }
@@ -64,22 +64,23 @@ DEF_OP(VCastFromGPR) {
 
 DEF_OP(Float_FromGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
-  uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
+  const uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
+
   switch (Conv) {
     case 0x0404: { // Float <- int32_t
-      cvtsi2ss(GetDst(Node), GetSrc<RA_32>(Op->Header.Args[0].ID()));
+      cvtsi2ss(GetDst(Node), GetSrc<RA_32>(Op->Src.ID()));
       break;
     }
     case 0x0408: { // Float <- int64_t
-      cvtsi2ss(GetDst(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
+      cvtsi2ss(GetDst(Node), GetSrc<RA_64>(Op->Src.ID()));
       break;
     }
     case 0x0804: { // Double <- int32_t
-      cvtsi2sd(GetDst(Node), GetSrc<RA_32>(Op->Header.Args[0].ID()));
+      cvtsi2sd(GetDst(Node), GetSrc<RA_32>(Op->Src.ID()));
       break;
     }
     case 0x0808: { // Double <- int64_t
-      cvtsi2sd(GetDst(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
+      cvtsi2sd(GetDst(Node), GetSrc<RA_64>(Op->Src.ID()));
       break;
     }
   }
@@ -87,14 +88,15 @@ DEF_OP(Float_FromGPR_S) {
 
 DEF_OP(Float_FToF) {
   auto Op = IROp->C<IR::IROp_Float_FToF>();
-  uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
+  const uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
+
   switch (Conv) {
     case 0x0804: { // Double <- Float
-      cvtss2sd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
+      cvtss2sd(GetDst(Node), GetSrc(Op->Scalar.ID()));
       break;
     }
     case 0x0408: { // Float <- Double
-      cvtsd2ss(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
+      cvtsd2ss(GetDst(Node), GetSrc(Op->Scalar.ID()));
       break;
     }
     default: LOGMAN_MSG_A_FMT("Unknown Float_FToF sizes: 0x{:x}", Conv);
@@ -105,7 +107,7 @@ DEF_OP(Vector_SToF) {
   auto Op = IROp->C<IR::IROp_Vector_SToF>();
   switch (Op->Header.ElementSize) {
     case 4:
-      cvtdq2ps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
+      cvtdq2ps(GetDst(Node), GetSrc(Op->Vector.ID()));
     break;
     case 8:
       // This operation is a bit disgusting in x86
@@ -113,8 +115,8 @@ DEF_OP(Vector_SToF) {
       // 1) First extract the top 64bits
       // 2) Do a scalar conversion on each
       // 3) Make sure to merge them together at the end
-      pextrq(rax, GetSrc(Op->Header.Args[0].ID()), 1);
-      pextrq(rcx, GetSrc(Op->Header.Args[0].ID()), 0);
+      pextrq(rax, GetSrc(Op->Vector.ID()), 1);
+      pextrq(rcx, GetSrc(Op->Vector.ID()), 0);
       cvtsi2sd(GetDst(Node), rcx);
       cvtsi2sd(xmm15, rax);
       movlhps(GetDst(Node), xmm15);
@@ -127,10 +129,10 @@ DEF_OP(Vector_FToZS) {
   auto Op = IROp->C<IR::IROp_Vector_FToZS>();
   switch (Op->Header.ElementSize) {
     case 4:
-      cvttps2dq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
+      cvttps2dq(GetDst(Node), GetSrc(Op->Vector.ID()));
     break;
     case 8:
-      cvttpd2dq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
+      cvttpd2dq(GetDst(Node), GetSrc(Op->Vector.ID()));
     break;
     default: LOGMAN_MSG_A_FMT("Unknown Vector_FToZS element size: {}", Op->Header.ElementSize);
   }
@@ -140,10 +142,10 @@ DEF_OP(Vector_FToS) {
   auto Op = IROp->C<IR::IROp_Vector_FToS>();
   switch (Op->Header.ElementSize) {
     case 4:
-      cvtps2dq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
+      cvtps2dq(GetDst(Node), GetSrc(Op->Vector.ID()));
     break;
     case 8:
-      cvtpd2dq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
+      cvtpd2dq(GetDst(Node), GetSrc(Op->Vector.ID()));
     break;
     default: LOGMAN_MSG_A_FMT("Unknown Vector_FToS element size: {}", Op->Header.ElementSize);
   }
@@ -151,15 +153,15 @@ DEF_OP(Vector_FToS) {
 
 DEF_OP(Vector_FToF) {
   auto Op = IROp->C<IR::IROp_Vector_FToF>();
-  uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
+  const uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
 
   switch (Conv) {
     case 0x0804: { // Double <- Float
-      cvtps2pd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
+      cvtps2pd(GetDst(Node), GetSrc(Op->Vector.ID()));
       break;
     }
     case 0x0408: { // Float <- Double
-      cvtpd2ps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
+      cvtpd2ps(GetDst(Node), GetSrc(Op->Vector.ID()));
       break;
     }
     default: LOGMAN_MSG_A_FMT("Unknown Vector_FToF conversion type : 0x{:04x}", Conv); break;
@@ -190,10 +192,10 @@ DEF_OP(Vector_FToI) {
 
   switch (Op->Header.ElementSize) {
     case 4:
-      roundps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), RoundMode);
+      roundps(GetDst(Node), GetSrc(Op->Vector.ID()), RoundMode);
     break;
     case 8:
-      roundpd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), RoundMode);
+      roundpd(GetDst(Node), GetSrc(Op->Vector.ID()), RoundMode);
     break;
   }
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/EncryptionOps.cpp

@@ -17,44 +17,44 @@ namespace FEXCore::CPU {
 
 DEF_OP(AESImc) {
   auto Op = IROp->C<IR::IROp_VAESImc>();
-  vaesimc(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
+  vaesimc(GetDst(Node), GetSrc(Op->Vector.ID()));
 }
 
 DEF_OP(AESEnc) {
   auto Op = IROp->C<IR::IROp_VAESEnc>();
-  vaesenc(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+  vaesenc(GetDst(Node), GetSrc(Op->State.ID()), GetSrc(Op->Key.ID()));
 }
 
 DEF_OP(AESEncLast) {
   auto Op = IROp->C<IR::IROp_VAESEncLast>();
-  vaesenclast(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+  vaesenclast(GetDst(Node), GetSrc(Op->State.ID()), GetSrc(Op->Key.ID()));
 }
 
 DEF_OP(AESDec) {
   auto Op = IROp->C<IR::IROp_VAESDec>();
-  vaesdec(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+  vaesdec(GetDst(Node), GetSrc(Op->State.ID()), GetSrc(Op->Key.ID()));
 }
 
 DEF_OP(AESDecLast) {
   auto Op = IROp->C<IR::IROp_VAESDecLast>();
-  vaesdeclast(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+  vaesdeclast(GetDst(Node), GetSrc(Op->State.ID()), GetSrc(Op->Key.ID()));
 }
 
 DEF_OP(AESKeyGenAssist) {
   auto Op = IROp->C<IR::IROp_VAESKeyGenAssist>();
-  vaeskeygenassist(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), Op->RCON);
+  vaeskeygenassist(GetDst(Node), GetSrc(Op->Src.ID()), Op->RCON);
 }
 
 DEF_OP(CRC32) {
   auto Op = IROp->C<IR::IROp_CRC32>();
   switch (IROp->Size) {
   case 4:
-    mov(TMP1, GetSrc<RA_32>(Op->Header.Args[1].ID()));
-    mov(GetDst<RA_32>(Node), GetSrc<RA_32>(Op->Header.Args[0].ID()));
+    mov(TMP1, GetSrc<RA_32>(Op->Src2.ID()));
+    mov(GetDst<RA_32>(Node), GetSrc<RA_32>(Op->Src1.ID()));
   break;
   case 8:
-    mov(TMP1, GetSrc<RA_64>(Op->Header.Args[1].ID()));
-    mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
+    mov(TMP1, GetSrc<RA_64>(Op->Src2.ID()));
+    mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Src1.ID()));
   break;
   default: LOGMAN_MSG_A_FMT("Unknown CRC32 size: {}", IROp->Size);
   }

External/FEXCore/Source/Interface/Core/JIT/x86_64/FlagOps.cpp

@@ -18,7 +18,7 @@ namespace FEXCore::CPU {
 DEF_OP(GetHostFlag) {
   auto Op = IROp->C<IR::IROp_GetHostFlag>();
 
-  mov(rax, GetSrc<RA_64>(Op->Header.Args[0].ID()));
+  mov(rax, GetSrc<RA_64>(Op->Value.ID()));
   shr(rax, Op->Flag);
   and_(rax, 1);
   mov(GetDst<RA_64>(Node), rax);

External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp

@@ -25,6 +25,7 @@ $end_info$
 #include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/IR/RegisterAllocationData.h>
 #include <FEXCore/Utils/Allocator.h>
+#include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 
 #include <algorithm>
@@ -293,7 +294,8 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) {
       case FABI_UNKNOWN:
       default:
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
-        LOGMAN_MSG_A_FMT("Unhandled IR Fallback ABI: {} {}", FEXCore::IR::GetName(IROp->Op), Info.ABI);
+        LOGMAN_MSG_A_FMT("Unhandled IR Fallback ABI: {} {}",
+                         IR::GetName(IROp->Op), ToUnderlying(Info.ABI));
 #endif
         break;
     }
@@ -312,7 +314,7 @@ static uint64_t X86JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame,
   }
 
   auto LinkerAddress = Frame->Pointers.Common.ExitFunctionLinker;
-  Thread->LookupCache->AddBlockLink(GuestRip, (uintptr_t)record, [record, LinkerAddress]{
+  Context::Context::ThreadAddBlockLink(Thread, GuestRip, (uintptr_t)record, [record, LinkerAddress]{
     // undo the link
     record[0] = LinkerAddress;
   });
@@ -361,7 +363,7 @@ X86JITCore::X86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalTh
     
     Common.PrintValue = reinterpret_cast<uint64_t>(PrintValue);
     Common.PrintVectorValue = reinterpret_cast<uint64_t>(PrintVectorValue);
-    Common.RemoveThreadCodeEntryFromJIT = reinterpret_cast<uintptr_t>(&Context::Context::RemoveThreadCodeEntryFromJit);
+    Common.ThreadRemoveCodeEntryFromJIT = reinterpret_cast<uintptr_t>(&Context::Context::ThreadRemoveCodeEntryFromJit);
     Common.CPUIDObj = reinterpret_cast<uint64_t>(&CTX->CPUID);
 
     {
@@ -371,7 +373,7 @@ X86JITCore::X86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalTh
 
     Common.SyscallHandlerObj = reinterpret_cast<uint64_t>(CTX->SyscallHandler);
     Common.SyscallHandlerFunc = reinterpret_cast<uint64_t>(FEXCore::Context::HandleSyscall);
-    Common.ExitFunctionLink = reinterpret_cast<uintptr_t>(&X86JITCore_ExitFunctionLink);
+    Common.ExitFunctionLink = reinterpret_cast<uintptr_t>(&Context::Context::ThreadExitFunctionLink<X86JITCore_ExitFunctionLink>);
 
     // Fill in the fallback handlers
     InterpreterOps::FillFallbackIndexPointers(Common.FallbackHandlerPointers);
@@ -407,7 +409,7 @@ void X86JITCore::ClearCache() {
 IR::PhysicalRegister X86JITCore::GetPhys(IR::NodeID Node) const {
   auto PhyReg = RAData->GetNodeRegister(Node);
 
-  LOGMAN_THROW_A_FMT(PhyReg.Raw != 255, "Couldn't Allocate register for node: ssa{}. Class: {}", Node, PhyReg.Class);
+  LOGMAN_THROW_AA_FMT(PhyReg.Raw != 255, "Couldn't Allocate register for node: ssa{}. Class: {}", Node, PhyReg.Class);
 
   return PhyReg;
 }
@@ -592,7 +594,7 @@ void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRLi
     setSize(getSize() + GDBSize);
   }
 
-  LOGMAN_THROW_A_FMT(RAData != nullptr, "Needs RA");
+  LOGMAN_THROW_AA_FMT(RAData != nullptr, "Needs RA");
 
   SpillSlots = RAData->SpillSlots();
 
@@ -649,7 +651,7 @@ void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRLi
     using namespace FEXCore::IR;
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
     auto BlockIROp = BlockHeader->CW<IROp_CodeBlock>();
-    LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
+    LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
 #endif
 
     auto BlockStartHostCode = getCurr<uint8_t *>();

External/FEXCore/Source/Interface/Core/JIT/x86_64/JITClass.h

@@ -181,6 +181,10 @@ private:
   [[nodiscard]] Xbyak::Xmm GetSrc(IR::NodeID Node) const;
   [[nodiscard]] Xbyak::Xmm GetDst(IR::NodeID Node) const;
 
+  [[nodiscard]] static Xbyak::Ymm ToYMM(const Xbyak::Xmm& xmm) {
+    return Xbyak::Ymm{xmm.getIdx()};
+  }
+
   [[nodiscard]] Xbyak::RegExp GenerateModRM(Xbyak::Reg Base, IR::OrderedNodeWrapper Offset,
                                             IR::MemOffsetType OffsetType, uint8_t OffsetScale) const;
 
@@ -312,7 +316,7 @@ private:
   DEF_OP(Syscall);
   DEF_OP(Thunk);
   DEF_OP(ValidateCode);
-  DEF_OP(RemoveThreadCodeEntry);
+  DEF_OP(ThreadRemoveCodeEntry);
   DEF_OP(CPUID);
 
   ///< Conversion ops

External/FEXCore/Source/Interface/Core/JIT/x86_64/MiscOps.cpp

@@ -45,56 +45,30 @@ DEF_OP(Fence) {
 
 DEF_OP(Break) {
   auto Op = IROp->C<IR::IROp_Break>();
-  switch (Op->Reason) {
-    case FEXCore::IR::Break_Unimplemented: // Hard fault
-    case FEXCore::IR::Break_Interrupt: // Guest ud2
-      ud2();
-      break;
-    case FEXCore::IR::Break_Overflow: // overflow
-      // Need to be outside of JIT cache space to ensure cache clearing correctness
-      jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.OverflowExceptionHandler)]);
-      break;
-    case FEXCore::IR::Break_Halt: { // HLT
-      // Time to quit
-      // Set our stack to the starting stack location
-      mov(rsp, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)]);
 
-      // Now we need to jump to the thread stop handler
-      jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadStopHandlerSpillSRA)]);
-      break;
-    }
-    case FEXCore::IR::Break_Interrupt3: // INT3
-    {
-      if (CTX->GetGdbServerStatus()) {
-        // Adjust the stack first for a regular return
-        if (SpillSlots) {
-          add(rsp, SpillSlots * 16);
-        }
+  if (SpillSlots) {
+    add(rsp, SpillSlots * 16);
+  }
 
-        // This jump target needs to be a constant offset here
-        jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadPauseHandlerSpillSRA)]);
-      }
-      else {
-        // If we don't have a gdb server attached then....crash?
-        // Treat this case like HLT
-        mov(rsp, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)]);
+  mov(byte [STATE + offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.FaultToTopAndGeneratedException)], 1);
+  mov(byte [STATE + offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.Signal)], Op->Reason.Signal);
+  mov(dword [STATE + offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.TrapNo)], Op->Reason.TrapNumber);
+  mov(dword [STATE + offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.err_code)], Op->Reason.ErrorRegister);
+  mov(dword [STATE + offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.si_code)], Op->Reason.si_code);
 
-        // Now we need to jump to the thread stop handler
-        jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadStopHandlerSpillSRA)]);
-      }
+  switch (Op->Reason.Signal) {
+  case SIGILL:
+    jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGILL)]);
+    break;
+  case SIGTRAP:
+    jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP)]);
+    break;
+  case SIGSEGV:
+    jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGSEGV)]);
+    break;
+  default:
+    jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP)]);
     break;
-    }
-    case FEXCore::IR::Break_InvalidInstruction:
-    {
-      if (SpillSlots) {
-        add(rsp, SpillSlots * 16);
-      }
-
-      // Need to be outside of JIT cache space to ensure cache clearing correctness
-      jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.UnimplementedInstructionHandler)]);
-      break;
-    }
-    default: LOGMAN_MSG_A_FMT("Unknown Break reason: {}", Op->Reason);
   }
 }
 
@@ -110,7 +84,7 @@ DEF_OP(GetRoundingMode) {
 
 DEF_OP(SetRoundingMode) {
   auto Op = IROp->C<IR::IROp_SetRoundingMode>();
-  auto Src = GetSrc<RA_32>(Op->Header.Args[0].ID());
+  auto Src = GetSrc<RA_32>(Op->RoundMode.ID());
 
   // Load old mxcsr
   // Only stores to memory
@@ -135,13 +109,13 @@ DEF_OP(Print) {
   auto Op = IROp->C<IR::IROp_Print>();
 
   PushRegs();
-  if (IsGPR(Op->Header.Args[0].ID())) {
-    mov (rdi, GetSrc<RA_64>(Op->Header.Args[0].ID()));
+  if (IsGPR(Op->Value.ID())) {
+    mov (rdi, GetSrc<RA_64>(Op->Value.ID()));
     call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.PrintValue)]);
   }
   else {
-    pextrq(rdi, GetSrc(Op->Header.Args[0].ID()), 0);
-    pextrq(rsi, GetSrc(Op->Header.Args[0].ID()), 1);
+    pextrq(rdi, GetSrc(Op->Value.ID()), 0);
+    pextrq(rsi, GetSrc(Op->Value.ID()), 1);
 
     call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.PrintVectorValue)]);
   }

External/FEXCore/Source/Interface/Core/JIT/x86_64/MoveOps.cpp

@@ -20,13 +20,13 @@ DEF_OP(ExtractElementPair) {
   auto Op = IROp->C<IR::IROp_ExtractElementPair>();
   switch (Op->Header.Size) {
     case 4: {
-      auto Src = GetSrcPair<RA_32>(Op->Header.Args[0].ID());
+      auto Src = GetSrcPair<RA_32>(Op->Pair.ID());
       std::array<Xbyak::Reg, 2> Regs = {Src.first, Src.second};
       mov (GetDst<RA_32>(Node), Regs[Op->Element]);
       break;
     }
     case 8: {
-      auto Src = GetSrcPair<RA_64>(Op->Header.Args[0].ID());
+      auto Src = GetSrcPair<RA_64>(Op->Pair.ID());
       std::array<Xbyak::Reg, 2> Regs = {Src.first, Src.second};
       mov (GetDst<RA_64>(Node), Regs[Op->Element]);
       break;
@@ -45,15 +45,15 @@ DEF_OP(CreateElementPair) {
   switch (IROp->ElementSize) {
     case 4: {
       Dst = GetSrcPair<RA_32>(Node);
-      RegFirst = GetSrc<RA_32>(Op->Header.Args[0].ID());
-      RegSecond = GetSrc<RA_32>(Op->Header.Args[1].ID());
+      RegFirst = GetSrc<RA_32>(Op->Lower.ID());
+      RegSecond = GetSrc<RA_32>(Op->Upper.ID());
       RegTmp = eax;
       break;
     }
     case 8: {
       Dst = GetSrcPair<RA_64>(Node);
-      RegFirst = GetSrc<RA_64>(Op->Header.Args[0].ID());
-      RegSecond = GetSrc<RA_64>(Op->Header.Args[1].ID());
+      RegFirst = GetSrc<RA_64>(Op->Lower.ID());
+      RegSecond = GetSrc<RA_64>(Op->Upper.ID());
       RegTmp = rax;
       break;
     }
@@ -75,7 +75,7 @@ DEF_OP(CreateElementPair) {
 
 DEF_OP(Mov) {
   auto Op = IROp->C<IR::IROp_Mov>();
-  mov (GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
+  mov (GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Value.ID()));
 }
 
 #undef DEF_OP

External/FEXCore/Source/Interface/Core/JIT/x86_64/x64Relocations.cpp

@@ -91,7 +91,7 @@ bool X86JITCore::ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uint6
   size_t DataIndex{};
   for (size_t j = 0; j < NumRelocations; ++j) {
     const FEXCore::CPU::Relocation *Reloc = reinterpret_cast<const FEXCore::CPU::Relocation *>(&EntryRelocations[DataIndex]);
-    LOGMAN_THROW_A_FMT((DataIndex % alignof(Relocation)) == 0, "Alignment of relocation wasn't adhered to");
+    LOGMAN_THROW_AA_FMT((DataIndex % alignof(Relocation)) == 0, "Alignment of relocation wasn't adhered to");
 
     switch (Reloc->Header.Type) {
       case FEXCore::CPU::RelocationTypes::RELOC_NAMED_SYMBOL_LITERAL: {

External/FEXCore/Source/Interface/Core/LookupCache.cpp

@@ -37,11 +37,11 @@ LookupCache::LookupCache(FEXCore::Context::Context *CTX)
   // We currently limit to 128MB of real memory for caching for the total cache size.
   // Can end up being inefficient if we compile a small number of blocks per page
   PageMemory = reinterpret_cast<uintptr_t>(FEXCore::Allocator::mmap(nullptr, CODE_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
-  LOGMAN_THROW_A_FMT(PageMemory != -1ULL, "Failed to allocate page memory");
+  LOGMAN_THROW_AA_FMT(PageMemory != -1ULL, "Failed to allocate page memory");
 
   // L1 Cache
   L1Pointer = reinterpret_cast<uintptr_t>(FEXCore::Allocator::mmap(nullptr, L1_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
-  LOGMAN_THROW_A_FMT(L1Pointer != -1ULL, "Failed to allocate L1Pointer");
+  LOGMAN_THROW_AA_FMT(L1Pointer != -1ULL, "Failed to allocate L1Pointer");
 
   VirtualMemSize = ctx->Config.VirtualMemSize;
 }

External/FEXCore/Source/Interface/Core/LookupCache.h

@@ -90,7 +90,7 @@ public:
     std::lock_guard<std::recursive_mutex> lk(WriteLock);
     
     [[maybe_unused]] auto Inserted = BlockList.emplace(Address, (uintptr_t)HostCode).second;
-    LOGMAN_THROW_A_FMT(Inserted, "Duplicate block mapping added");
+    LOGMAN_THROW_AA_FMT(Inserted, "Duplicate block mapping added");
 
     // There is no need to update L1 or L2, they will get updated on first lookup
     // However, adding to L1 here increases performance

External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -17,6 +17,7 @@ $end_info$
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IREmitter.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
+#include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 
 #include <algorithm>
@@ -350,7 +351,7 @@ void OpDispatchBuilder::SecondaryALUOp(OpcodeArgs) {
         break;
       }
       default:
-        LOGMAN_MSG_A_FMT("Unknown Atomic IR Op: {}", IROp);
+        LOGMAN_MSG_A_FMT("Unknown Atomic IR Op: {}", ToUnderlying(IROp));
         break;
     }
   }
@@ -1589,7 +1590,12 @@ void OpDispatchBuilder::MOVSegOp(OpcodeArgs) {
       case 2: // CS
       case FEXCore::X86State::REG_R9: // CS
         // CPL3 can't write to this
-        _Break(FEXCore::IR::Break_InvalidInstruction, 0);
+        _Break(FEXCore::IR::BreakDefinition {
+            .ErrorRegister = 0,
+            .Signal = SIGILL,
+            .TrapNumber = 0,
+            .si_code = 0,
+        });
         break;
       case 3: // SS
       case FEXCore::X86State::REG_R10: // SS
@@ -4503,7 +4509,7 @@ void OpDispatchBuilder::Finalize() {
 
   [[maybe_unused]] const FEXCore::IR::IROp_Header *IROp =
   RealNode->Op(DualListData.DataBegin());
-  LOGMAN_THROW_A_FMT(IROp->Op == OP_IRHEADER, "First op in function must be our header");
+  LOGMAN_THROW_AA_FMT(IROp->Op == OP_IRHEADER, "First op in function must be our header");
 
   // Let's walk the jump blocks and see if we have handled every block target
   for (auto &Handler : JumpTargets) {
@@ -4529,7 +4535,7 @@ uint8_t OpDispatchBuilder::GetDstSize(X86Tables::DecodedOp Op) const {
 
   const uint32_t DstSizeFlag = X86Tables::DecodeFlags::GetSizeDstFlags(Op->Flags);
   const uint8_t Size = Sizes[DstSizeFlag];
-  LOGMAN_THROW_A_FMT(Size != 0, "Invalid destination size for op");
+  LOGMAN_THROW_AA_FMT(Size != 0, "Invalid destination size for op");
   return Size;
 }
 
@@ -4547,7 +4553,7 @@ uint8_t OpDispatchBuilder::GetSrcSize(X86Tables::DecodedOp Op) const {
 
   const uint32_t SrcSizeFlag = X86Tables::DecodeFlags::GetSizeSrcFlags(Op->Flags);
   const uint8_t Size = Sizes[SrcSizeFlag];
-  LOGMAN_THROW_A_FMT(Size != 0, "Invalid destination size for op");
+  LOGMAN_THROW_AA_FMT(Size != 0, "Invalid destination size for op");
   return Size;
 }
 
@@ -4641,7 +4647,14 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(FEXCore::IR::RegisterClass
       Src = _LoadContext(OpSize, FPRClass, offsetof(FEXCore::Core::CPUState, mm[gpr - FEXCore::X86State::REG_MM_0]));
     }
     else if (gpr >= FEXCore::X86State::REG_XMM_0) {
-      Src = _LoadContext(OpSize, FPRClass, offsetof(FEXCore::Core::CPUState, xmm[gpr - FEXCore::X86State::REG_XMM_0][Operand.Data.GPR.HighBits ? 1 : 0]));
+      const auto gprIndex = gpr - X86State::REG_XMM_0;
+      const auto highIndex = Operand.Data.GPR.HighBits ? 1 : 0;
+
+      if (CTX->HostFeatures.SupportsAVX) {
+        Src = _LoadContext(OpSize, FPRClass, offsetof(Core::CPUState, xmm.avx.data[gprIndex][highIndex]));
+      } else {
+        Src = _LoadContext(OpSize, FPRClass, offsetof(Core::CPUState, xmm.sse.data[gprIndex][highIndex]));
+      }
     }
     else {
       Src = _LoadContext(OpSize, GPRClass, offsetof(FEXCore::Core::CPUState, gregs[gpr]) + (Operand.Data.GPR.HighBits ? 1 : 0));
@@ -4783,7 +4796,14 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
       _StoreContext(OpSize, Class, Src, offsetof(FEXCore::Core::CPUState, mm[gpr - FEXCore::X86State::REG_MM_0]));
     }
     else if (gpr >= FEXCore::X86State::REG_XMM_0) {
-      _StoreContext(OpSize, Class, Src, offsetof(FEXCore::Core::CPUState, xmm[gpr - FEXCore::X86State::REG_XMM_0][Operand.Data.GPR.HighBits ? 1 : 0]));
+      const auto gprIndex = gpr - X86State::REG_XMM_0;
+      const auto highIndex = Operand.Data.GPR.HighBits ? 1 : 0;
+
+      if (CTX->HostFeatures.SupportsAVX) {
+        _StoreContext(OpSize, Class, Src, offsetof(Core::CPUState, xmm.avx.data[gprIndex][highIndex]));
+      } else {
+        _StoreContext(OpSize, Class, Src, offsetof(Core::CPUState, xmm.sse.data[gprIndex][highIndex]));
+      }
     }
     else {
       if (GPRSize == 8 && OpSize == 4) {
@@ -4791,11 +4811,11 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
         // For all other sizes, the upper bits are guaranteed to already be zero
          OrderedNode *Value = GetOpSize(Src) == 8 ? _Bfe(4, 32, 0, Src) : Src;
 
-        LOGMAN_THROW_A_FMT(!Operand.Data.GPR.HighBits, "Can't handle 32bit store to high 8bit register");
+        LOGMAN_THROW_AA_FMT(!Operand.Data.GPR.HighBits, "Can't handle 32bit store to high 8bit register");
         _StoreContext(GPRSize, Class, Value, offsetof(FEXCore::Core::CPUState, gregs[gpr]));
       }
       else {
-        LOGMAN_THROW_A_FMT(!(GPRSize == 4 && OpSize > 4), "Oops had a {} GPR load", OpSize);
+        LOGMAN_THROW_AA_FMT(!(GPRSize == 4 && OpSize > 4), "Oops had a {} GPR load", OpSize);
         _StoreContext(std::min(GPRSize, OpSize), Class, Src, offsetof(FEXCore::Core::CPUState, gregs[gpr]) + (Operand.Data.GPR.HighBits ? 1 : 0));
       }
     }
@@ -5029,7 +5049,7 @@ void OpDispatchBuilder::ALUOp(OpcodeArgs) {
         break;
       }
       default:
-        LOGMAN_MSG_A_FMT("Unknown Atomic IR Op: {}", IROp);
+        LOGMAN_MSG_A_FMT("Unknown Atomic IR Op: {}", ToUnderlying(IROp));
         break;
     }
   }
@@ -5069,37 +5089,58 @@ void OpDispatchBuilder::ALUOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::INTOp(OpcodeArgs) {
-  FEXCore::IR::BreakReason Reason{};
-  uint8_t Literal{};
-  bool setRIP = false;
+  IR::BreakDefinition Reason;
+  bool SetRIPToNext = false;
 
   switch (Op->OP) {
-  case 0xCD:
-    Reason = FEXCore::IR::Break_Interrupt;
-    Literal = Op->Src[0].Data.Literal.Value;
+  case 0xCD: { // INT imm8
+    uint8_t Literal = Op->Src[0].Data.Literal.Value;
+
     if (Literal == 0x80) {
       // Syscall on linux
       SyscallOp(Op);
       return;
     }
+
+    Reason.ErrorRegister = Literal << 3 | (0b010);
+    Reason.Signal = SIGSEGV;
+    // GP is raised when task-gate isn't setup to be valid
+    Reason.TrapNumber = X86State::X86_TRAPNO_GP;
+    Reason.si_code = 0x80;
+    break;
+  }
+  case 0xCE: // INTO
+    Reason.ErrorRegister = 0;
+    Reason.Signal = SIGSEGV;
+    Reason.TrapNumber = X86State::X86_TRAPNO_OF;
+    Reason.si_code = 0x80;
+   break;
+  case 0xF1: // INT1
+    Reason.ErrorRegister = 0;
+    Reason.Signal = SIGTRAP;
+    Reason.TrapNumber = X86State::X86_TRAPNO_DB;
+    Reason.si_code = 1;
+    SetRIPToNext = true;
   break;
-  case 0xCE:
-    Reason = FEXCore::IR::Break_Overflow;
-  break;
-  case 0xF1:
-    Reason = FEXCore::IR::Break_Interrupt;
-  break;
-  case 0xF4: {
-    Reason = FEXCore::IR::Break_Halt;
-    setRIP = true;
+  case 0xF4: { // HLT
+    Reason.ErrorRegister = 0;
+    Reason.Signal = SIGSEGV;
+    Reason.TrapNumber = X86State::X86_TRAPNO_GP;
+    Reason.si_code = 0x80;
   break;
   }
-  case 0x0B:
-    Reason = FEXCore::IR::Break_Interrupt;
+  case 0x0B: // UD2
+    Reason.ErrorRegister = 0;
+    Reason.Signal = SIGILL;
+    Reason.TrapNumber = X86State::X86_TRAPNO_UD;
+    Reason.si_code = 2;
   break;
-  case 0xCC:
-    Reason = FEXCore::IR::Break_Interrupt3;
-    setRIP = true;
+  case 0xCC: // INT3
+    Reason.ErrorRegister = 0;
+    Reason.Signal = SIGTRAP;
+    Reason.TrapNumber = X86State::X86_TRAPNO_BP;
+    Reason.si_code = 0x80;
+    SetRIPToNext = true;
   break;
   }
 
@@ -5108,13 +5149,17 @@ void OpDispatchBuilder::INTOp(OpcodeArgs) {
 
   const uint8_t GPRSize = CTX->GetGPRSize();
 
-  if (setRIP) {
-    BlockSetRIP = setRIP;
+  if (SetRIPToNext) {
+    BlockSetRIP = SetRIPToNext;
 
-    // We want to set RIP to the next instruction after HLT/INT3
+    // We want to set RIP to the next instruction after INT3/INT1
     auto NewRIP = GetRelocatedPC(Op);
     _StoreContext(GPRSize, GPRClass, NewRIP, offsetof(FEXCore::Core::CPUState, rip));
   }
+  else if (Op->OP != 0xCE) {
+    auto NewRIP = GetRelocatedPC(Op, -Op->InstSize);
+    _StoreContext(GPRSize, GPRClass, NewRIP, offsetof(FEXCore::Core::CPUState, rip));
+  }
 
   if (Op->OP == 0xCE) { // Conditional to only break if Overflow == 1
     auto Flag = GetRFLAG(FEXCore::X86State::RFLAG_OF_LOC);
@@ -5127,7 +5172,7 @@ void OpDispatchBuilder::INTOp(OpcodeArgs) {
 
     auto NewRIP = GetRelocatedPC(Op);
     _StoreContext(GPRSize, GPRClass, NewRIP, offsetof(FEXCore::Core::CPUState, rip));
-    _Break(Reason, Literal);
+    _Break(Reason);
 
     // Make sure to start a new block after ending this one
     auto JumpTarget = CreateNewCodeBlockAfter(FalseBlock);
@@ -5135,7 +5180,8 @@ void OpDispatchBuilder::INTOp(OpcodeArgs) {
     SetCurrentCodeBlock(JumpTarget);
   }
   else {
-    _Break(Reason, Literal);
+    BlockSetRIP = true;
+    _Break(Reason);
   }
 }
 
@@ -5238,7 +5284,13 @@ void OpDispatchBuilder::UnimplementedOp(OpcodeArgs) {
   // We don't actually support this instruction
   // Multiblock may hit it though
   _StoreContext(GPRSize, GPRClass, GetRelocatedPC(Op, -Op->InstSize), offsetof(FEXCore::Core::CPUState, rip));
-  _Break(FEXCore::IR::Break_Unimplemented, 0);
+  _Break(FEXCore::IR::BreakDefinition {
+    .ErrorRegister = 0,
+    .Signal = SIGILL,
+    .TrapNumber = 0,
+    .si_code = 0,
+  });
+
   BlockSetRIP = true;
 
   if (Multiblock) {
@@ -5256,7 +5308,12 @@ void OpDispatchBuilder::InvalidOp(OpcodeArgs) {
   // We don't actually support this instruction
   // Multiblock may hit it though
   _StoreContext(GPRSize, GPRClass, GetRelocatedPC(Op, -Op->InstSize), offsetof(FEXCore::Core::CPUState, rip));
-  _Break(FEXCore::IR::Break_InvalidInstruction, 0);
+  _Break(FEXCore::IR::BreakDefinition {
+    .ErrorRegister = 0,
+    .Signal = SIGILL,
+    .TrapNumber = 0,
+    .si_code = 0,
+  });
   BlockSetRIP = true;
 }
 

External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h

@@ -665,7 +665,7 @@ private:
   void StoreResult(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp Op, OrderedNode *const Src, int8_t Align, MemoryAccessType AccessType = MemoryAccessType::ACCESS_DEFAULT);
 
   [[nodiscard]] static uint32_t GPROffset(X86State::X86Reg reg) {
-    LOGMAN_THROW_A_FMT(reg <= X86State::X86Reg::REG_R15, "Invalid reg used");
+    LOGMAN_THROW_AA_FMT(reg <= X86State::X86Reg::REG_R15, "Invalid reg used");
     return static_cast<uint32_t>(offsetof(Core::CPUState, gregs[static_cast<size_t>(reg)]));
   }
 

External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp

@@ -221,7 +221,7 @@ void OpDispatchBuilder::SHA256RNDS2Op(OpcodeArgs) {
 
   OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
   OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
-  OrderedNode *XMM0 = _LoadContext(16, FPRClass, offsetof(FEXCore::Core::CPUState, xmm[0]));
+  OrderedNode *XMM0 = _LoadContext(16, FPRClass, offsetof(FEXCore::Core::CPUState, xmm.avx.data[0]));
 
   auto A0 = _VExtractToGPR(16, 4, Src, 3);
   auto B0 = _VExtractToGPR(16, 4, Src, 2);

External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp

@@ -440,10 +440,16 @@ void OpDispatchBuilder::MOVQOp(OpcodeArgs) {
   // This instruction is a bit special that if the destination is a register then it'll ZEXT the 64bit source to 128bit
   if (Op->Dest.IsGPR()) {
     const auto gpr = Op->Dest.Data.GPR.GPR;
+    const auto gprIndex = gpr - X86State::REG_XMM_0;
 
-    _StoreContext(8, FPRClass, Src, offsetof(FEXCore::Core::CPUState, xmm[gpr - FEXCore::X86State::REG_XMM_0][0]));
+    const auto fprLowOffset = CTX->HostFeatures.SupportsAVX ? offsetof(Core::CPUState, xmm.avx.data[gprIndex][0])
+                                                            : offsetof(Core::CPUState, xmm.sse.data[gprIndex][0]);
+    const auto fprHighOffset = CTX->HostFeatures.SupportsAVX ? offsetof(Core::CPUState, xmm.avx.data[gprIndex][1])
+                                                             : offsetof(Core::CPUState, xmm.sse.data[gprIndex][1]);
+
+    _StoreContext(8, FPRClass, Src, fprLowOffset);
     auto Const = _Constant(0);
-    _StoreContext(8, GPRClass, Const, offsetof(FEXCore::Core::CPUState, xmm[gpr - FEXCore::X86State::REG_XMM_0][1]));
+    _StoreContext(8, GPRClass, Const, fprHighOffset);
   }
   else {
     // This is simple, just store the result
@@ -562,7 +568,7 @@ void OpDispatchBuilder::PSHUFBOp(OpcodeArgs) {
 
 template<size_t ElementSize, bool HalfSize, bool Low>
 void OpDispatchBuilder::PSHUFDOp(OpcodeArgs) {
-  LOGMAN_THROW_A_FMT(ElementSize != 0, "What. No element size?");
+  LOGMAN_THROW_AA_FMT(ElementSize != 0, "What. No element size?");
   const auto Size = GetSrcSize(Op);
   OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
   uint8_t Shuffle = Op->Src[1].Data.Literal.Value;
@@ -599,7 +605,7 @@ void OpDispatchBuilder::PSHUFDOp<4, false, true>(OpcodeArgs);
 
 template<size_t ElementSize>
 void OpDispatchBuilder::SHUFOp(OpcodeArgs) {
-  LOGMAN_THROW_A_FMT(ElementSize != 0, "What. No element size?");
+  LOGMAN_THROW_AA_FMT(ElementSize != 0, "What. No element size?");
   const auto Size = GetSrcSize(Op);
   OrderedNode *Src1 = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
   OrderedNode *Src2 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
@@ -1390,10 +1396,18 @@ void OpDispatchBuilder::FXSaveOp(OpcodeArgs) {
 
     _StoreMem(FPRClass, 16, MemLocation, MMReg, 16);
   }
-  unsigned NumRegs = CTX->Config.Is64BitMode ? 16 : 8;
+
+  const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
+  const auto GetXMMOffset = [this](size_t i) {
+    if (CTX->HostFeatures.SupportsAVX) {
+      return offsetof(Core::CPUState, xmm.avx.data[i]);
+    } else {
+      return offsetof(Core::CPUState, xmm.sse.data[i]);
+    }
+  };
 
   for (unsigned i = 0; i < NumRegs; ++i) {
-    OrderedNode *XMMReg = _LoadContext(16, FPRClass, offsetof(FEXCore::Core::CPUState, xmm[i]));
+    OrderedNode *XMMReg = _LoadContext(16, FPRClass, GetXMMOffset(i));
     OrderedNode *MemLocation = _Add(Mem, _Constant(i * 16 + 160));
 
     _StoreMem(FPRClass, 16, MemLocation, XMMReg, 16);
@@ -1439,12 +1453,20 @@ void OpDispatchBuilder::FXRStoreOp(OpcodeArgs) {
     auto MMReg = _LoadMem(FPRClass, 16, MemLocation, 16);
     _StoreContext(16, FPRClass, MMReg, offsetof(FEXCore::Core::CPUState, mm[i]));
   }
-  unsigned NumRegs = CTX->Config.Is64BitMode ? 16 : 8;
+
+  const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
+  const auto GetXMMOffset = [this](size_t i) {
+    if (CTX->HostFeatures.SupportsAVX) {
+      return offsetof(Core::CPUState, xmm.avx.data[i]);
+    } else {
+      return offsetof(Core::CPUState, xmm.sse.data[i]);
+    }
+  };
 
   for (unsigned i = 0; i < NumRegs; ++i) {
     OrderedNode *MemLocation = _Add(Mem, _Constant(i * 16 + 160));
     auto XMMReg = _LoadMem(FPRClass, 16, MemLocation, 16);
-    _StoreContext(16, FPRClass, XMMReg, offsetof(FEXCore::Core::CPUState, xmm[i]));
+    _StoreContext(16, FPRClass, XMMReg, GetXMMOffset(i));
   }
 }
 
@@ -1590,8 +1612,12 @@ void OpDispatchBuilder::MOVQ2DQ(OpcodeArgs) {
 
   // This instruction is a bit special in that if the source is MMX then it zexts to 128bit
   if constexpr (ToXMM) {
+    const auto Index = Op->Dest.Data.GPR.GPR - FEXCore::X86State::REG_XMM_0;
+    const auto Offset = CTX->HostFeatures.SupportsAVX ? offsetof(FEXCore::Core::CPUState, xmm.avx.data[Index][0])
+                                                      : offsetof(FEXCore::Core::CPUState, xmm.sse.data[Index][0]);
+
     Src = _VMov(16, Src);
-    _StoreContext(16, FPRClass, Src, offsetof(FEXCore::Core::CPUState, xmm[Op->Dest.Data.GPR.GPR - FEXCore::X86State::REG_XMM_0][0]));
+    _StoreContext(16, FPRClass, Src, Offset);
   }
   else {
     // This is simple, just store the result
@@ -2356,7 +2382,7 @@ void OpDispatchBuilder::VectorVariableBlend(OpcodeArgs) {
   OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
 
   // The mask is hardcoded to be xmm0 in this instruction
-  OrderedNode *Mask = _LoadContext(16, FPRClass, offsetof(FEXCore::Core::CPUState, xmm[0]));
+  OrderedNode *Mask = _LoadContext(16, FPRClass, offsetof(FEXCore::Core::CPUState, xmm.avx.data[0]));
   // Each element is selected by the high bit of that element size
   // Dest[ElementIdx] = Xmm0[ElementIndex][HighBit] ? Src : Dest;
   //

External/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h

@@ -33,7 +33,7 @@ static inline void GenerateTable(X86InstInfo *FinalTable, X86TablesInfoStruct<Op
     auto OpNum = Op.first;
     X86InstInfo const &Info = Op.Info;
     for (uint32_t i = 0; i < Op.second; ++i) {
-      LOGMAN_THROW_A_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
+      LOGMAN_THROW_AA_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
       FinalTable[OpNum + i] = Info;
 #ifndef NDEBUG
       ++Total;
@@ -51,7 +51,7 @@ static inline void GenerateTableWithCopy(X86InstInfo *FinalTable, X86TablesInfoS
     auto OpNum = Op.first;
     X86InstInfo const &Info = Op.Info;
     for (uint32_t i = 0; i < Op.second; ++i) {
-      LOGMAN_THROW_A_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
+      LOGMAN_THROW_AA_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
       if (Info.Type == TYPE_COPY_OTHER) {
         FinalTable[OpNum + i] = OtherLocal[OpNum + i];
       }
@@ -74,7 +74,7 @@ static inline void GenerateX87Table(X86InstInfo *FinalTable, X86TablesInfoStruct
     auto OpNum = Op.first;
     X86InstInfo const &Info = Op.Info;
     for (uint32_t i = 0; i < Op.second; ++i) {
-      LOGMAN_THROW_A_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
+      LOGMAN_THROW_AA_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
       if ((OpNum & 0b11'000'000) == 0b11'000'000) {
         // If the mod field is 0b11 then it is a regular op
         FinalTable[OpNum + i] = Info;
@@ -82,7 +82,7 @@ static inline void GenerateX87Table(X86InstInfo *FinalTable, X86TablesInfoStruct
       else {
         // If the mod field is !0b11 then this instruction is duplicated through the whole mod [0b00, 0b10] range
         // and the modrm.rm space because that is used part of the instruction encoding
-        LOGMAN_THROW_A_FMT((OpNum & 0b11'000'000) == 0, "Only support mod field of zero in this path");
+        LOGMAN_THROW_AA_FMT((OpNum & 0b11'000'000) == 0, "Only support mod field of zero in this path");
         for (uint16_t mod = 0b00'000'000; mod < 0b11'000'000; mod += 0b01'000'000) {
           for (uint16_t rm = 0b000; rm < 0b1'000; ++rm) {
             FinalTable[(OpNum | mod | rm) + i] = Info;

External/FEXCore/Source/Interface/HLE/Thunks/Thunks.cpp

@@ -28,6 +28,10 @@ $end_info$
 #include <string>
 #include <utility>
 
+#ifdef ENABLE_JEMALLOC
+#include "jemalloc/jemalloc.h"
+#endif
+
 struct LoadlibArgs {
     const char *Name;
 };
@@ -66,12 +70,23 @@ namespace FEXCore {
     struct ExportEntry { uint8_t *sha256; ThunkedFunction* Fn; };
 
     struct TrampolineInstanceInfo {
-      uintptr_t HostPacker;
+      void* HostPacker;
       uintptr_t CallCallback;
       uintptr_t GuestUnpacker;
       uintptr_t GuestTarget;
     };
 
+    // Opaque type pointing to an instance of HostToGuestTrampolineTemplate and its
+    // embedded TrampolineInstanceInfo
+    struct HostToGuestTrampolinePtr;
+    const auto HostToGuestTrampolineSize = __stop_HostToGuestTrampolineTemplate - __start_HostToGuestTrampolineTemplate;
+
+    static TrampolineInstanceInfo& GetInstanceInfo(HostToGuestTrampolinePtr* Trampoline) {
+      const auto Length = __stop_HostToGuestTrampolineTemplate - __start_HostToGuestTrampolineTemplate;
+      const auto InstanceInfoOffset = Length - sizeof(TrampolineInstanceInfo);
+      return *reinterpret_cast<TrampolineInstanceInfo*>(reinterpret_cast<char*>(Trampoline) + InstanceInfoOffset);
+    }
+
     struct GuestcallInfo {
       uintptr_t GuestUnpacker;
       uintptr_t GuestTarget;
@@ -94,7 +109,9 @@ namespace FEXCore {
       }
     };
 
-    class ThunkHandler_impl final: public ThunkHandler {
+    HostToGuestTrampolinePtr* MakeHostTrampolineForGuestFunction(void* HostPacker, uintptr_t GuestTarget, uintptr_t GuestUnpacker);
+
+    struct ThunkHandler_impl final: public ThunkHandler {
         std::shared_mutex ThunksMutex;
 
         std::unordered_map<IR::SHA256Sum, ThunkedFunction*, TruncatingSHA256Hash> Thunks = {
@@ -108,23 +125,28 @@ namespace FEXCore {
                 { 0xee, 0x57, 0xba, 0x0c, 0x5f, 0x6e, 0xef, 0x2a, 0x8c, 0xb5, 0x19, 0x81, 0xc9, 0x23, 0xe6, 0x51, 0xae, 0x65, 0x02, 0x8f, 0x2b, 0x5d, 0x59, 0x90, 0x6a, 0x7e, 0xe2, 0xe7, 0x1c, 0x33, 0x8a, 0xff },
                 &IsLibLoaded
             },
+            {
+                // sha256(fex:is_host_heap_allocation)
+                { 0xf5, 0x77, 0x68, 0x43, 0xbb, 0x6b, 0x28, 0x18, 0x40, 0xb0, 0xdb, 0x8a, 0x66, 0xfb, 0x0e, 0x2d, 0x98, 0xc2, 0xad, 0xe2, 0x5a, 0x18, 0x5a, 0x37, 0x2e, 0x13, 0xc9, 0xe7, 0xb9, 0x8c, 0xa9, 0x3e },
+                &IsHostHeapAllocation
+            },
             {
                 // sha256(fex:link_address_to_function)
                 { 0xe6, 0xa8, 0xec, 0x1c, 0x7b, 0x74, 0x35, 0x27, 0xe9, 0x4f, 0x5b, 0x6e, 0x2d, 0xc9, 0xa0, 0x27, 0xd6, 0x1f, 0x2b, 0x87, 0x8f, 0x2d, 0x35, 0x50, 0xea, 0x16, 0xb8, 0xc4, 0x5e, 0x42, 0xfd, 0x77 },
                 &LinkAddressToGuestFunction
             },
             {
-                // sha256(fex:make_host_trampoline_for_guest_function)
-                { 0x1e, 0x51, 0x6b, 0x07, 0x39, 0xeb, 0x50, 0x59, 0xb3, 0xf3, 0x4f, 0xca, 0xdd, 0x58, 0x37, 0xe9, 0xf0, 0x30, 0xe5, 0x89, 0x81, 0xc7, 0x14, 0xfb, 0x24, 0xf9, 0xba, 0xe7, 0x0e, 0x00, 0x1e, 0x86 },
-                &MakeHostTrampolineForGuestFunction
-            }
+                // sha256(fex:allocate_host_trampoline_for_guest_function)
+                { 0x9b, 0xb2, 0xf4, 0xb4, 0x83, 0x7d, 0x28, 0x93, 0x40, 0xcb, 0xf4, 0x7a, 0x0b, 0x47, 0x85, 0x87, 0xf9, 0xbc, 0xb5, 0x27, 0xca, 0xa6, 0x93, 0xa5, 0xc0, 0x73, 0x27, 0x24, 0xae, 0xc8, 0xb8, 0x5a },
+                &AllocateHostTrampolineForGuestFunction
+            },
         };
 
         // Can't be a string_view. We need to keep a copy of the library name in-case string_view pointer goes away.
         // Ideally we track when a library has been unloaded and remove it from this set before the memory backing goes away.
         std::set<std::string> Libs;
 
-        std::unordered_map<GuestcallInfo, uintptr_t, GuestcallInfoHash> GuestcallToHostTrampoline;
+        std::unordered_map<GuestcallInfo, HostToGuestTrampolinePtr*, GuestcallInfoHash> GuestcallToHostTrampoline;
 
         uint8_t *HostTrampolineInstanceDataPtr;
         size_t HostTrampolineInstanceDataAvailable = 0;
@@ -157,11 +179,11 @@ namespace FEXCore {
             auto args = reinterpret_cast<args_t*>(argsv);
             auto CTX = Thread->CTX;
 
-            LOGMAN_THROW_A_FMT(args->original_callee, "Tried to link null pointer address to guest function");
-            LOGMAN_THROW_A_FMT(args->target_addr, "Tried to link address to null pointer guest function");
+            LOGMAN_THROW_AA_FMT(args->original_callee, "Tried to link null pointer address to guest function");
+            LOGMAN_THROW_AA_FMT(args->target_addr, "Tried to link address to null pointer guest function");
             if (!CTX->Config.Is64BitMode) {
-                LOGMAN_THROW_A_FMT((args->original_callee >> 32) == 0, "Tried to link 64-bit address in 32-bit mode");
-                LOGMAN_THROW_A_FMT((args->target_addr >> 32) == 0, "Tried to link 64-bit address in 32-bit mode");
+                LOGMAN_THROW_AA_FMT((args->original_callee >> 32) == 0, "Tried to link 64-bit address in 32-bit mode");
+                LOGMAN_THROW_AA_FMT((args->target_addr >> 32) == 0, "Tried to link 64-bit address in 32-bit mode");
             }
 
             LogMan::Msg::DFmt("Thunks: Adding guest trampoline from address {:#x} to guest function {:#x}",
@@ -194,98 +216,44 @@ namespace FEXCore {
         }
 
         /**
-         * Generates a host-callable trampoline to call guest functions via the host ABI.
+         * Guest-side helper to initiate creation of a host trampoline for
+         * calling guest functions. This must be followed by a host-side call
+         * to FinalizeHostTrampolineForGuestFunction to make the trampoline
+         * usable.
          *
-         * This trampoline uses the same calling convention as the given HostPacker. Trampolines
-         * are cached, so it's safe to call this function repeatedly on the same arguments without
-         * leaking memory.
-         *
-         * Invoking the returned trampoline has the effect of:
-         * - packing the arguments (using the HostPacker identified by its SHA256)
-         * - performing a host->guest transition
-         * - unpacking the arguments via GuestUnpacker
-         * - calling the function at GuestTarget
-         *
-         * The primary use case of this is ensuring that guest function pointers ("callbacks")
-         * passed to thunked APIs can safely be called by the native host library.
+         * This two-step initialization is equivalent to a host-side call to
+         * MakeHostTrampolineForGuestFunction. The split is needed if the
+         * host doesn't have all information needed to create the trampoline
+         * on its own.
          */
-        static void MakeHostTrampolineForGuestFunction(void* ArgsRV) {
-          struct ArgsRV_t {
-              IR::SHA256Sum *HostPackerSha256;
-              uintptr_t GuestUnpacker;
-              uintptr_t GuestTarget;
-              uintptr_t rv; // Pointer to host trampoline + TrampolineInstanceInfo
-          } *args = reinterpret_cast<ArgsRV_t*>(ArgsRV);
+        static void AllocateHostTrampolineForGuestFunction(void* ArgsRV) {
+            struct ArgsRV_t {
+                uintptr_t GuestUnpacker;
+                uintptr_t GuestTarget;
+                uintptr_t rv; // Pointer to host trampoline + TrampolineInstanceInfo
+            } *args = reinterpret_cast<ArgsRV_t*>(ArgsRV);
 
-          LOGMAN_THROW_A_FMT(args->GuestTarget, "Tried to create host-trampoline to null pointer guest function");
+            args->rv = (uintptr_t)MakeHostTrampolineForGuestFunction(nullptr, args->GuestTarget, args->GuestUnpacker);
+        }
 
-          const auto CTX = Thread->CTX;
-          const auto ThunkHandler = reinterpret_cast<ThunkHandler_impl *>(CTX->ThunkHandler.get());
+        /**
+         * Checks if the given pointer is allocated on the host heap.
+         *
+         * This is useful for thunking APIs that need to work with both guest
+         * and host heap pointers.
+         */
+        static void IsHostHeapAllocation(void* ArgsRV) {
+#ifdef ENABLE_JEMALLOC
+            struct ArgsRV_t {
+                void* ptr;
+                bool rv;
+            } *args = reinterpret_cast<ArgsRV_t*>(ArgsRV);
 
-          const GuestcallInfo gci = { args->GuestUnpacker, args->GuestTarget };
-
-          // Try first with shared_lock
-          {
-            std::shared_lock lk(ThunkHandler->ThunksMutex);
-
-            auto found = ThunkHandler->GuestcallToHostTrampoline.find(gci);
-            if (found != ThunkHandler->GuestcallToHostTrampoline.end()) {
-              args->rv = found->second;
-              return;
-            }
-          }
-
-          std::lock_guard lk(ThunkHandler->ThunksMutex);
-
-          // Retry lookup with full lock before making a new trampoline to avoid double trampolines
-          {
-            auto found = ThunkHandler->GuestcallToHostTrampoline.find(gci);
-            if (found != ThunkHandler->GuestcallToHostTrampoline.end()) {
-              args->rv = found->second;
-              return;
-            }
-          }
-
-          // No entry found => create new trampoline
-          auto HostPackerEntry = ThunkHandler->Thunks.find(*args->HostPackerSha256);
-          if (HostPackerEntry == ThunkHandler->Thunks.end()) {
-            ERROR_AND_DIE_FMT("Unknown host packing function for callback");
-          }
-
-          LogMan::Msg::DFmt("Thunks: Adding host trampoline for guest function {:#x}",
-                            args->GuestTarget);
-
-          const auto Length = __stop_HostToGuestTrampolineTemplate - __start_HostToGuestTrampolineTemplate;
-          const auto InstanceInfoOffset = Length - sizeof(TrampolineInstanceInfo);
-
-          if (ThunkHandler->HostTrampolineInstanceDataAvailable < Length) {
-            const auto allocation_step = 16 * 1024;
-            ThunkHandler->HostTrampolineInstanceDataAvailable = allocation_step;
-            ThunkHandler->HostTrampolineInstanceDataPtr = (uint8_t *)mmap(
-                0, ThunkHandler->HostTrampolineInstanceDataAvailable,
-                PROT_READ | PROT_WRITE | PROT_EXEC,
-                MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
-
-            LOGMAN_THROW_A_FMT(ThunkHandler->HostTrampolineInstanceDataPtr != MAP_FAILED, "Failed to mmap HostTrampolineInstanceDataPtr");
-          }
-
-          const TrampolineInstanceInfo NewTrampolineInfo {
-            .HostPacker = reinterpret_cast<uintptr_t>(HostPackerEntry->second),
-            .CallCallback = (uintptr_t)&CallCallback,
-            .GuestUnpacker = args->GuestUnpacker,
-            .GuestTarget = args->GuestTarget
-          };
-
-          uint8_t* const HostTrampoline = ThunkHandler->HostTrampolineInstanceDataPtr;
-          ThunkHandler->HostTrampolineInstanceDataAvailable -= Length;
-          ThunkHandler->HostTrampolineInstanceDataPtr += Length;
-
-          memcpy(HostTrampoline, (void*)&HostToGuestTrampolineTemplate, Length);
-          memcpy(HostTrampoline + InstanceInfoOffset, &NewTrampolineInfo, sizeof(NewTrampolineInfo));
-
-          args->rv = reinterpret_cast<uintptr_t>(HostTrampoline);
-
-          ThunkHandler->GuestcallToHostTrampoline[gci] = args->rv;
+            args->rv = je_is_known_allocation(args->ptr);
+#else
+            // Thunks usage without jemalloc isn't supported
+            ERROR_AND_DIE_FMT("Unsupported: Thunks querying for host heap allocation information");
+#endif
         }
 
         static void LoadLib(void *ArgsV) {
@@ -352,9 +320,7 @@ namespace FEXCore {
             }
         }
 
-        public:
-
-        ThunkedFunction* LookupThunk(const IR::SHA256Sum &sha256) {
+        ThunkedFunction* LookupThunk(const IR::SHA256Sum &sha256) override {
 
             std::shared_lock lk(ThunksMutex);
 
@@ -367,12 +333,112 @@ namespace FEXCore {
             }
         }
 
-        void RegisterTLSState(FEXCore::Core::InternalThreadState *Thread) {
+        void RegisterTLSState(FEXCore::Core::InternalThreadState *Thread) override {
             ::Thread = Thread;
         }
+
+        void AppendThunkDefinitions(std::vector<FEXCore::IR::ThunkDefinition> const& Definitions) override {
+          for (auto & Definition : Definitions) {
+            Thunks.emplace(Definition.Sum, Definition.ThunkFunction);
+          }
+        }
     };
 
     ThunkHandler* ThunkHandler::Create() {
-        return new ThunkHandler_impl();
+      return new ThunkHandler_impl();
+    }
+
+    /**
+     * Generates a host-callable trampoline to call guest functions via the host ABI.
+     *
+     * This trampoline uses the same calling convention as the given HostPacker. Trampolines
+     * are cached, so it's safe to call this function repeatedly on the same arguments without
+     * leaking memory.
+     *
+     * Invoking the returned trampoline has the effect of:
+     * - packing the arguments (using the HostPacker identified by its SHA256)
+     * - performing a host->guest transition
+     * - unpacking the arguments via GuestUnpacker
+     * - calling the function at GuestTarget
+     *
+     * The primary use case of this is ensuring that guest function pointers ("callbacks")
+     * passed to thunked APIs can safely be called by the native host library.
+     *
+     * Returns a pointer to the generated host trampoline and its TrampolineInstanceInfo.
+     *
+     * If HostPacker is zero, the trampoline will be partially initialized and needs to be
+     * finalized with a call to FinalizeHostTrampolineForGuestFunction. A typical use case
+     * is to allocate the trampoline for a given GuestTarget/GuestUnpacker on the guest-side,
+     * and provide the HostPacker host-side.
+     */
+    FEX_DEFAULT_VISIBILITY
+    HostToGuestTrampolinePtr* MakeHostTrampolineForGuestFunction(void* HostPacker, uintptr_t GuestTarget, uintptr_t GuestUnpacker) {
+      LOGMAN_THROW_AA_FMT(GuestTarget, "Tried to create host-trampoline to null pointer guest function");
+
+      const auto CTX = Thread->CTX;
+      const auto ThunkHandler = reinterpret_cast<ThunkHandler_impl *>(CTX->ThunkHandler.get());
+
+      const GuestcallInfo gci = { GuestUnpacker, GuestTarget };
+
+      // Try first with shared_lock
+      {
+        std::shared_lock lk(ThunkHandler->ThunksMutex);
+
+        auto found = ThunkHandler->GuestcallToHostTrampoline.find(gci);
+        if (found != ThunkHandler->GuestcallToHostTrampoline.end()) {
+          return found->second;
+        }
+      }
+
+      std::lock_guard lk(ThunkHandler->ThunksMutex);
+
+      // Retry lookup with full lock before making a new trampoline to avoid double trampolines
+      {
+        auto found = ThunkHandler->GuestcallToHostTrampoline.find(gci);
+        if (found != ThunkHandler->GuestcallToHostTrampoline.end()) {
+          return found->second;
+        }
+      }
+
+      LogMan::Msg::DFmt("Thunks: Adding host trampoline for guest function {:#x} via unpacker {:#x}",
+                        GuestTarget, GuestUnpacker);
+
+      if (ThunkHandler->HostTrampolineInstanceDataAvailable < HostToGuestTrampolineSize) {
+        const auto allocation_step = 16 * 1024;
+        ThunkHandler->HostTrampolineInstanceDataAvailable = allocation_step;
+        ThunkHandler->HostTrampolineInstanceDataPtr = (uint8_t *)mmap(
+            0, ThunkHandler->HostTrampolineInstanceDataAvailable,
+            PROT_READ | PROT_WRITE | PROT_EXEC,
+            MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+
+        LOGMAN_THROW_AA_FMT(ThunkHandler->HostTrampolineInstanceDataPtr != MAP_FAILED, "Failed to mmap HostTrampolineInstanceDataPtr");
+      }
+
+      auto HostTrampoline = reinterpret_cast<HostToGuestTrampolinePtr* const>(ThunkHandler->HostTrampolineInstanceDataPtr);
+      ThunkHandler->HostTrampolineInstanceDataAvailable -= HostToGuestTrampolineSize;
+      ThunkHandler->HostTrampolineInstanceDataPtr += HostToGuestTrampolineSize;
+      memcpy(HostTrampoline, (void*)&HostToGuestTrampolineTemplate, HostToGuestTrampolineSize);
+      GetInstanceInfo(HostTrampoline) = TrampolineInstanceInfo {
+          .HostPacker = HostPacker,
+          .CallCallback = (uintptr_t)&ThunkHandler_impl::CallCallback,
+          .GuestUnpacker = GuestUnpacker,
+          .GuestTarget = GuestTarget
+      };
+
+      ThunkHandler->GuestcallToHostTrampoline[gci] = HostTrampoline;
+      return HostTrampoline;
+    }
+
+    FEX_DEFAULT_VISIBILITY
+    void FinalizeHostTrampolineForGuestFunction(HostToGuestTrampolinePtr* TrampolineAddress, void* HostPacker) {
+      auto& Trampoline = GetInstanceInfo(TrampolineAddress);
+
+      LOGMAN_THROW_A_FMT(Trampoline.CallCallback == (uintptr_t)&ThunkHandler_impl::CallCallback,
+                        "Invalid trampoline at {} passed to {}", fmt::ptr(TrampolineAddress), __FUNCTION__);
+
+      if (!Trampoline.HostPacker) {
+        LogMan::Msg::DFmt("Thunks: Finalizing trampoline at {} with host packer {}", fmt::ptr(TrampolineAddress), fmt::ptr(HostPacker));
+        Trampoline.HostPacker = HostPacker;
+      }
     }
 }

External/FEXCore/Source/Interface/HLE/Thunks/Thunks.h

@@ -6,6 +6,10 @@ $end_info$
 
 #pragma once
 
+#include <FEXCore/IR/IR.h>
+
+#include <vector>
+
 namespace FEXCore::Context {
   struct Context;
 }
@@ -28,5 +32,7 @@ namespace FEXCore {
         virtual ~ThunkHandler() { }
 
         static ThunkHandler* Create();
+
+        virtual void AppendThunkDefinitions(std::vector<FEXCore::IR::ThunkDefinition> const& Definitions) = 0;
     };
 };

External/FEXCore/Source/Interface/IR/AOTIR.cpp

@@ -127,7 +127,7 @@ namespace FEXCore::IR {
 
     auto Array = (AOTIRInlineIndex *)((char*)FilePtr + IndexOffset);
 
-    LOGMAN_THROW_A_FMT(Entry->Array == nullptr && Entry->FilePtr == nullptr, "Entry must not be initialized here");
+    LOGMAN_THROW_AA_FMT(Entry->Array == nullptr && Entry->FilePtr == nullptr, "Entry must not be initialized here");
     Entry->Array = Array;
     Entry->FilePtr = FilePtr;
     Entry->Size = Size;
@@ -387,7 +387,7 @@ namespace FEXCore::IR {
       auto Inserted = AOTIRCache.insert({fileid, AOTIRCacheEntry { .FileId = fileid, .Filename = filename }});
       auto Entry = &(Inserted.first->second);
 
-      LOGMAN_THROW_A_FMT(Entry->Array == nullptr, "Duplicate LoadAOTIRCacheEntry");
+      LOGMAN_THROW_AA_FMT(Entry->Array == nullptr, "Duplicate LoadAOTIRCacheEntry");
 
       if (CTX->Config.AOTIRLoad && AOTIRLoader) {
         auto streamfd = AOTIRLoader(fileid);
@@ -403,7 +403,7 @@ namespace FEXCore::IR {
   }
 
   void AOTIRCaptureCache::UnloadAOTIRCacheEntry(AOTIRCacheEntry *Entry) {
-    LOGMAN_THROW_A_FMT(Entry != nullptr, "Removing not existing entry");
+    LOGMAN_THROW_AA_FMT(Entry != nullptr, "Removing not existing entry");
 
     if (Entry->Array) {
       FEXCore::Allocator::munmap(Entry->FilePtr, Entry->Size);

External/FEXCore/Source/Interface/IR/IR.json

@@ -123,12 +123,12 @@
     "constexpr FEXCore::IR::MemOffsetType MEM_OFFSET_UXTW {1}",
     "constexpr FEXCore::IR::MemOffsetType MEM_OFFSET_SXTW {2}",
 
-    "constexpr FEXCore::IR::BreakReason Break_Unimplemented      {0}",
-    "constexpr FEXCore::IR::BreakReason Break_Interrupt          {1}",
-    "constexpr FEXCore::IR::BreakReason Break_Interrupt3         {2}",
-    "constexpr FEXCore::IR::BreakReason Break_Halt               {3}",
-    "constexpr FEXCore::IR::BreakReason Break_Overflow           {4}",
-    "constexpr FEXCore::IR::BreakReason Break_InvalidInstruction {5}"
+    "struct BreakDefinition {",
+    "  uint16_t ErrorRegister;",
+    "  uint8_t Signal;",
+    "  uint8_t TrapNumber;",
+    "  uint8_t si_code;",
+    "};"
   ],
   "IRTypes" : {
     "i1":  "bool",
@@ -150,7 +150,7 @@
     "SyscallFlags": "FEXCore::IR::SyscallFlags",
     "SHA256Sum": "SHA256Sum",
     "MemOffsetType": "MemOffsetType",
-    "BreakReason": "BreakReason",
+    "BreakDefinition": "BreakDefinition",
     "RoundType": "RoundType"
   },
   "Ops": {
@@ -192,7 +192,7 @@
         "DestSize": "8"
       },
 
-      "RemoveThreadCodeEntry": {
+      "ThreadRemoveCodeEntry": {
         "HasSideEffects": true
       },
 
@@ -261,7 +261,7 @@
         "HasSideEffects": true,
         "DestSize": "GetOpSize(_NewRIP)"
       },
-      "Break BreakReason:$Reason, u8:$Literal": {
+      "Break BreakDefinition:$Reason": {
         "HasSideEffects": true
       },
       "SignalReturn": {

External/FEXCore/Source/Interface/IR/IRDumper.cpp

@@ -182,7 +182,12 @@ static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const*
   }
 }
 
-
+static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::BreakDefinition Arg) {
+  *out << "{" << Arg.ErrorRegister << ".";
+  *out << static_cast<uint32_t>(Arg.Signal) << ".";
+  *out << static_cast<uint32_t>(Arg.TrapNumber) << ".";
+  *out << static_cast<uint32_t>(Arg.si_code) << "}";
+}
 
 void Dump(std::stringstream *out, IRListView const* IR, IR::RegisterAllocationData *RAData) {
   auto HeaderOp = IR->GetHeader();

External/FEXCore/Source/Interface/IR/IREmitter.cpp

@@ -8,6 +8,7 @@ $end_info$
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IREmitter.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
+#include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 
 #include <array>
@@ -87,7 +88,8 @@ FEXCore::IR::RegisterClassType IREmitter::WalkFindRegClass(OrderedNode *Node) {
       break;
     }
     default:
-      LOGMAN_MSG_A_FMT("Unhandled op type: {} {} in argument class validation", IROp->Op, GetOpName(Node));
+      LOGMAN_MSG_A_FMT("Unhandled op type: {} {} in argument class validation",
+                       ToUnderlying(IROp->Op), GetOpName(Node));
       break;
   }
   return InvalidClass;
@@ -167,7 +169,7 @@ IREmitter::IRPair<IROp_CodeBlock> IREmitter::CreateNewCodeBlockAfter(OrderedNode
   if (insertAfter) {
     LinkCodeBlocks(insertAfter, CodeNode);
   } else {
-    LOGMAN_THROW_A_FMT(CurrentCodeBlock != nullptr, "CurrentCodeBlock must not be null here");
+    LOGMAN_THROW_AA_FMT(CurrentCodeBlock != nullptr, "CurrentCodeBlock must not be null here");
 
     // Find last block
     auto LastBlock = CurrentCodeBlock;

External/FEXCore/Source/Interface/IR/IRParser.cpp

@@ -252,22 +252,36 @@ class IRParser: public FEXCore::IR::IREmitter {
   }
 
   template<>
-  std::pair<DecodeFailure, FEXCore::IR::BreakReason> DecodeValue(const std::string &Arg) {
-    static constexpr std::array<std::string_view, 6> Names = {
-      "Unimplemented",
-      "Interrupt",
-      "Interrupt3",
-      "Halt",
-      "Overfloat",
-      "InvalidInstruction",
-    };
+  std::pair<DecodeFailure, FEXCore::IR::BreakDefinition> DecodeValue(const std::string &Arg) {
+    uint32_t tmp{};
+    std::stringstream ss{Arg};
+    BreakDefinition Reason{};
 
-    for (size_t i = 0; i < Names.size(); ++i) {
-      if (Names[i] == Arg) {
-        return {DecodeFailure::DECODE_OKAY, BreakReason{static_cast<uint8_t>(i)}};
-      }
+    // Seek past '{'
+    ss.seekg(1, std::ios::cur);
+    ss >> Reason.ErrorRegister;
+
+    // Seek past '.'
+    ss.seekg(1, std::ios::cur);
+    ss >> tmp;
+    Reason.Signal = tmp;
+
+    // Seek past '.'
+    ss.seekg(1, std::ios::cur);
+    ss >> tmp;
+    Reason.TrapNumber = tmp;
+
+    // Seek past '.'
+    ss.seekg(1, std::ios::cur);
+    ss >> tmp;
+    Reason.si_code = tmp;
+
+    if (ss.fail()) {
+      return {DecodeFailure::DECODE_INVALIDCHAR, {}};
+    }
+    else {
+      return {DecodeFailure::DECODE_OKAY, Reason};
     }
-    return {DecodeFailure::DECODE_INVALID_BREAKTYPE, {}};
   }
 
   template<>

External/FEXCore/Source/Interface/IR/PassManager.cpp

@@ -20,7 +20,7 @@ void PassManager::AddDefaultPasses(FEXCore::Context::Context *ctx, bool InlineCo
   FEX_CONFIG_OPT(DisablePasses, O0);
 
   if (!DisablePasses()) {
-    InsertPass(CreateContextLoadStoreElimination());
+    InsertPass(CreateContextLoadStoreElimination(ctx->HostFeatures.SupportsAVX));
 
     if (Is64BitMode()) {
       // This needs to run after RCLSE
@@ -28,7 +28,7 @@ void PassManager::AddDefaultPasses(FEXCore::Context::Context *ctx, bool InlineCo
       InsertPass(CreateLongDivideEliminationPass());
     }
 
-    InsertPass(CreateDeadStoreElimination());
+    InsertPass(CreateDeadStoreElimination(ctx->HostFeatures.SupportsAVX));
     InsertPass(CreatePassDeadCodeElimination());
     InsertPass(CreateConstProp(InlineConstants, ctx->HostFeatures.SupportsTSOImm9));
 
@@ -39,12 +39,12 @@ void PassManager::AddDefaultPasses(FEXCore::Context::Context *ctx, bool InlineCo
 
     // only do SRA if enabled and JIT
     if (InlineConstants && StaticRegisterAllocation)
-      InsertPass(CreateStaticRegisterAllocationPass());
+      InsertPass(CreateStaticRegisterAllocationPass(ctx->HostFeatures.SupportsAVX));
   }
   else {
     // only do SRA if enabled and JIT
     if (InlineConstants && StaticRegisterAllocation)
-      InsertPass(CreateStaticRegisterAllocationPass());
+      InsertPass(CreateStaticRegisterAllocationPass(ctx->HostFeatures.SupportsAVX));
   }
 
   // If the IR is compacted post-RA then the node indexing gets messed up and the backend isn't able to find the register assigned to a node
@@ -61,8 +61,8 @@ void PassManager::AddDefaultValidationPasses() {
 #endif
 }
 
-void PassManager::InsertRegisterAllocationPass(bool OptimizeSRA) {
-  InsertPass(IR::CreateRegisterAllocationPass(GetPass("Compaction"), OptimizeSRA), "RA");
+void PassManager::InsertRegisterAllocationPass(bool OptimizeSRA, bool SupportsAVX) {
+  InsertPass(IR::CreateRegisterAllocationPass(GetPass("Compaction"), OptimizeSRA, SupportsAVX), "RA");
 }
 
 bool PassManager::Run(IREmitter *IREmit) {

External/FEXCore/Source/Interface/IR/PassManager.h

@@ -52,7 +52,7 @@ public:
     return PassPtr;
   }
 
-  void InsertRegisterAllocationPass(bool OptimizeSRA);
+  void InsertRegisterAllocationPass(bool OptimizeSRA, bool SupportsAVX);
 
   bool Run(IREmitter *IREmit);
 

External/FEXCore/Source/Interface/IR/Passes.h

@@ -12,14 +12,16 @@ class RegisterAllocationPass;
 class RegisterAllocationData;
 
 std::unique_ptr<FEXCore::IR::Pass> CreateConstProp(bool InlineConstants, bool SupportsTSOImm9);
-std::unique_ptr<FEXCore::IR::Pass> CreateContextLoadStoreElimination();
+std::unique_ptr<FEXCore::IR::Pass> CreateContextLoadStoreElimination(bool SupportsAVX);
 std::unique_ptr<FEXCore::IR::Pass> CreateSyscallOptimization();
 std::unique_ptr<FEXCore::IR::Pass> CreateDeadFlagCalculationEliminination();
-std::unique_ptr<FEXCore::IR::Pass> CreateDeadStoreElimination();
+std::unique_ptr<FEXCore::IR::Pass> CreateDeadStoreElimination(bool SupportsAVX);
 std::unique_ptr<FEXCore::IR::Pass> CreatePassDeadCodeElimination();
 std::unique_ptr<FEXCore::IR::Pass> CreateIRCompaction(FEXCore::Utils::IntrusivePooledAllocator &Allocator);
-std::unique_ptr<FEXCore::IR::RegisterAllocationPass> CreateRegisterAllocationPass(FEXCore::IR::Pass* CompactionPass, bool OptimizeSRA);
-std::unique_ptr<FEXCore::IR::Pass> CreateStaticRegisterAllocationPass();
+std::unique_ptr<FEXCore::IR::RegisterAllocationPass> CreateRegisterAllocationPass(FEXCore::IR::Pass* CompactionPass,
+                                                                                  bool OptimizeSRA,
+                                                                                  bool SupportsAVX);
+std::unique_ptr<FEXCore::IR::Pass> CreateStaticRegisterAllocationPass(bool SupportsAVX);
 std::unique_ptr<FEXCore::IR::Pass> CreateLongDivideEliminationPass();
 
 namespace Validation {

External/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp

@@ -299,7 +299,7 @@ void ConstProp::FCMPOptimization(IREmitter *IREmit, const IRListView& CurrentIR)
       auto ghf = IROp->CW<IR::IROp_GetHostFlag>();
 
       auto fcmp = IREmit->GetOpHeader(ghf->Value)->CW<IR::IROp_FCmp>();
-      LOGMAN_THROW_A_FMT(fcmp->Header.Op == OP_FCMP || fcmp->Header.Op == OP_F80CMP, "Unexpected OP_GETHOSTFLAG source");
+      LOGMAN_THROW_AA_FMT(fcmp->Header.Op == OP_FCMP || fcmp->Header.Op == OP_F80CMP, "Unexpected OP_GETHOSTFLAG source");
       if(fcmp->Header.Op == OP_FCMP) {
         fcmp->Flags |= 1 << ghf->Flag;
       }

External/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp

@@ -25,7 +25,7 @@ $end_info$
 namespace {
   struct ContextMemberClassification {
     size_t Offset;
-    uint8_t Size;
+    uint16_t Size;
   };
 
   enum LastAccessType {
@@ -76,10 +76,7 @@ namespace {
     std::vector<ContextMemberInfo> ClassificationInfo;
   };
 
-  constexpr static std::array<LastAccessType, 16> DefaultAccess = {
-    ACCESS_NONE,
-    ACCESS_NONE,
-    ACCESS_INVALID, // PAD
+  constexpr static std::array<LastAccessType, 15> DefaultAccess = {
     ACCESS_NONE,
     ACCESS_NONE,
     ACCESS_NONE,
@@ -88,14 +85,16 @@ namespace {
     ACCESS_NONE,
     ACCESS_NONE,
     ACCESS_NONE,
-    ACCESS_INVALID, // PAD
+    ACCESS_NONE,
+    ACCESS_INVALID, // SSE padding in non-AVX case
+    ACCESS_NONE,
     ACCESS_NONE,
     ACCESS_NONE,
     ACCESS_NONE,
     ACCESS_NONE,
   };
 
-  static void ClassifyContextStruct(ContextInfo *ContextClassificationInfo) {
+  static void ClassifyContextStruct(ContextInfo *ContextClassificationInfo, bool SupportsAVX) {
     auto ContextClassification = &ContextClassificationInfo->ClassificationInfo;
 
     ContextClassification->emplace_back(ContextMemberInfo{
@@ -118,32 +117,12 @@ namespace {
       });
     }
 
-    ContextClassification->emplace_back(ContextMemberInfo{
-      ContextMemberClassification {
-        offsetof(FEXCore::Core::CPUState, gregs[16]),
-        sizeof(uint64_t),
-      },
-      DefaultAccess[2], ///< NOP padding
-      FEXCore::IR::InvalidClass,
-    });
-
-    for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
-      ContextClassification->emplace_back(ContextMemberInfo{
-        ContextMemberClassification {
-          offsetof(FEXCore::Core::CPUState, xmm[0][0]) + sizeof(FEXCore::Core::CPUState::xmm[0]) * i,
-          FEXCore::Core::CPUState::XMM_REG_SIZE,
-        },
-        DefaultAccess[3],
-        FEXCore::IR::InvalidClass,
-      });
-    }
-
     ContextClassification->emplace_back(ContextMemberInfo{
       ContextMemberClassification {
         offsetof(FEXCore::Core::CPUState, es),
         sizeof(FEXCore::Core::CPUState::es),
       },
-      DefaultAccess[5],
+      DefaultAccess[2],
       FEXCore::IR::InvalidClass,
     });
 
@@ -152,7 +131,7 @@ namespace {
         offsetof(FEXCore::Core::CPUState, cs),
         sizeof(FEXCore::Core::CPUState::cs),
       },
-      DefaultAccess[6],
+      DefaultAccess[3],
       FEXCore::IR::InvalidClass,
     });
 
@@ -161,7 +140,7 @@ namespace {
         offsetof(FEXCore::Core::CPUState, ss),
         sizeof(FEXCore::Core::CPUState::ss),
       },
-      DefaultAccess[7],
+      DefaultAccess[4],
       FEXCore::IR::InvalidClass,
     });
 
@@ -170,7 +149,7 @@ namespace {
         offsetof(FEXCore::Core::CPUState, ds),
         sizeof(FEXCore::Core::CPUState::ds),
       },
-      DefaultAccess[8],
+      DefaultAccess[5],
       FEXCore::IR::InvalidClass,
     });
 
@@ -179,7 +158,7 @@ namespace {
         offsetof(FEXCore::Core::CPUState, gs),
         sizeof(FEXCore::Core::CPUState::gs),
       },
-      DefaultAccess[4],
+      DefaultAccess[6],
       FEXCore::IR::InvalidClass,
     });
 
@@ -188,10 +167,43 @@ namespace {
         offsetof(FEXCore::Core::CPUState, fs),
         sizeof(FEXCore::Core::CPUState::fs),
       },
-      DefaultAccess[9],
+      DefaultAccess[7],
       FEXCore::IR::InvalidClass,
     });
 
+    if (SupportsAVX) {
+      for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
+        ContextClassification->emplace_back(ContextMemberInfo{
+          ContextMemberClassification {
+            offsetof(FEXCore::Core::CPUState, xmm.avx.data[0][0]) + FEXCore::Core::CPUState::XMM_AVX_REG_SIZE * i,
+            FEXCore::Core::CPUState::XMM_AVX_REG_SIZE,
+          },
+          DefaultAccess[8],
+          FEXCore::IR::InvalidClass,
+        });
+      }
+    } else {
+      for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
+        ContextClassification->emplace_back(ContextMemberInfo{
+          ContextMemberClassification {
+            offsetof(FEXCore::Core::CPUState, xmm.sse.data[0][0]) + FEXCore::Core::CPUState::XMM_SSE_REG_SIZE * i,
+            FEXCore::Core::CPUState::XMM_SSE_REG_SIZE,
+          },
+          DefaultAccess[8],
+          FEXCore::IR::InvalidClass,
+        });
+      }
+
+      ContextClassification->emplace_back(ContextMemberInfo{
+          ContextMemberClassification {
+            offsetof(FEXCore::Core::CPUState, xmm.sse.pad[0][0]),
+            static_cast<uint16_t>(FEXCore::Core::CPUState::XMM_SSE_REG_SIZE * FEXCore::Core::CPUState::NUM_XMMS),
+          },
+          DefaultAccess[9],
+          FEXCore::IR::InvalidClass,
+        });
+    }
+
     for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_FLAGS; ++i) {
       ContextClassification->emplace_back(ContextMemberInfo{
         ContextMemberClassification {
@@ -203,22 +215,13 @@ namespace {
       });
     }
 
-    ContextClassification->emplace_back(ContextMemberInfo{
-      ContextMemberClassification {
-        offsetof(FEXCore::Core::CPUState, flags[48]),
-        sizeof(uint64_t),
-      },
-      DefaultAccess[11], ///< NOP padding
-      FEXCore::IR::InvalidClass,
-    });
-
     for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_MMS; ++i) {
       ContextClassification->emplace_back(ContextMemberInfo{
         ContextMemberClassification {
           offsetof(FEXCore::Core::CPUState, mm[0][0]) + sizeof(FEXCore::Core::CPUState::mm[0]) * i,
           FEXCore::Core::CPUState::MM_REG_SIZE
         },
-        DefaultAccess[12],
+        DefaultAccess[11],
         FEXCore::IR::InvalidClass,
       });
     }
@@ -230,7 +233,7 @@ namespace {
           offsetof(FEXCore::Core::CPUState, gdt[0]) + sizeof(FEXCore::Core::CPUState::gdt[0]) * i,
           sizeof(FEXCore::Core::CPUState::gdt[0]),
         },
-        DefaultAccess[13],
+        DefaultAccess[12],
         FEXCore::IR::InvalidClass,
       });
     }
@@ -241,7 +244,7 @@ namespace {
         offsetof(FEXCore::Core::CPUState, FCW),
         sizeof(FEXCore::Core::CPUState::FCW),
       },
-      DefaultAccess[14],
+      DefaultAccess[13],
       FEXCore::IR::InvalidClass,
     });
 
@@ -251,7 +254,7 @@ namespace {
         offsetof(FEXCore::Core::CPUState, FTW),
         sizeof(FEXCore::Core::CPUState::FTW),
       },
-      DefaultAccess[15],
+      DefaultAccess[14],
       FEXCore::IR::InvalidClass,
     });
 
@@ -266,7 +269,7 @@ namespace {
       ClassifiedStructSize += it.Class.Size;
     }
 
-    LOGMAN_THROW_A_FMT(ClassifiedStructSize == sizeof(FEXCore::Core::CPUState),
+    LOGMAN_THROW_AA_FMT(ClassifiedStructSize == sizeof(FEXCore::Core::CPUState),
       "Classified CPUStruct size doesn't match real CPUState struct size! {} (classified) != {} (real)",
       ClassifiedStructSize, sizeof(FEXCore::Core::CPUState));
 
@@ -275,7 +278,7 @@ namespace {
       ContextClassificationInfo->Lookup.size(), sizeof(FEXCore::Core::CPUState));
   }
 
-  static void ResetClassificationAccesses(ContextInfo *ContextClassificationInfo) {
+  static void ResetClassificationAccesses(ContextInfo *ContextClassificationInfo, bool SupportsAVX) {
     auto ContextClassification = &ContextClassificationInfo->ClassificationInfo;
 
     auto SetAccess = [&](size_t Offset, auto Access) {
@@ -289,36 +292,36 @@ namespace {
     for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_GPRS; ++i) {
       SetAccess(Offset++, DefaultAccess[1]);
     }
+
     SetAccess(Offset++, DefaultAccess[2]);
-
-    for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
-      SetAccess(Offset++, DefaultAccess[3]);
-    }
-
+    SetAccess(Offset++, DefaultAccess[3]);
     SetAccess(Offset++, DefaultAccess[4]);
     SetAccess(Offset++, DefaultAccess[5]);
     SetAccess(Offset++, DefaultAccess[6]);
     SetAccess(Offset++, DefaultAccess[7]);
-    SetAccess(Offset++, DefaultAccess[8]);
-    SetAccess(Offset++, DefaultAccess[9]);
 
+    for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
+      SetAccess(Offset++, DefaultAccess[8]);
+    }
+
+    if (!SupportsAVX) {
+      SetAccess(Offset++, DefaultAccess[9]);
+    }
 
     for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_FLAGS; ++i) {
       SetAccess(Offset++, DefaultAccess[10]);
     }
 
-    SetAccess(Offset++, DefaultAccess[11]);
-
     for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_MMS; ++i) {
-      SetAccess(Offset++, DefaultAccess[12]);
+      SetAccess(Offset++, DefaultAccess[11]);
     }
 
     for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_GDTS; ++i) {
-      SetAccess(Offset++, DefaultAccess[13]);
+      SetAccess(Offset++, DefaultAccess[12]);
     }
 
+    SetAccess(Offset++, DefaultAccess[13]);
     SetAccess(Offset++, DefaultAccess[14]);
-    SetAccess(Offset++, DefaultAccess[15]);
   }
 
   struct BlockInfo {
@@ -330,8 +333,8 @@ namespace {
 
 class RCLSE final : public FEXCore::IR::Pass {
 public:
-  RCLSE() {
-    ClassifyContextStruct(&ClassifiedStruct);
+  explicit RCLSE(bool SupportsAVX_) : SupportsAVX{SupportsAVX_} {
+    ClassifyContextStruct(&ClassifiedStruct, SupportsAVX);
     DCE = FEXCore::IR::CreatePassDeadCodeElimination();
   }
   bool Run(FEXCore::IR::IREmitter *IREmit) override;
@@ -341,6 +344,8 @@ private:
   ContextInfo ClassifiedStruct;
   std::unordered_map<FEXCore::IR::NodeID, BlockInfo> OffsetToBlockMap;
 
+  bool SupportsAVX;
+
   ContextMemberInfo *FindMemberInfo(ContextInfo *ClassifiedInfo, uint32_t Offset, uint8_t Size);
   ContextMemberInfo *RecordAccess(ContextMemberInfo *Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode = nullptr);
   ContextMemberInfo *RecordAccess(ContextInfo *ClassifiedInfo, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode = nullptr);
@@ -355,8 +360,8 @@ ContextMemberInfo *RCLSE::FindMemberInfo(ContextInfo *ContextClassificationInfo,
 }
 
 ContextMemberInfo *RCLSE::RecordAccess(ContextMemberInfo *Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode) {
-  LOGMAN_THROW_A_FMT((Offset + Size) <= (Info->Class.Offset + Info->Class.Size), "Access to context item went over member size");
-  LOGMAN_THROW_A_FMT(Info->Accessed != ACCESS_INVALID, "Tried to access invalid member");
+  LOGMAN_THROW_AA_FMT((Offset + Size) <= (Info->Class.Offset + Info->Class.Size), "Access to context item went over member size");
+  LOGMAN_THROW_AA_FMT(Info->Accessed != ACCESS_INVALID, "Tried to access invalid member");
 
   // If we aren't fully overwriting the member then it is a partial write that we need to track
   if (Size < Info->Class.Size) {
@@ -483,7 +488,7 @@ bool RCLSE::RedundantStoreLoadElimination(FEXCore::IR::IREmitter *IREmit) {
     auto BlockOp = BlockHeader->CW<FEXCore::IR::IROp_CodeBlock>();
     auto BlockEnd = IREmit->GetIterator(BlockOp->Last);
 
-    ResetClassificationAccesses(&LocalInfo);
+    ResetClassificationAccesses(&LocalInfo, SupportsAVX);
 
     for (auto [CodeNode, IROp] : CurrentIR.GetCode(BlockNode)) {
       if (IROp->Op == OP_STORECONTEXT) {
@@ -675,14 +680,14 @@ bool RCLSE::RedundantStoreLoadElimination(FEXCore::IR::IREmitter *IREmit) {
 
         if ((Flags & FEXCore::IR::SyscallFlags::OPTIMIZETHROUGH) != FEXCore::IR::SyscallFlags::OPTIMIZETHROUGH) {
           // We can't track through these
-          ResetClassificationAccesses(&LocalInfo);
+          ResetClassificationAccesses(&LocalInfo, SupportsAVX);
         }
       }
       else if (IROp->Op == OP_STORECONTEXTINDEXED ||
                IROp->Op == OP_LOADCONTEXTINDEXED ||
                IROp->Op == OP_BREAK) {
         // We can't track through these
-        ResetClassificationAccesses(&LocalInfo);
+        ResetClassificationAccesses(&LocalInfo, SupportsAVX);
       }
     }
   }
@@ -710,8 +715,8 @@ bool RCLSE::Run(FEXCore::IR::IREmitter *IREmit) {
 
 namespace FEXCore::IR {
 
-std::unique_ptr<FEXCore::IR::Pass> CreateContextLoadStoreElimination() {
-  return std::make_unique<RCLSE>();
+std::unique_ptr<FEXCore::IR::Pass> CreateContextLoadStoreElimination(bool SupportsAVX) {
+  return std::make_unique<RCLSE>(SupportsAVX);
 }
 
 }

External/FEXCore/Source/Interface/IR/Passes/DeadStoreElimination.cpp

@@ -24,7 +24,69 @@ constexpr int PropagationRounds = 5;
 
 class DeadStoreElimination final : public FEXCore::IR::Pass {
 public:
+  explicit DeadStoreElimination(bool SupportsAVX_) : SupportsAVX{SupportsAVX_} {}
+
   bool Run(IREmitter *IREmit) override;
+
+private:
+  bool SupportsAVX;
+
+  bool IsFPR(uint32_t Offset) const {
+    const auto [begin, end] = [this]() -> std::pair<ptrdiff_t, ptrdiff_t> {
+      if (SupportsAVX) {
+        return {
+          offsetof(FEXCore::Core::CpuStateFrame, State.xmm.avx.data[0][0]),
+          offsetof(FEXCore::Core::CpuStateFrame, State.xmm.avx.data[16][0])
+        };
+      } else {
+        return {
+          offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[0][0]),
+          offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[16][0])
+        };
+      }
+    }();
+
+    if (Offset < begin || Offset >= end)
+      return false;
+
+    return true;
+  }
+
+  bool IsTrackedWriteFPR(uint32_t Offset, uint8_t Size) const {
+    if (Size != 16 && Size != 8 && Size != 4)
+      return false;
+    if (Offset & 15)
+      return false;
+
+    return IsFPR(Offset);
+  }
+
+  uint64_t FPRBit(uint32_t Offset, uint32_t Size) const {
+    if (!IsFPR(Offset)) {
+      return 0;
+    }
+
+    const auto begin = offsetof(Core::CpuStateFrame, State.xmm.avx.data[0][0]);
+
+    const auto regSize = SupportsAVX ? Core::CPUState::XMM_AVX_REG_SIZE
+                                     : Core::CPUState::XMM_SSE_REG_SIZE;
+    const auto regn = (Offset - begin) / regSize;
+    const auto bitn = regn * 3;
+
+    if (!IsTrackedWriteFPR(Offset, Size))
+      return 7UL << (bitn);
+
+    if (Size == 16)
+      return  7UL << (bitn);
+    else if (Size == 8)
+      return  3UL << (bitn);
+    else if (Size == 4)
+      return  1UL << (bitn);
+    else
+      LOGMAN_MSG_A_FMT("Unexpected FPR size {}", Size);
+
+    return 7UL << (bitn); // Return maximum on failure case
+  }
 };
 
 struct FlagInfo {
@@ -74,60 +136,12 @@ struct FPRInfo {
   uint64_t kill { 0 };
 };
 
-bool IsFPR(uint32_t Offset) {
-
-  auto begin = offsetof(FEXCore::Core::CpuStateFrame, State.xmm[0][0]);
-  auto end = offsetof(FEXCore::Core::CpuStateFrame, State.xmm[16][0]);
-
-  if (Offset < begin || Offset >= end)
-    return false;
-
-  return true;
-}
-
-bool IsTrackedWriteFPR(uint32_t Offset, uint8_t Size) {
-  if (Size != 16 && Size != 8 && Size != 4)
-    return false;
-  if (Offset & 15)
-    return false;
-
-  return IsFPR(Offset);
-}
-
-
-
-uint64_t FPRBit(uint32_t Offset, uint32_t Size) {
-  if (!IsFPR(Offset)) {
-    return 0;
-  }
-
-  auto begin = offsetof(Core::CpuStateFrame, State.xmm[0][0]);
-
-  auto regn = (Offset - begin) / Core::CPUState::XMM_REG_SIZE;
-  auto bitn = regn * 3;
-
-  if (!IsTrackedWriteFPR(Offset, Size))
-    return 7UL << (bitn);
-
-  if (Size == 16)
-    return  7UL << (bitn);
-  else if (Size == 8)
-    return  3UL << (bitn);
-  else if (Size == 4)
-    return  1UL << (bitn);
-  else
-    LOGMAN_MSG_A_FMT("Unexpected FPR size {}", Size);
-
-  return 7UL << (bitn); // Return maximum on failure case
-}
-
 struct Info {
   FlagInfo flag;
   GPRInfo gpr;
   FPRInfo fpr;
 };
 
-
 /**
  * @brief This is a temporary pass to detect simple multiblock dead flag/gpr/fpr stores
  *
@@ -341,8 +355,8 @@ bool DeadStoreElimination::Run(IREmitter *IREmit) {
   return Changed;
 }
 
-std::unique_ptr<FEXCore::IR::Pass> CreateDeadStoreElimination() {
-  return std::make_unique<DeadStoreElimination>();
+std::unique_ptr<FEXCore::IR::Pass> CreateDeadStoreElimination(bool SupportsAVX) {
+  return std::make_unique<DeadStoreElimination>(SupportsAVX);
 }
 
 }

External/FEXCore/Source/Interface/IR/Passes/IRCompaction.cpp

@@ -77,7 +77,7 @@ bool IRCompaction::Run(IREmitter *IREmit) {
 
   auto HeaderNode = CurrentIR.GetHeaderNode();
   auto HeaderOp = CurrentIR.GetHeader();
-  LOGMAN_THROW_A_FMT(HeaderOp->Header.Op == OP_IRHEADER, "First op wasn't IRHeader");
+  LOGMAN_THROW_AA_FMT(HeaderOp->Header.Op == OP_IRHEADER, "First op wasn't IRHeader");
 
   // This compaction pass is something that we need to ensure correct ordering and distances between IROps
   // Later on we assume that an IROp's SSA value live range is its Node locations
@@ -101,7 +101,7 @@ bool IRCompaction::Run(IREmitter *IREmit) {
   {
     // Generate our codeblocks and link them together
     for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) {
-      LOGMAN_THROW_A_FMT(BlockHeader->Op == OP_CODEBLOCK, "IR type failed to be a code block");
+      LOGMAN_THROW_AA_FMT(BlockHeader->Op == OP_CODEBLOCK, "IR type failed to be a code block");
 
       auto LocalBlockIRNode = LocalBuilder._CodeBlock(LocalHeaderOp, LocalHeaderOp); // Use LocalHeaderOp as a dummy arg for now
       OldToNewRemap[CurrentIR.GetID(BlockNode).Value].NodeID = LocalIR.GetID(LocalBlockIRNode.Node);
@@ -165,7 +165,7 @@ bool IRCompaction::Run(IREmitter *IREmit) {
     for (auto &Block : GeneratedCodeBlocks) {
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
       auto BlockIROp = LocalIR.GetOp<FEXCore::IR::IROp_CodeBlock>(Block.NewNode);
-      LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == OP_CODEBLOCK, "IR type failed to be a code block");
+      LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == OP_CODEBLOCK, "IR type failed to be a code block");
 #endif
 
       for (auto [LocalNode, LocalIROp] : LocalIR.GetCode(Block.NewNode)) {

External/FEXCore/Source/Interface/IR/Passes/IRValidation.cpp

@@ -63,7 +63,7 @@ bool IRValidation::Run(IREmitter *IREmit) {
 
   for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) {
     auto BlockIROp = BlockHeader->CW<FEXCore::IR::IROp_CodeBlock>();
-    LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == OP_CODEBLOCK, "IR type failed to be a code block");
+    LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == OP_CODEBLOCK, "IR type failed to be a code block");
 
     if (!EntryBlock) {
       EntryBlock = BlockNode;

External/FEXCore/Source/Interface/IR/Passes/RAValidation.cpp

@@ -197,11 +197,11 @@ bool RAValidation::Run(IREmitter *IREmit) {
 
   // Get the control flow graph from the validation pass
   auto ValidationPass = Manager->GetPass<IRValidation>("IRValidation");
-  LOGMAN_THROW_A_FMT(ValidationPass != nullptr, "Couldn't find IRValidation pass");
+  LOGMAN_THROW_AA_FMT(ValidationPass != nullptr, "Couldn't find IRValidation pass");
 
   auto& OffsetToBlockMap = ValidationPass->OffsetToBlockMap;
 
-  LOGMAN_THROW_A_FMT(ValidationPass->EntryBlock != nullptr, "No entry point");
+  LOGMAN_THROW_AA_FMT(ValidationPass->EntryBlock != nullptr, "No entry point");
   BlocksToVisit.push_front(ValidationPass->EntryBlock); // Currently only a single entry point
 
   bool HadError = false;

External/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp

@@ -267,7 +267,7 @@ namespace {
 
   class ConstrainedRAPass final : public RegisterAllocationPass {
     public:
-      ConstrainedRAPass(FEXCore::IR::Pass* _CompactionPass, bool OptimizeSRA);
+      ConstrainedRAPass(FEXCore::IR::Pass* _CompactionPass, bool OptimizeSRA, bool SupportsAVX);
       ~ConstrainedRAPass();
       bool Run(IREmitter *IREmit) override;
 
@@ -293,6 +293,7 @@ namespace {
       RegisterGraph *Graph;
       FEXCore::IR::Pass* CompactionPass;
       bool OptimizeSRA;
+      bool SupportsAVX;
 
       std::vector<LiveRange> LiveRanges;
 
@@ -340,8 +341,8 @@ namespace {
       bool RunAllocateVirtualRegisters(IREmitter *IREmit);
   };
 
-  ConstrainedRAPass::ConstrainedRAPass(FEXCore::IR::Pass* _CompactionPass, bool _OptimizeSRA)
-    : CompactionPass {_CompactionPass}, OptimizeSRA(_OptimizeSRA) {
+  ConstrainedRAPass::ConstrainedRAPass(FEXCore::IR::Pass* _CompactionPass, bool _OptimizeSRA, bool _SupportsAVX)
+    : CompactionPass {_CompactionPass}, OptimizeSRA(_OptimizeSRA), SupportsAVX{_SupportsAVX} {
   }
 
   ConstrainedRAPass::~ConstrainedRAPass() {
@@ -349,8 +350,8 @@ namespace {
   }
 
   void ConstrainedRAPass::AllocateRegisterSet(uint32_t RegisterCount, uint32_t ClassCount) {
-    LOGMAN_THROW_A_FMT(RegisterCount <= INVALID_REG, "Up to {} regs supported", INVALID_REG);
-    LOGMAN_THROW_A_FMT(ClassCount <= INVALID_CLASS, "Up to {} classes supported", INVALID_CLASS);
+    LOGMAN_THROW_AA_FMT(RegisterCount <= INVALID_REG, "Up to {} regs supported", INVALID_REG);
+    LOGMAN_THROW_AA_FMT(ClassCount <= INVALID_CLASS, "Up to {} classes supported", INVALID_CLASS);
 
     Graph = AllocateRegisterGraph(ClassCount);
 
@@ -363,7 +364,7 @@ namespace {
   }
 
   void ConstrainedRAPass::AddRegisters(FEXCore::IR::RegisterClassType Class, uint32_t RegisterCount) {
-    LOGMAN_THROW_A_FMT(RegisterCount <= INVALID_REG, "Up to {} regs supported", INVALID_REG);
+    LOGMAN_THROW_AA_FMT(RegisterCount <= INVALID_REG, "Up to {} regs supported", INVALID_REG);
 
     AllocatePhysicalRegisters(Graph, Class, RegisterCount);
   }
@@ -396,7 +397,7 @@ namespace {
         const auto BeginID = Op->Begin.ID();
         const auto LastID = Op->Last.ID();
 
-        LOGMAN_THROW_A_FMT(Op->Header.Op == OP_CODEBLOCK, "Block not defined by codeblock?");
+        LOGMAN_THROW_AA_FMT(Op->Header.Op == OP_CODEBLOCK, "Block not defined by codeblock?");
 
         LiveRange->Begin = std::min(LiveRange->Begin, BeginID);
         LiveRange->End = std::max(LiveRange->End, BeginID);
@@ -453,7 +454,7 @@ namespace {
 
         // If the destination hasn't yet been set then set it now
         if (IROp->HasDest) {
-          LOGMAN_THROW_A_FMT(NodeLiveRange.Begin.Value == UINT32_MAX,
+          LOGMAN_THROW_AA_FMT(NodeLiveRange.Begin.Value == UINT32_MAX,
                              "Node begin already defined?");
           NodeLiveRange.Begin = Node;
           // Default to ending right where after it starts
@@ -491,7 +492,7 @@ namespace {
 
           const auto ArgNode = Arg.ID();
           auto& ArgNodeLiveRange = LiveRanges[ArgNode.Value];
-          LOGMAN_THROW_A_FMT(ArgNodeLiveRange.Begin.Value != UINT32_MAX,
+          LOGMAN_THROW_AA_FMT(ArgNodeLiveRange.Begin.Value != UINT32_MAX,
                              "%ssa{} used by %ssa{} before defined?", ArgNode, Node);
 
           const auto ArgNodeBlockID = Graph->Nodes[ArgNode.Value].Head.BlockID;
@@ -544,48 +545,62 @@ namespace {
 
     // Is an OP_STOREREGISTER eligible to write directly to the SRA reg?
     auto IsPreWritable = [](uint8_t Size, RegisterClassType StaticClass) {
+      LOGMAN_THROW_A_FMT(StaticClass == GPRFixedClass || StaticClass == FPRFixedClass, "Unexpected static class {}", StaticClass);
       if (StaticClass == GPRFixedClass) {
         return Size == 8;
       } else if (StaticClass == FPRFixedClass) {
         return Size == 16;
-      } else {
-        LOGMAN_THROW_A_FMT(false, "Unexpected static class {}", StaticClass);
       }
       return false; // Unknown
     };
 
     // Is an OP_LOADREGISTER eligible to read directly from the SRA reg?
     auto IsAliasable = [](uint8_t Size, RegisterClassType StaticClass, uint32_t Offset) {
+      LOGMAN_THROW_A_FMT(StaticClass == GPRFixedClass || StaticClass == FPRFixedClass, "Unexpected static class {}", StaticClass);
       if (StaticClass == GPRFixedClass) {
         // We need more meta info to support not-size-of-reg
         return (Size == 8 /*|| Size == 4*/) && ((Offset & 7) == 0);
       } else if (StaticClass == FPRFixedClass) {
         // We need more meta info to support not-size-of-reg
         return (Size == 16 /*|| Size == 8 || Size == 4*/) && ((Offset & 15) == 0);
-      } else {
-        LOGMAN_THROW_A_FMT(false, "Unexpected static class {}", StaticClass);
       }
       return false; // Unknown
     };
 
-    // Get SRA Reg and Class from a Context offset
-    auto GetRegAndClassFromOffset = [](uint32_t Offset) {
-        auto beginGpr = offsetof(FEXCore::Core::CpuStateFrame, State.gregs[0]);
-        auto endGpr = offsetof(FEXCore::Core::CpuStateFrame, State.gregs[16]);
+    const auto GetFPRBeginAndEnd = [this]() -> std::pair<ptrdiff_t, ptrdiff_t> {
+      if (SupportsAVX) {
+        return {
+          offsetof(FEXCore::Core::CpuStateFrame, State.xmm.avx.data[0][0]),
+          offsetof(FEXCore::Core::CpuStateFrame, State.xmm.avx.data[16][0]),
+        };
+      } else {
+        return {
+          offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[0][0]),
+          offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[16][0]),
+        };
+      }
+    };
 
-        auto beginFpr = offsetof(FEXCore::Core::CpuStateFrame, State.xmm[0][0]);
-        auto endFpr = offsetof(FEXCore::Core::CpuStateFrame, State.xmm[16][0]);
+    // Get SRA Reg and Class from a Context offset
+    const auto GetRegAndClassFromOffset = [&, this](uint32_t Offset) {
+        const auto beginGpr = offsetof(FEXCore::Core::CpuStateFrame, State.gregs[0]);
+        const auto endGpr = offsetof(FEXCore::Core::CpuStateFrame, State.gregs[16]);
+
+        const auto [beginFpr, endFpr] = GetFPRBeginAndEnd();
+
+        LOGMAN_THROW_AA_FMT((Offset >= beginGpr && Offset < endGpr) || (Offset >= beginFpr && Offset < endFpr), "Unexpected Offset {}", Offset);
 
         if (Offset >= beginGpr && Offset < endGpr) {
           auto reg = (Offset - beginGpr) / Core::CPUState::GPR_REG_SIZE;
           return PhysicalRegister(GPRFixedClass, reg);
         } else if (Offset >= beginFpr && Offset < endFpr) {
-          auto reg = (Offset - beginFpr) / Core::CPUState::XMM_REG_SIZE;
+          const auto size = SupportsAVX ? Core::CPUState::XMM_AVX_REG_SIZE
+                                        : Core::CPUState::XMM_SSE_REG_SIZE;
+          const auto reg = (Offset - beginFpr) / size;
           return PhysicalRegister(FPRFixedClass, reg);
-        } else {
-          LOGMAN_THROW_A_FMT(false, "Unexpected Offset {}", Offset);
-          return PhysicalRegister::Invalid();
         }
+
+        return PhysicalRegister::Invalid();
     };
 
     auto GprSize = Graph->Set.Classes[GPRFixedClass.Val].PhysicalCount;
@@ -594,34 +609,37 @@ namespace {
 
     // Get a StaticMap entry from context offset
     const auto GetStaticMapFromOffset = [&](uint32_t Offset) -> LiveRange** {
-        auto beginGpr = offsetof(FEXCore::Core::CpuStateFrame, State.gregs[0]);
-        auto endGpr = offsetof(FEXCore::Core::CpuStateFrame, State.gregs[16]);
+        const auto beginGpr = offsetof(FEXCore::Core::CpuStateFrame, State.gregs[0]);
+        const auto endGpr = offsetof(FEXCore::Core::CpuStateFrame, State.gregs[16]);
 
-        auto beginFpr = offsetof(FEXCore::Core::CpuStateFrame, State.xmm[0][0]);
-        auto endFpr = offsetof(FEXCore::Core::CpuStateFrame, State.xmm[16][0]);
+        const auto [beginFpr, endFpr] = GetFPRBeginAndEnd();
+
+        LOGMAN_THROW_AA_FMT((Offset >= beginGpr && Offset < endGpr) || (Offset >= beginFpr && Offset < endFpr), "Unexpected Offset {}", Offset);
 
         if (Offset >= beginGpr && Offset < endGpr) {
           auto reg = (Offset - beginGpr) / Core::CPUState::GPR_REG_SIZE;
           return &StaticMaps[reg];
         } else if (Offset >= beginFpr && Offset < endFpr) {
-          auto reg = (Offset - beginFpr) / Core::CPUState::XMM_REG_SIZE;
+          const auto size = SupportsAVX ? Core::CPUState::XMM_AVX_REG_SIZE
+                                        : Core::CPUState::XMM_SSE_REG_SIZE;
+          const auto reg = (Offset - beginFpr) / size;
           return &StaticMaps[GprSize + reg];
-        } else {
-          LOGMAN_THROW_A_FMT(false, "Unexpected offset {}", Offset);
-          return nullptr;
         }
+
+        return nullptr;
     };
 
     // Get a StaticMap entry from reg and class
     const auto GetStaticMapFromReg = [&](IR::PhysicalRegister PhyReg) -> LiveRange** {
+      LOGMAN_THROW_A_FMT(PhyReg.Class == GPRFixedClass.Val || PhyReg.Class == FPRFixedClass.Val, "Unexpected Class {}", PhyReg.Class);
+
       if (PhyReg.Class == GPRFixedClass.Val) {
         return &StaticMaps[PhyReg.Reg];
       } else if (PhyReg.Class == FPRFixedClass.Val) {
         return &StaticMaps[GprSize + PhyReg.Reg];
-      } else {
-        LOGMAN_THROW_A_FMT(false, "Unexpected Class {}", PhyReg.Class);
-        return nullptr;
       }
+
+      return nullptr;
     };
 
     // First pass: Mark pre-writes
@@ -778,7 +796,7 @@ namespace {
 
     for (auto [BlockNode, BlockHeader] : IR->GetBlocks()) {
       auto BlockIROp = BlockHeader->CW<FEXCore::IR::IROp_CodeBlock>();
-      LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
+      LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
 
       const auto BlockNodeID = IR->GetID(BlockNode);
       const auto BlockBeginID = BlockIROp->Begin.ID();
@@ -888,7 +906,7 @@ namespace {
     };
 
     // SpanStart/SpanEnd assume SSA id will fit in 24bits
-    LOGMAN_THROW_A_FMT(NodeCount <= 0xff'ffff, "Block too large for Spans");
+    LOGMAN_THROW_AA_FMT(NodeCount <= 0xff'ffff, "Block too large for Spans");
 
     SpanStart.resize(NodeCount);
     SpanEnd.resize(NodeCount);
@@ -924,7 +942,7 @@ namespace {
       });
     }
 
-    LOGMAN_THROW_A_FMT(Active.Items[0] == 0, "Interference bug");
+    LOGMAN_THROW_AA_FMT(Active.Items[0] == 0, "Interference bug");
     SpanStart.clear();
     SpanEnd.clear();
   }
@@ -1350,7 +1368,7 @@ namespace {
     auto LastCursor = IREmit->GetWriteCursor();
     auto [CodeNode, IROp] = IR.at(SpillPointId)();
 
-    LOGMAN_THROW_A_FMT(IROp->HasDest, "Can't spill with no dest");
+    LOGMAN_THROW_AA_FMT(IROp->HasDest, "Can't spill with no dest");
 
     const auto Node = IR.GetID(CodeNode);
     RegisterNode *CurrentNode = &Graph->Nodes[Node.Value];
@@ -1539,7 +1557,7 @@ namespace {
     return Changed;
   }
 
-  std::unique_ptr<FEXCore::IR::RegisterAllocationPass> CreateRegisterAllocationPass(FEXCore::IR::Pass* CompactionPass, bool OptimizeSRA) {
-    return std::make_unique<ConstrainedRAPass>(CompactionPass, OptimizeSRA);
+  std::unique_ptr<FEXCore::IR::RegisterAllocationPass> CreateRegisterAllocationPass(FEXCore::IR::Pass* CompactionPass, bool OptimizeSRA, bool SupportsAVX) {
+    return std::make_unique<ConstrainedRAPass>(CompactionPass, OptimizeSRA, SupportsAVX);
   }
 }

External/FEXCore/Source/Interface/IR/Passes/StaticRegisterAllocationPass.cpp

@@ -20,38 +20,57 @@ namespace FEXCore::IR {
 
 class StaticRegisterAllocationPass final : public FEXCore::IR::Pass {
 public:
+  explicit StaticRegisterAllocationPass(bool SupportsAVX_) : SupportsAVX{SupportsAVX_} {}
+
   bool Run(IREmitter *IREmit) override;
+
+private:
+  bool SupportsAVX;
+
+  bool IsStaticAllocGpr(uint32_t Offset, RegisterClassType Class) const {
+    const auto begin = offsetof(Core::CPUState, gregs[0]);
+    const auto end = offsetof(Core::CPUState, gregs[16]);
+
+    if (Offset >= begin && Offset < end) {
+      const auto reg = (Offset - begin) / Core::CPUState::GPR_REG_SIZE;
+      LOGMAN_THROW_AA_FMT(Class.Val == IR::GPRClass.Val, "unexpected Class {}", Class);
+
+      // 0..15 -> 16 in total
+      return reg < Core::CPUState::NUM_GPRS;
+    }
+
+    return false;
+  }
+
+  bool IsStaticAllocFpr(uint32_t Offset, RegisterClassType Class, bool AllowGpr) const {
+    const auto [begin, end] = [this]() -> std::pair<ptrdiff_t, ptrdiff_t> {
+      if (SupportsAVX) {
+        return {
+          offsetof(Core::CPUState, xmm.avx.data[0][0]),
+          offsetof(Core::CPUState, xmm.avx.data[16][0]),
+        };
+      } else {
+        return {
+          offsetof(Core::CPUState, xmm.sse.data[0][0]),
+          offsetof(Core::CPUState, xmm.sse.data[16][0]),
+        };
+      }
+    }();
+
+    if (Offset >= begin && Offset < end) {
+      const auto size = SupportsAVX ? Core::CPUState::XMM_AVX_REG_SIZE
+                                    : Core::CPUState::XMM_SSE_REG_SIZE;
+      const auto reg = (Offset - begin) / size;
+      LOGMAN_THROW_AA_FMT(Class.Val == IR::FPRClass.Val || (AllowGpr && Class.Val == IR::GPRClass.Val), "unexpected Class {}, AllowGpr {}", Class, AllowGpr);
+
+      // 0..15 -> 16 in total
+      return reg < Core::CPUState::NUM_XMMS;
+    }
+
+    return false;
+  }
 };
 
-bool IsStaticAllocGpr(uint32_t Offset, RegisterClassType Class) {
-  const auto begin = offsetof(Core::CPUState, gregs[0]);
-  const auto end = offsetof(Core::CPUState, gregs[16]);
-
-  if (Offset >= begin && Offset < end) {
-    const auto reg = (Offset - begin) / Core::CPUState::GPR_REG_SIZE;
-    LOGMAN_THROW_A_FMT(Class == IR::GPRClass, "unexpected Class {}", Class);
-
-    // 0..15 -> 16 in total
-    return reg < Core::CPUState::NUM_GPRS;
-  }
-
-  return false;
-}
-
-bool IsStaticAllocFpr(uint32_t Offset, RegisterClassType Class, bool AllowGpr) {
-  const auto begin = offsetof(FEXCore::Core::CPUState, xmm[0][0]);
-  const auto end = offsetof(FEXCore::Core::CPUState, xmm[16][0]);
-
-  if (Offset >= begin && Offset < end) {
-    const auto reg = (Offset - begin) / Core::CPUState::XMM_REG_SIZE;
-    LOGMAN_THROW_A_FMT(Class == IR::FPRClass || (AllowGpr && Class == IR::GPRClass), "unexpected Class {}, AllowGpr {}", Class, AllowGpr);
-
-    // 0..15 -> 16 in total
-    return reg < Core::CPUState::NUM_XMMS;
-  }
-
-  return false;
-}
 /**
  * @brief This pass replaces Load/Store Context with Load/Store Register for Statically Mapped registers. It also does some validation.
  *
@@ -102,8 +121,8 @@ bool StaticRegisterAllocationPass::Run(IREmitter *IREmit) {
   return true;
 }
 
-std::unique_ptr<FEXCore::IR::Pass> CreateStaticRegisterAllocationPass() {
-  return std::make_unique<StaticRegisterAllocationPass>();
+std::unique_ptr<FEXCore::IR::Pass> CreateStaticRegisterAllocationPass(bool SupportsAVX) {
+  return std::make_unique<StaticRegisterAllocationPass>(SupportsAVX);
 }
 
 }

External/FEXCore/Source/Utils/Allocator.cpp

@@ -6,6 +6,10 @@
 #include <FEXHeaderUtils/TypeDefines.h>
 
 #include <array>
+#include <asm-generic/errno-base.h>
+#include <cctype>
+#include <cstdio>
+#include <fcntl.h>
 #include <sys/mman.h>
 #include <sys/user.h>
 #ifdef ENABLE_JEMALLOC
@@ -131,91 +135,119 @@ namespace FEXCore::Allocator {
     FEX_UNREACHABLE;
   }
 
-  PtrCache* StealMemoryRegion(uintptr_t Begin, uintptr_t End) {
-    PtrCache *Cache{};
-    uint64_t CacheSize{};
-    uint64_t CurrentCacheOffset = 0;
-    constexpr std::array<size_t, 10> ReservedVMARegionSizes = {{
-      // Anything larger than 64GB fails out
-      64ULL * 1024 * 1024 * 1024,   // 64GB
-      32ULL * 1024 * 1024 * 1024,   // 32GB
-      16ULL * 1024 * 1024 * 1024,   // 16GB
-      4ULL * 1024 * 1024 * 1024,    // 4GB
-      1ULL * 1024 * 1024 * 1024, // 1GB
-      512ULL * 1024 * 1024,      // 512MB
-      128ULL * 1024 * 1024,      // 128MB
-      32ULL * 1024 * 1024,       // 32MB
-      1ULL * 1024 * 1024,        // 1MB
-      4096ULL                    // One page
-    }};
-    constexpr size_t AllocationSizeMaxIndex = ReservedVMARegionSizes.size() - 1;
-    uint64_t CurrentSizeIndex = 0;
+  #define STEAL_LOG(...) // fprintf(stderr, __VA_ARGS__)
 
-    int PROT_FLAGS = PROT_READ | PROT_WRITE;
-    for (size_t MemoryOffset = Begin; MemoryOffset < End;) {
-      size_t AllocationSize = ReservedVMARegionSizes[CurrentSizeIndex];
-      size_t MemoryOffsetUpper = MemoryOffset + AllocationSize;
+  std::vector<MemoryRegion> StealMemoryRegion(uintptr_t Begin, uintptr_t End) {
+    std::vector<MemoryRegion> Regions;
+    
+    int MapsFD = open("/proc/self/maps", O_RDONLY);
+    LogMan::Throw::AFmt(MapsFD != -1, "Failed to open /proc/self/maps");
 
-      // If we would go above the upper bound on size then try the next size
-      if (MemoryOffsetUpper > End) {
-        ++CurrentSizeIndex;
-        continue;
+    enum {ParseBegin, ParseEnd, ScanEnd} State = ParseBegin;
+
+    uintptr_t RegionBegin = 0;
+    uintptr_t RegionEnd = 0;
+
+    char Buffer[2048];
+    const char *Cursor;
+    ssize_t Remaining = 0;
+
+    for(;;) {
+
+      if (Remaining == 0) {
+        do { 
+          Remaining = read(MapsFD, Buffer, sizeof(Buffer));
+        } while ( Remaining == -1 && errno == EAGAIN);
+
+        Cursor = Buffer;
       }
 
-      void *Ptr = ::mmap(reinterpret_cast<void*>(MemoryOffset), AllocationSize, PROT_FLAGS, MAP_PRIVATE | MAP_ANONYMOUS | MAP_NORESERVE | MAP_FIXED_NOREPLACE, -1, 0);
+      if (Remaining == 0 && State == ParseBegin) {
+        STEAL_LOG("[%d] EndOfFile; RegionBegin: %016lX RegionEnd: %016lX\n", __LINE__, RegionBegin, RegionEnd);
 
-      // If we managed to allocate and not get the address we want then unmap it
-      // This happens with kernels older than 4.17
-      if (reinterpret_cast<uintptr_t>(Ptr) + AllocationSize > End) {
-        ::munmap(Ptr, AllocationSize);
-        Ptr = reinterpret_cast<void*>(~0ULL);
-      }
+        auto MapBegin = std::max(RegionEnd, Begin);
+        auto MapEnd = End;
 
-      // If we failed to allocate and we are on the smallest allocation size then just continue onward
-      // This page was unmappable
-      if (reinterpret_cast<uintptr_t>(Ptr) == ~0ULL && CurrentSizeIndex == AllocationSizeMaxIndex) {
-        CurrentSizeIndex = 0;
-        MemoryOffset += AllocationSize;
-        continue;
-      }
+        STEAL_LOG("     MapBegin: %016lX MapEnd: %016lX\n", MapBegin, MapEnd);
 
-      // Congratulations we were able to map this bit
-      // Reset and claim it was available
-      if (reinterpret_cast<uintptr_t>(Ptr) != ~0ULL) {
-        if (!Cache) {
-          Cache = reinterpret_cast<PtrCache *>(Ptr);
-          CacheSize = AllocationSize;
-          PROT_FLAGS = PROT_NONE;
-        }
-        else {
-          Cache[CurrentCacheOffset] = {
-            .Ptr = static_cast<uint64_t>(reinterpret_cast<uint64_t>(Ptr)),
-            .Size = static_cast<uint64_t>(AllocationSize)
-          };
-          ++CurrentCacheOffset;
+        if (MapEnd > MapBegin) {
+          STEAL_LOG("     Reserving\n");
+
+          auto MapSize = MapEnd - MapBegin;
+          auto Alloc = mmap((void*)MapBegin, MapSize, PROT_NONE, MAP_ANONYMOUS | MAP_NORESERVE | MAP_PRIVATE | MAP_FIXED_NOREPLACE, -1, 0);
+
+          LogMan::Throw::AFmt(Alloc != MAP_FAILED, "mmap({:x},{:x}) failed", MapBegin, MapSize);
+          LogMan::Throw::AFmt(Alloc == (void*)MapBegin, "mmap({},{:x}) returned {} instead of {:x}", Alloc, MapBegin);
+
+          Regions.push_back({(void*)MapBegin, MapSize});
         }
 
-        CurrentSizeIndex = 0;
-        MemoryOffset += AllocationSize;
+        close(MapsFD);
+        return Regions;
+      }
+
+      LogMan::Throw::AFmt(Remaining > 0, "Failed to parse /proc/self/maps");
+
+      auto c = *Cursor++;
+      Remaining--;
+
+      if (State == ScanEnd) {
+        if (c == '\n') {
+          State = ParseBegin;
+        }
         continue;
       }
 
-      // Couldn't allocate at this size
-      // Increase and continue
-      ++CurrentSizeIndex;
+      if (State == ParseBegin) {
+        if (c == '-') {
+          STEAL_LOG("[%d] ParseBegin; RegionBegin: %016lX RegionEnd: %016lX\n", __LINE__, RegionBegin, RegionEnd);
+
+          auto MapBegin = std::max(RegionEnd, Begin);
+          auto MapEnd = std::min(RegionBegin, End);
+          
+          STEAL_LOG("     MapBegin: %016lX MapEnd: %016lX\n", MapBegin, MapEnd);
+
+          if (MapEnd > MapBegin) {
+            STEAL_LOG("     Reserving\n");
+
+            auto MapSize = MapEnd - MapBegin;
+            auto Alloc = mmap((void*)MapBegin, MapSize, PROT_NONE, MAP_ANONYMOUS | MAP_NORESERVE | MAP_PRIVATE | MAP_FIXED_NOREPLACE, -1, 0);
+
+            LogMan::Throw::AFmt(Alloc != MAP_FAILED, "mmap({:x},{:x}) failed", MapBegin, MapSize);
+            LogMan::Throw::AFmt(Alloc == (void*)MapBegin, "mmap({},{:x}) returned {} instead of {:x}", Alloc, MapBegin);
+
+            Regions.push_back({(void*)MapBegin, MapSize});
+          }
+          RegionBegin = 0;
+          RegionEnd = 0;
+          State = ParseEnd;
+          continue;
+        } else {
+          LogMan::Throw::AFmt(std::isalpha(c) || std::isdigit(c), "Unexpected char '{}' in ParseBegin", c);
+          RegionBegin = (RegionBegin << 4) | (c <= '9' ? (c - '0') : (c - 'a' + 10));
+        }
+      }
+
+      if (State == ParseEnd) {
+        if (c == ' ') {
+          STEAL_LOG("[%d] ParseEnd; RegionBegin: %016lX RegionEnd: %016lX\n", __LINE__, RegionBegin, RegionEnd);
+
+          State = ScanEnd;
+          continue;
+        } else {
+          LogMan::Throw::AFmt(std::isalpha(c) || std::isdigit(c), "Unexpected char '{}' in ParseEnd", c);
+          RegionEnd = (RegionEnd << 4) | (c <= '9' ? (c - '0') : (c - 'a' + 10));
+        }
+      }
     }
 
-    Cache[CurrentCacheOffset] = {
-      .Ptr = static_cast<uint64_t>(reinterpret_cast<uint64_t>(Cache)),
-      .Size = CacheSize,
-    };
-    return Cache;
+    ERROR_AND_DIE_FMT("unreachable");
   }
 
-  PtrCache* Steal48BitVA() {
+  std::vector<MemoryRegion> Steal48BitVA() {
     size_t Bits = FEXCore::Allocator::DetermineVASize();
     if (Bits < 48) {
-      return nullptr;
+      return {};
     }
 
     uintptr_t Begin48BitVA = 0x0'8000'0000'0000ULL;
@@ -223,18 +255,9 @@ namespace FEXCore::Allocator {
     return StealMemoryRegion(Begin48BitVA, End48BitVA);
   }
 
-  void ReclaimMemoryRegion(PtrCache* Regions) {
-    if (Regions == nullptr) {
-      return;
-    }
-
-    for (size_t i = 0;; ++i) {
-      void *Ptr = reinterpret_cast<void*>(Regions[i].Ptr);
-      size_t Size = Regions[i].Size;
-      ::munmap(Ptr, Size);
-      if (Ptr == Regions) {
-        break;
-      }
+  void ReclaimMemoryRegion(const std::vector<MemoryRegion> &Regions) {
+    for (const auto &Region: Regions) {
+      ::munmap(Region.Ptr, Region.Size);
     }
   }
 }

External/FEXCore/Source/Utils/Allocator/64BitAllocator.cpp

@@ -70,7 +70,10 @@ namespace Alloc::OSAllocator {
         ReservedVMARegion *SlabInfo;
         uint64_t FreeSpace{};
         uint32_t LastPageAllocation{};
-        FEXCore::FlexBitSet<uint64_t> UsedPages;
+
+        // Align UsedPages so it pads to the next page.
+        // Necessary to take advantage of madvise zero page pooling.
+        alignas(4096) FEXCore::FlexBitSet<uint64_t> UsedPages;
 
         // This returns the size of the LiveVMARegion in addition to the flex set that tracks the used data
         // The LiveVMARegion lives at the start of the VMA region which means on initialization we need to set that
@@ -93,16 +96,23 @@ namespace Alloc::OSAllocator {
           Region->FreeSpace = Region->SlabInfo->RegionSize - SizePlusManagedData;
 
           size_t NumPages = SizePlusManagedData >> FHU::FEX_PAGE_SHIFT;
-          // Memset the full tracking to zero to state nothing used
-          Region->UsedPages.MemSet(Region->SlabInfo->RegionSize >> FHU::FEX_PAGE_SHIFT);
+
+          // Use madvise to set the full tracking region to zero.
+          // This ensures unused pages are zero, while not having the backing pages consuming memory.
+          ::madvise(Region->UsedPages.Memory + (NumPages * 4096), (Region->SlabInfo->RegionSize >> FHU::FEX_PAGE_SHIFT) - (NumPages * 4096), MADV_DONTNEED);
+
+          // Use madvise to claim WILLNEED on the beginning pages for initial state tracking.
+          // Improves performance of the following MemClear by not doing a page level fault dance for data necessary to track >170TB of used pages.
+          ::madvise(Region->UsedPages.Memory, NumPages * 4096, MADV_WILLNEED);
+
           // Set our reserved pages
-          for (size_t i = 0; i < NumPages; ++i) {
-            // Set our used pages
-            Region->UsedPages.Set(i);
-          }
+          Region->UsedPages.MemSet(NumPages);
           Region->LastPageAllocation = NumPages;
         }
       };
+
+      static_assert(sizeof(LiveVMARegion) == 4096, "Needs to be the size of a page");
+
       static_assert(std::is_trivially_copyable<LiveVMARegion>::value, "Needs to be trivially copyable");
       static_assert(offsetof(LiveVMARegion, UsedPages) == sizeof(LiveVMARegion), "FlexBitSet needs to be at the end");
 
@@ -125,29 +135,35 @@ namespace Alloc::OSAllocator {
 
         [[maybe_unused]] auto Res = mprotect(reinterpret_cast<void*>(ReservedRegion->Base), SizePlusManagedData, PROT_READ | PROT_WRITE);
 
-        LOGMAN_THROW_A_FMT(Res == 0, "Couldn't mprotect region: {} '{}' Likely occurs when running out of memory or Maximum VMAs", errno, strerror(errno));
+        LOGMAN_THROW_AA_FMT(Res == 0, "Couldn't mprotect region: {} '{}' Likely occurs when running out of memory or Maximum VMAs", errno, strerror(errno));
 
         LiveVMARegion *LiveRange = new (reinterpret_cast<void*>(ReservedRegion->Base)) LiveVMARegion();
 
         // Copy over the reserved data
         LiveRange->SlabInfo = ReservedRegion;
+
         // Initialize VMA
         LiveVMARegion::InitializeVMARegionUsed(LiveRange, UsedSize);
 
         // Add to our active tracked ranges
         auto LiveIter = LiveRegions->emplace_back(LiveRange);
-
         return LiveIter;
       }
 
       // 32-bit old kernel workarounds
-      FEXCore::Allocator::PtrCache *Steal32BitIfOldKernel();
+      std::vector<FEXCore::Allocator::MemoryRegion> Steal32BitIfOldKernel();
   };
 
 void OSAllocator_64Bit::DetermineVASize() {
   size_t Bits = FEXCore::Allocator::DetermineVASize();
   uintptr_t Size = 1ULL << Bits;
+
   UPPER_BOUND = Size;
+
+  #if _M_X86_64 // Last page cannot be allocated on x86
+    UPPER_BOUND -= FHU::FEX_PAGE_SIZE;
+  #endif
+
   UPPER_BOUND_PAGE = UPPER_BOUND / FHU::FEX_PAGE_SIZE;
 }
 
@@ -490,11 +506,11 @@ int OSAllocator_64Bit::Munmap(void *addr, size_t length) {
   return 0;
 }
 
-FEXCore::Allocator::PtrCache *OSAllocator_64Bit::Steal32BitIfOldKernel() {
+std::vector<FEXCore::Allocator::MemoryRegion> OSAllocator_64Bit::Steal32BitIfOldKernel() {
   // First calculate kernel version
   struct utsname buf{};
   if (uname(&buf) == -1) {
-    return nullptr;
+    return {};
   }
 
   int32_t Major{};
@@ -512,7 +528,7 @@ FEXCore::Allocator::PtrCache *OSAllocator_64Bit::Steal32BitIfOldKernel() {
 
   if (Version >= ((4 << 24) | (17 << 16) | 0)) {
     // If the kernel is >= 4.17 then it supports MAP_FIXED_NOREPLACE
-    return nullptr;
+    return {};
   }
 
   constexpr size_t LOWER_BOUND_32 = 0x1'0000;
@@ -523,101 +539,39 @@ FEXCore::Allocator::PtrCache *OSAllocator_64Bit::Steal32BitIfOldKernel() {
 
 OSAllocator_64Bit::OSAllocator_64Bit() {
   DetermineVASize();
-  auto ArrayPtr = Steal32BitIfOldKernel();
+  auto LowMem = Steal32BitIfOldKernel();
 
-  // On allocation try and steal the entire upper 64bits of address space for mapping
-  constexpr std::array<size_t, 8> ReservedVMARegionSizes = {{
-    // Anything larger than 64GB fails out
-    64ULL * 1024 * 1024 * 1024,   // 64GB
-    32ULL * 1024 * 1024 * 1024,   // 32GB
-    16ULL * 1024 * 1024 * 1024,   // 16GB
-    4ULL * 1024 * 1024 * 1024,    // 4GB
-    1ULL * 1024 * 1024 * 1024,    // 1GB
-    512ULL * 1024 * 1024,         // 512MB
-    128ULL * 1024 * 1024,         // 128MB
-    4096ULL                       // One page
-  }};
+  auto Ranges = FEXCore::Allocator::StealMemoryRegion(LOWER_BOUND, UPPER_BOUND);
 
-  constexpr size_t AllocationSizeMaxIndex = ReservedVMARegionSizes.size() - 1;
+  for (auto [Ptr, AllocationSize]: Ranges) {
+    if (!ObjectAlloc) {
+      auto MaxSize = std::min(size_t(64) * 1024 * 1024, AllocationSize);
 
-  // Have the first region only be 4GB VMA
-  // Avoids conflicts with some tests
-  uint64_t CurrentSizeIndex = 3;
-  ReservedVMARegion *PrevReserved{};
-  for (size_t MemoryOffset = LOWER_BOUND; MemoryOffset < UPPER_BOUND;) {
-    size_t AllocationSize = ReservedVMARegionSizes[CurrentSizeIndex];
-    size_t MemoryOffsetUpper = MemoryOffset + AllocationSize;
+      // Allocate up to 64 MiB the first allocation for an intrusive allocator
+      mprotect(Ptr, MaxSize, PROT_READ | PROT_WRITE);
 
-    // If we would go above the upper bound on size then try the next size
-    if (MemoryOffsetUpper > UPPER_BOUND) {
-      ++CurrentSizeIndex;
-      continue;
-    }
+      // This enables the kernel to use transparent large pages in the allocator which can reduce memory pressure
+      ::madvise(Ptr, MaxSize, MADV_HUGEPAGE);
 
-    void *Ptr = ::mmap(reinterpret_cast<void*>(MemoryOffset), AllocationSize, PROT_NONE, MAP_FIXED_NOREPLACE | MAP_PRIVATE | MAP_ANONYMOUS | MAP_NORESERVE, -1, 0);
+      ObjectAlloc = new (Ptr) Alloc::ForwardOnlyIntrusiveArenaAllocator(Ptr, MaxSize);
+      ReservedRegions = ObjectAlloc->new_construct(ReservedRegions, ObjectAlloc);
+      LiveRegions = ObjectAlloc->new_construct(LiveRegions, ObjectAlloc);
 
-    // If we managed to allocate and not get the address we want then unmap it
-    // This happens with kernels older than 4.17
-    if (reinterpret_cast<uintptr_t>(Ptr) != MemoryOffset &&
-        reinterpret_cast<uintptr_t>(Ptr) < LOWER_BOUND) {
-      ::munmap(Ptr, AllocationSize);
-      Ptr = reinterpret_cast<void*>(~0ULL);
-    }
-
-    // If we failed to allocate and we are on the smallest allocation size then just continue onward
-    // This page was unmappable
-    if (reinterpret_cast<uintptr_t>(Ptr) == ~0ULL && CurrentSizeIndex == AllocationSizeMaxIndex) {
-      CurrentSizeIndex = 0;
-      MemoryOffset += AllocationSize;
-      continue;
-    }
-
-    // Congratulations we were able to map this bit
-    // Reset and claim it was available
-    if (reinterpret_cast<uintptr_t>(Ptr) != ~0ULL) {
-      if (!ObjectAlloc) {
-        // Steal the first allocation for an intrusive allocator
-        // Will be mprotected correctly already
-        mprotect(Ptr, AllocationSize, PROT_READ | PROT_WRITE);
-        ObjectAlloc = new (Ptr) Alloc::ForwardOnlyIntrusiveArenaAllocator(Ptr, AllocationSize);
-        ReservedRegions = ObjectAlloc->new_construct(ReservedRegions, ObjectAlloc);
-        LiveRegions = ObjectAlloc->new_construct(LiveRegions, ObjectAlloc);
+      if (AllocationSize > MaxSize) {
+        AllocationSize -= MaxSize;
+        (uint8_t*&)Ptr += MaxSize;
+      } else {
+        continue;
       }
-      else {
-
-        // If the allocation size is large than a page, then try allowing it to be a huge page
-        // This enables the kernel to use transparent large pages in the allocator which can reduce memory pressure
-        // Considering we are allocating the entire VA space, this is a good thing
-        // If MADV_HUGEPAGE isn't support then this will fail harmlessly
-        if (AllocationSize > 4096) {
-          ::madvise(Ptr, AllocationSize, MADV_HUGEPAGE);
-        }
-
-        bool Merged = false;
-        if (PrevReserved) {
-          Merged = MergeReservedRegionIfPossible(PrevReserved, reinterpret_cast<uint64_t>(Ptr), AllocationSize);
-        }
-
-        if (!Merged) {
-          ReservedVMARegion *Region = ObjectAlloc->new_construct<ReservedVMARegion>();
-          Region->Base = reinterpret_cast<uint64_t>(Ptr);
-          Region->RegionSize = AllocationSize;
-          ReservedRegions->emplace_back(Region);
-          PrevReserved = Region;
-        }
-      }
-
-      CurrentSizeIndex = 0;
-      MemoryOffset += AllocationSize;
-      continue;
     }
-
-    // Couldn't allocate at this size
-    // Increase and continue
-    ++CurrentSizeIndex;
+    
+    ReservedVMARegion *Region = ObjectAlloc->new_construct<ReservedVMARegion>();
+    Region->Base = reinterpret_cast<uint64_t>(Ptr);
+    Region->RegionSize = AllocationSize;
+    ReservedRegions->emplace_back(Region);
   }
 
-  FEXCore::Allocator::ReclaimMemoryRegion(ArrayPtr);
+  FEXCore::Allocator::ReclaimMemoryRegion(LowMem);
 }
 
 OSAllocator_64Bit::~OSAllocator_64Bit() {

External/FEXCore/Source/Utils/MemberFunctionToPointer.h

@@ -21,12 +21,12 @@ class MemberFunctionToPointerCast final {
       // Itanium C++ ABI (https://itanium-cxx-abi.github.io/cxx-abi/abi.html#member-function-pointers)
       // Low bit of ptr specifies if this Member function pointer is virtual or not
       // Throw an assert if we were trying to cast a virtual member
-      LOGMAN_THROW_A_FMT((PMF.ptr & 1) == 0, "C++ Pointer-To-Member representation didn't have low bit set to 0. Are you trying to cast a virtual member?");
+      LOGMAN_THROW_AA_FMT((PMF.ptr & 1) == 0, "C++ Pointer-To-Member representation didn't have low bit set to 0. Are you trying to cast a virtual member?");
 #elif defined(_M_ARM_64 )
       // C++ ABI for the Arm 64-bit Architecture (IHI 0059E)
       // 4.2.1 Representation of pointer to member function
       // Differs from Itanium specification
-      LOGMAN_THROW_A_FMT(PMF.adj == 0, "C++ Pointer-To-Member representation didn't have adj == 0. Are you trying to cast a virtual member?");
+      LOGMAN_THROW_AA_FMT(PMF.adj == 0, "C++ Pointer-To-Member representation didn't have adj == 0. Are you trying to cast a virtual member?");
 #else
 #error Don't know how to cast Member to function here. Likely just Itanium
 #endif

External/FEXCore/Source/Utils/Telemetry.cpp

@@ -35,9 +35,9 @@ namespace FEXCore::Telemetry {
     }
   }
 
-  void Shutdown(std::filesystem::path &ApplicationName) {
+  void Shutdown(std::string const &ApplicationName) {
     auto DataDirectory = Config::GetDataDirectory();
-    DataDirectory += "Telemetry/" + ApplicationName.string() + ".telem";
+    DataDirectory += "Telemetry/" + ApplicationName + ".telem";
 
     std::error_code ec{};
     if (std::filesystem::exists(DataDirectory, ec)) {

External/FEXCore/include/FEXCore/Config/Config.h

@@ -71,6 +71,7 @@ namespace Handler {
   };
 
   enum class LayerType {
+    LAYER_GLOBAL_MAIN, ///< /usr/share/fex-emu/Config.json by default
     LAYER_MAIN,
     LAYER_ARGUMENTS,
     LAYER_GLOBAL_APP,
@@ -100,7 +101,7 @@ namespace Type {
 
   FEX_DEFAULT_VISIBILITY std::string GetDataDirectory();
   FEX_DEFAULT_VISIBILITY std::string GetConfigDirectory(bool Global);
-  FEX_DEFAULT_VISIBILITY std::string GetConfigFileLocation();
+  FEX_DEFAULT_VISIBILITY std::string GetConfigFileLocation(bool Global = false);
   FEX_DEFAULT_VISIBILITY std::string GetApplicationConfig(const std::string &Filename, bool Global);
 
   using LayerValue = std::list<std::string>;
@@ -246,6 +247,13 @@ namespace Type {
     void MapNameToOption(const char *ConfigName, const char *ConfigString);
   };
 
+  /**
+   * @brief Loads the global FEX config
+   *
+   * @return unique_ptr for that layer
+   */
+  FEX_DEFAULT_VISIBILITY std::unique_ptr<FEXCore::Config::Layer> CreateGlobalMainLayer();
+
   /**
    * @brief Loads the main application config
    *

External/FEXCore/include/FEXCore/Core/Context.h

@@ -5,6 +5,7 @@
 
 #include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/Core/CPUID.h>
+#include <FEXCore/IR/IR.h>
 #include <FEXCore/Utils/CompilerDefs.h>
 
 #include <istream>
@@ -16,6 +17,7 @@
 
 namespace FEXCore {
   class CodeLoader;
+  class HostFeatures;
 }
 
 namespace FEXCore::Core {
@@ -239,6 +241,14 @@ namespace FEXCore::Context {
    */
   FEX_DEFAULT_VISIBILITY void RegisterExternalSyscallVisitor(FEXCore::Context::Context *CTX, uint64_t Syscall, FEXCore::HLE::SyscallVisitor *Visitor);
 
+  /**
+   * @brief Retrieves a feature struct indicating certain supported aspects from
+   *        the hose.
+   * 
+   * @param CTX A valid non-null context instance.
+   */
+  FEX_DEFAULT_VISIBILITY HostFeatures GetHostFeatures(const FEXCore::Context::Context *CTX);
+
   FEX_DEFAULT_VISIBILITY void HandleCallback(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread, uint64_t RIP);
 
   FEX_DEFAULT_VISIBILITY void RegisterHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func, bool Required);
@@ -271,4 +281,12 @@ namespace FEXCore::Context {
 
   FEX_DEFAULT_VISIBILITY void ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, std::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress);
   FEX_DEFAULT_VISIBILITY CustomIRResult AddCustomIREntrypoint(FEXCore::Context::Context *CTX, uintptr_t Entrypoint, std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)> Handler, void *Creator = nullptr, void *Data = nullptr);
+
+  /**
+   * @brief Allows the frontend to register its own thunk handlers independent of what is controlled in the backend.
+   *
+   * @param CTX A valid non-null context instance.
+   * @param Definitions A vector of thunk definitions that the frontend controls
+   */
+  FEX_DEFAULT_VISIBILITY void AppendThunkDefinitions(FEXCore::Context::Context *CTX, std::vector<FEXCore::IR::ThunkDefinition> const& Definitions);
 }

External/FEXCore/include/FEXCore/Core/CoreState.h

@@ -11,15 +11,28 @@
 
 namespace FEXCore::Core {
   struct FEX_PACKED CPUState {
+    // Allows more efficient handling of the register
+    // file in the event AVX is not supported.
+    union XMMRegs {
+      struct AVX {
+        uint64_t data[16][4];
+      };
+      struct SSE {
+        uint64_t data[16][2];
+        uint64_t pad[16][2];
+      };
+
+      AVX avx;
+      SSE sse;
+    };
+
     uint64_t rip; ///< Current core's RIP. May not be entirely accurate while JIT is active
     uint64_t gregs[16];
-    uint64_t : 64;
-    uint64_t xmm[16][2];
     uint16_t es, cs, ss, ds;
     uint64_t gs;
     uint64_t fs;
+    XMMRegs xmm;
     uint8_t flags[48];
-    uint64_t : 64; // Ensures mm is aligned
     uint64_t mm[8][2];
 
     // 32bit x86 state
@@ -32,7 +45,8 @@ namespace FEXCore::Core {
     static constexpr size_t FLAG_SIZE = sizeof(flags[0]);
     static constexpr size_t GDT_SIZE = sizeof(gdt[0]);
     static constexpr size_t GPR_REG_SIZE = sizeof(gregs[0]);
-    static constexpr size_t XMM_REG_SIZE = sizeof(xmm[0]);
+    static constexpr size_t XMM_AVX_REG_SIZE = sizeof(xmm.avx.data[0]);
+    static constexpr size_t XMM_SSE_REG_SIZE = XMM_AVX_REG_SIZE / 2;
     static constexpr size_t MM_REG_SIZE = sizeof(mm[0]);
 
     // Only the first 32 bits are defined.
@@ -40,10 +54,11 @@ namespace FEXCore::Core {
     static constexpr size_t NUM_FLAGS = sizeof(flags) / FLAG_SIZE;
     static constexpr size_t NUM_GDTS = sizeof(gdt) / GDT_SIZE;
     static constexpr size_t NUM_GPRS = sizeof(gregs) / GPR_REG_SIZE;
-    static constexpr size_t NUM_XMMS = sizeof(xmm) / XMM_REG_SIZE;
+    static constexpr size_t NUM_XMMS = sizeof(xmm) / XMM_AVX_REG_SIZE;
     static constexpr size_t NUM_MMS = sizeof(mm) / MM_REG_SIZE;
   };
-  static_assert(offsetof(CPUState, xmm) % 16 == 0, "xmm needs to be 128bit aligned!");
+  static_assert(offsetof(CPUState, xmm) % 32 == 0, "xmm needs to be 256-bit aligned!");
+  static_assert(offsetof(CPUState, mm) % 16 == 0, "mm needs to be 128-bit aligned!");
 
   struct InternalThreadState;
 
@@ -114,7 +129,7 @@ namespace FEXCore::Core {
 
       uint64_t PrintValue{};
       uint64_t PrintVectorValue{};
-      uint64_t RemoveThreadCodeEntryFromJIT{};
+      uint64_t ThreadRemoveCodeEntryFromJIT{};
       uint64_t CPUIDObj{};
       uint64_t CPUIDFunction{};
       uint64_t SyscallHandlerObj{};
@@ -133,7 +148,9 @@ namespace FEXCore::Core {
       uint64_t ThreadStopHandlerSpillSRA{};
       uint64_t ThreadPauseHandlerSpillSRA{};
       uint64_t UnimplementedInstructionHandler{};
-      uint64_t OverflowExceptionHandler{};
+      uint64_t GuestSignal_SIGILL{};
+      uint64_t GuestSignal_SIGTRAP{};
+      uint64_t GuestSignal_SIGSEGV{};
       uint64_t SignalReturnHandler{};
       uint64_t L1Pointer{};
       uint64_t L2Pointer{};
@@ -196,6 +213,7 @@ namespace FEXCore::Core {
 
     struct SynchronousFaultDataStruct {
       bool FaultToTopAndGeneratedException{};
+      uint8_t Signal;
       uint32_t TrapNo;
       uint32_t err_code;
       uint32_t si_code;

External/FEXCore/include/FEXCore/Core/HostFeatures.h

@@ -21,6 +21,12 @@ class HostFeatures final {
     bool SupportsRCPC{};
     bool SupportsTSOImm9{};
     bool SupportsRAND{};
+    bool Supports3DNow{};
+    bool SupportsSSE4A{};
+    bool SupportsAVX{};
+    bool SupportsSHA{};
+    bool SupportsBMI1{};
+    bool SupportsBMI2{};
 
     // Float exception behaviour
     bool SupportsFlushInputsToZero{};

External/FEXCore/include/FEXCore/Core/SignalDelegator.h

@@ -69,6 +69,14 @@ namespace Core {
     // Called from the thunk handler to handle the signal
     void HandleSignal(int Signal, void *Info, void *UContext);
 
+    /**
+     * @brief Check to ensure the XID handler is still set to the FEX handler
+     *
+     * On a new thread GLIBC will set the XID handler underneath us.
+     * After the first thread is created check this.
+     */
+    virtual void CheckXIDHandler() = 0;
+
     constexpr static size_t MAX_SIGNALS {64};
 
     // Use the last signal just so we are less likely to ever conflict with something that the guest application is using

External/FEXCore/include/FEXCore/Core/UContext.h

@@ -27,6 +27,65 @@ namespace FEXCore {
     };
     static_assert(sizeof(FEXCore::x86_64::stack_t) == 24, "This needs to be the right size");
 
+    /**
+     * Describes the software specific bytes added at the end of the
+     * fpstate to identify whether or not an extended context area is
+     * present and what kind of extended features are present in said
+     * context area.
+     */
+    struct FEX_PACKED fpx_sw_bytes {
+      static constexpr uint32_t FP_XSTATE_MAGIC = 0x46505853;
+
+      enum FeatureFlag : uint32_t {
+        FEATURE_FP         = 1U << 0,
+        FEATURE_SSE        = 1U << 1,
+        FEATURE_YMM        = 1U << 2,
+        FEATURE_BNDREGS    = 1U << 3,
+        FEATURE_BNDCSR     = 1U << 4,
+        FEATURE_OPMASK     = 1U << 5,
+        FEATURE_ZMM_Hi256  = 1U << 6,
+        FEATURE_Hi16_ZMM   = 1U << 7,
+        FEATURE_PT_UNIMPL  = 1U << 8,
+        FEATURE_PKRU       = 1U << 9,
+        FEATURE_PASID      = 1U << 10,
+        FEATURE_RESERVED11 = 1U << 11,
+        FEATURE_RESERVED12 = 1U << 12,
+        FEATURE_RESERVED13 = 1U << 13,
+        FEATURE_RESERVED14 = 1U << 14,
+        FEATURE_LBR        = 1U << 15,
+        FEATURE_RESERVED16 = 1U << 16,
+        FEATURE_XTILE_CFG  = 1U << 17,
+        FEATURE_XTILE_DATA = 1U << 18,
+      };
+
+      bool HasExtendedContext() const {
+        return magic1 == FP_XSTATE_MAGIC;
+      }
+
+      bool HasYMMH() const {
+        return (xfeatures & FEATURE_YMM) != 0;
+      }
+
+      // If magic1 is set to FP_XSTATE_MAGIC, then the encompassing
+      // frame is an xstate frame. If 0, then it's a legacy frame.
+      uint32_t magic1;
+
+      // Total size of the fpstate area
+      // - magic1 = 0               -> sizeof(fpstate)
+      // - magic1 = FP_XSTATE_MAGIC -> sizeof(xstate) + extensions (if any)
+      uint32_t extended_size;
+
+      // Feature bitmask describing supported features.
+      uint64_t xfeatures;
+
+      // Actual XSAVE state size, based on above xfeatures
+      uint32_t xstate_size;
+
+      // Reserved data
+      uint32_t padding[7];
+    };
+    static_assert(sizeof(fpx_sw_bytes) == 48);
+
     struct FEX_PACKED _libc_fpstate {
       // This is in FXSAVE format
       uint16_t fcw;
@@ -39,10 +98,37 @@ namespace FEXCore {
       uint32_t mxcsr_mask;
       __uint128_t _st[8];
       __uint128_t _xmm[16];
-      uint32_t _res[24];
+      uint32_t _res[12];
+
+      // Linux uses 12 of the bytes relegated for software purposes
+      // to store info describing any existing XSAVE context data.
+      fpx_sw_bytes sw_reserved;
     };
     static_assert(sizeof(FEXCore::x86_64::_libc_fpstate) == 512, "This needs to be the right size");
 
+    struct FEX_PACKED xstate_header {
+      uint64_t xfeatures;
+      uint64_t reserved1[2];
+      uint64_t reserved2[5];
+    };
+    static_assert(sizeof(xstate_header) == 64);
+
+    struct FEX_PACKED ymmh_state {
+      __uint128_t ymmh_space[16];
+    };
+    static_assert(sizeof(ymmh_state) == 256);
+
+    /**
+     * Extended state that includes both the main fpstate
+     * and the extended state.
+     */
+    struct FEX_PACKED xstate {
+      _libc_fpstate fpstate;
+      xstate_header xstate_hdr;
+      ymmh_state ymmh;
+    };
+    static_assert(sizeof(xstate) == 832);
+
     ///< The order of these must match the GNU ordering
     enum ContextRegs {
       FEX_REG_R8 = 0,
@@ -233,6 +319,11 @@ namespace FEXCore {
     };
     static_assert(sizeof(FEXCore::x86::_libc_fpreg) == 10, "This needs to be the right size");
 
+    // Same layout on both x86 and x86_64
+    using fpx_sw_bytes = x86_64::fpx_sw_bytes;
+    using xstate_header = x86_64::xstate_header;
+    using ymmh_state = x86_64::ymmh_state;
+
     enum fpstate_magic {
       // Legacy fpstate
       MAGIC_FPU = 0xFFFF'0000,
@@ -257,10 +348,21 @@ namespace FEXCore {
       __uint128_t _st_pad[8]; // Ignored st data
       __uint128_t _xmm[8]; // First 8 XMM registers
       uint32_t pad2[44]; // Second 8 XMM registers plus padding
-      uint32_t pad3[12]; // extended state encoding
+      fpx_sw_bytes sw_reserved; // extended state encoding
     };
     static_assert(sizeof(FEXCore::x86::_libc_fpstate) == 624, "This needs to be the right size");
 
+    /**
+     * Extended state that includes both the main fpstate
+     * and the extended state.
+     */
+    struct FEX_PACKED xstate {
+      _libc_fpstate fpstate;
+      xstate_header xstate_hdr;
+      ymmh_state ymmh;
+    };
+    static_assert(sizeof(xstate) == 944);
+
     struct FEX_PACKED ucontext_t {
       uint32_t uc_flags;
       uint32_t uc_link; // XXX: should be a compat_ptr<FEXCore::x86::ucontext_t>