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VectorOps: Handle 256-bit VOr

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lioncash committed 2022-08-24 12:52:05 -04:00
1 parent 4be6626c89
commit afc5e8a140
2 files changed
+16 -2
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External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
Vendored
+10 -1
View File
@@ -154,7 +154,16 @@ DEF_OP(VBic) {
DEF_OP(VOr) {
auto Op = IROp->C<IR::IROp_VOr>();
orr(GetDst(Node).V16B(), GetSrc(Op->Vector1.ID()).V16B(), GetSrc(Op->Vector2.ID()).V16B());
const auto Dst = GetDst(Node);
const auto Vector1 = GetSrc(Op->Vector1.ID());
const auto Vector2 = GetSrc(Op->Vector2.ID());
if (CanUseSVE) {
orr(Dst.Z().VnD(), Vector1.Z().VnD(), Vector2.Z().VnD());
} else {
orr(Dst.V16B(), Vector1.V16B(), Vector2.V16B());
}
}
DEF_OP(VXor) {
External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
Vendored
+6 -1
View File
@@ -157,7 +157,12 @@ DEF_OP(VBic) {
DEF_OP(VOr) {
auto Op = IROp->C<IR::IROp_VOr>();
vpor(GetDst(Node), GetSrc(Op->Vector1.ID()), GetSrc(Op->Vector2.ID()));
const auto Dst = ToYMM(GetDst(Node));
const auto Vector1 = ToYMM(GetSrc(Op->Vector1.ID()));
const auto Vector2 = ToYMM(GetSrc(Op->Vector2.ID()));
vpor(Dst, Vector1, Vector2);
}
DEF_OP(VXor) {