From afc5e8a140916ba80b3d778e55d8a98fee12ef4e Mon Sep 17 00:00:00 2001
From: lioncash <mathew1800@gmail.com>
Date: Tue, 9 Aug 2022 13:14:50 -0400
Subject: [PATCH] VectorOps: Handle 256-bit VOr

---
 .../Source/Interface/Core/JIT/Arm64/VectorOps.cpp     | 11 ++++++++++-
 .../Source/Interface/Core/JIT/x86_64/VectorOps.cpp    |  7 ++++++-
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
index f4c383eb0..82cf18824 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
@@ -154,7 +154,16 @@ DEF_OP(VBic) {
 
 DEF_OP(VOr) {
   auto Op = IROp->C<IR::IROp_VOr>();
-  orr(GetDst(Node).V16B(), GetSrc(Op->Vector1.ID()).V16B(), GetSrc(Op->Vector2.ID()).V16B());
+
+  const auto Dst = GetDst(Node);
+  const auto Vector1 = GetSrc(Op->Vector1.ID());
+  const auto Vector2 = GetSrc(Op->Vector2.ID());
+
+  if (CanUseSVE) {
+    orr(Dst.Z().VnD(), Vector1.Z().VnD(), Vector2.Z().VnD());
+  } else {
+    orr(Dst.V16B(), Vector1.V16B(), Vector2.V16B());
+  }
 }
 
 DEF_OP(VXor) {
diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
index c67058cbe..1817bce0c 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
@@ -157,7 +157,12 @@ DEF_OP(VBic) {
 
 DEF_OP(VOr) {
   auto Op = IROp->C<IR::IROp_VOr>();
-  vpor(GetDst(Node), GetSrc(Op->Vector1.ID()), GetSrc(Op->Vector2.ID()));
+
+  const auto Dst = ToYMM(GetDst(Node));
+  const auto Vector1 = ToYMM(GetSrc(Op->Vector1.ID()));
+  const auto Vector2 = ToYMM(GetSrc(Op->Vector2.ID()));
+
+  vpor(Dst, Vector1, Vector2);
 }
 
 DEF_OP(VXor) {