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Code Issues Packages Projects Releases 67 Wiki Activity
10,388 Commits 11 Branches 71 Tags
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Commit Graph
350 Commits
Author SHA1 Message Date
Alyssa Rosenzweig ce8e6e5c0c OpcodeDispatcher: optimize adc 0 
clang generates this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-22 10:51:06 -04:00
Alyssa Rosenzweig d53e689e22 IR: model tbz/tbnz 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-21 17:52:22 -04:00
Alyssa Rosenzweig d0e040514f IR: add LoadContextPair 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig 850c027d52 IR: add AllocateFPR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig 5df90563e2 IR: add LoadMemPair 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig 7a489d18c6 IR: add StoreMemPair 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig 1db092e96f IR: add StoreContextPair 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig 7de6a5cb07 OpcodeDispatcher: optimize rotate flags 
introduce an IR op for it so we can reason about flags across rotate
instructions easily.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-19 10:40:53 -04:00
Alyssa Rosenzweig e06b3a4186 ConstProp: optimize and x, -1 
mitigates regression from previous patch

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-19 08:54:47 -04:00
Alyssa Rosenzweig 49e4426ed5 RedundantFlagCalculationElimination: drop register writes 
this allows us to form real cmp instructions when we know PF is dead.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-19 08:54:47 -04:00
Alyssa Rosenzweig c4e2436885 ConstProp: optimize add eax, -1 and friends 
need to sign extend to get the constant inlined.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-19 08:54:47 -04:00
Alyssa Rosenzweig 200c6c054f IR: introduce POP operation 
rmw on a source, kind of terrible.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 231c28395c RegisterAllocationPass: clean up after pair removal 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 64a45c0d29 IR: remove pairs 
They're now unused. And won't be missed.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig cab02be637 IR: remove unused pair create/extract 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig 74f341bc0e IR: remove pair from cpuid 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig feaa1af1a8 IR: remove pair from XGetBV 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:37:06 -04:00
Alyssa Rosenzweig d59d040b4e IR: add design doc breadcrumb 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig a9c26cbf71 IR: add coalescing heuristics for pair replacements 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig 13974df204 IR: drop CASPair pair result 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig fa6fe9bf06 IR: drop cmppairz pairs 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig 746be0824e IR: drop CASPair source pairs 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig 93120cabbb IR: drop pair from memcpy 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig 04ae05f4ce IR: add hack for multiple destinations 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig 83773dddc7 IR: fix size for cmppairz 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-14 09:17:23 -04:00
Alyssa Rosenzweig d9c779289c OpcodeDispatcher: simplify RDRAND 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 15:18:00 -04:00
Alyssa Rosenzweig 5631ff4fd5 OpcodeDispatcher: optimize variable shifts 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig 3b8cd44ca4 IR: add NZCVSelectIncrement 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Ryan Houdek 6ff3c90af3 CodeEmitter: Removes vestigial vixl usage 
- IsImmLogical already existed in our CodeEmitter. We just forgot to
  allow nullptr arguments and to use it.
- Adds an equivalent IsImmAddSub helper and uses it

This gets us closer to removing vixl's global initializers from FEXCore.
 2024-08-03 21:04:56 -07:00
Billy Laws f26bb6bf53 x87StackOptimizationPass: Default initialise StackMemberInfo members 
Not doing so is UB.
 2024-07-31 17:30:29 +00:00
Ryan Houdek 3c5b59d985 AVX128: Implement support for scalar FMA with AFP 
Now that I have AFP supporting hardware I felt better implementing this
since I can run unit tests.

Fixes #3793
 2024-07-22 12:58:19 -07:00
Alyssa Rosenzweig 587b924de9 json_ir_generator: stop prefixing arguments 
stop prefixing the arguments when we generate allocate ops (in particular), this
is more convenient and simpler. in exchange we need to prefix Op to avoid a
collision on fcmpscalarinsert which has an argument named Op, but that's a local
change at least.

came up when experimenting with new IR, but I think this is probably a win by
itself.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-07-22 13:50:21 -04:00
Paulo Matos a1378f94ce X87 Code Refactoring and Optimization Pass 2024-07-22 08:44:45 +02:00
Alyssa Rosenzweig 610caf8529 ConstProp: treat StoreContext as zeroable 
todo: FPR equivalent.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-07-21 15:49:09 -04:00
Alyssa Rosenzweig d20b46e46f IR: drop LoadFlag/StoreFlag ops 
pointless, we can just load/store the context now.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-07-21 15:49:09 -04:00
Alyssa Rosenzweig 4094aa1b9a DeadStoreElimination: drop flag handling 
now that we do everything via NZCV, this is mostly vestigial. DF/x87 flags are
sufficiently rare to be "don't care"s here, and we don't even have multiblock
enabled yet!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-07-21 15:49:08 -04:00
Ryan Houdek b78da2e5ad Arm64: Implements support for DAZ using AFP.FIZ 
When AFP is supported then we can actually support DAZ. This might also
fix the audio corruption in Animal Well but I can't test it until Steam
is running on Oryon. Requires a bit of plumbing for MXCSR which we were
hacking around before but now we actually want to store the value.

Fixes #3856
 2024-07-20 15:34:54 -07:00
Alyssa Rosenzweig e7d5a01c5f IR: remove F80Cmp flags 
nothing is optimizing around this, it's just adding pointless complexity. if we
want to actually optimize F80Cmp, the right way would be to lift the
implementation into the OpcodeDispatcher or JIT. it wouldn't be terribly
difficult. This kludge doesn't get us closer there.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-07-16 14:53:58 -04:00
Alyssa Rosenzweig 0c3a8d0bc8 IR: remove GetHostFlag 
it doesn't get host flags, it's just an extra Bfe used in x87. pointless and
confusing!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-07-16 14:44:34 -04:00
Paulo Matos 8d89adef2e Add IR stack operations 
These IR operations deal implicitly with the x87 stack and are removed
by the x87 stack optimization pass.
 2024-07-16 09:07:35 +02:00
Alyssa Rosenzweig 1e709d1150 OpcodeDispatcher: add RecordX87 helper 
calls will be generated.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-07-16 09:07:35 +02:00
Alyssa Rosenzweig 476ee0cd7d IR: track whether x87 is used in header 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-07-16 09:07:35 +02:00
Ryan Houdek d79b7fcc49 Merge pull request #3808 from alyssarosenzweig/rclse/3 
Try to delete RCLSE again
 2024-07-12 20:38:06 -07:00
Alyssa Rosenzweig 3a334c4585 Reapply "IR: drop RCLSE" 
This reverts commit 78aee4d96e.
 2024-07-11 13:21:14 -04:00
Ryan Houdek 4c21aa2604 Arm64: Implement support for NT Loads with ASIMD fallback 2024-07-10 23:06:46 -07:00
Tony Wasserka 56bb3744a5 AOTIR: Change std::unique_ptr to fextl::unique_ptr 2024-07-10 19:34:24 +02:00
Mai af6a0be832 Merge pull request #3842 from Sonicadvance1/fix_f64_to_i32 
VCVT{T,}PD2DQ fixes and optimization
 2024-07-09 03:49:31 -04:00
Ryan Houdek d3d76aa8ce IR: Adds new F64 -> I32 operation that changes behaviour depending on SVE 
SVE added the ability to do F64 -> I32 conversions directly without an
fcvtn inbetween. So maybe sure to support them.
 2024-07-09 00:38:47 -07:00
Ryan Houdek c5a0ae7b34 IR: Adds new QPS gather load variant! 2024-07-08 17:19:18 -07:00
Ryan Houdek c168ee6940 Arm64: Implements VSSHLL{,2} IR ops 2024-07-06 18:32:35 -07:00