steam-frame/FEX-Emu--FEX
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Code Issues Packages Projects Releases 67 Wiki Activity
5,821 Commits 11 Branches 71 Tags
88fee019a1535737dd7aa8b00d4ad2fa413a3c19
Commit Graph
2768 Commits
Author SHA1 Message Date
Lioncache 88fee019a1 OpcodeDispatcher: Handle VPBLENDVB 2023-02-06 23:04:26 -05:00
Lioncache 5d3141dffc OpcodeDispatcher: Handle VBLENDVPD 2023-02-06 23:04:26 -05:00
Lioncache 94e91565b1 OpcodeDispatcher: Handle VBLENDVPS 2023-02-06 23:04:26 -05:00
Lioncache acbfee55b4 IR: Allow provising register size for VBSL 
Necessary, since this will now be used with both 256-bit and 128-bit
registers, rather than just 128-bit.
 2023-02-06 23:04:26 -05:00
Lioncache a2481d6892 OpcodeDispatcher: Add helper for AVX variable blends 
These will be used by following instruction implementations.
 2023-02-06 23:04:26 -05:00
Ryan Houdek e255f1cdef Merge pull request #2383 from lioncash/blend 
OpcodeDispatcher: Handle VBLENDPD/VPBLENDW
 2023-02-06 18:55:31 -08:00
Ryan Houdek cb3cfed9c2 Merge pull request #2384 from lioncash/sqadd 
ARMEmitter: Handle SVE2 saturating add/subtract category
 2023-02-06 18:55:23 -08:00
Lioncache 2b12a46d2d ARMEmitter: Handle UQSUBR 2023-02-06 21:29:10 -05:00
Lioncache 8f50109501 ARMEmitter: Handle SQSUBR 2023-02-06 21:29:10 -05:00
Lioncache 1d451b8df1 ARMEmitter: Handle USQADD 2023-02-06 21:29:10 -05:00
Lioncache 49772c6826 ARMEmitter: Handle SUQADD 2023-02-06 21:29:10 -05:00
Lioncache 535a2ab2ba ARMEmitter: Handle UQSUB (vectors, predicated) 2023-02-06 21:29:10 -05:00
Lioncache b8b212719f ARMEmitter: Handle SQSUB (vectors, predicated) 2023-02-06 21:29:10 -05:00
Lioncache be593d43ce ARMEmitter: Handle UQADD (vectors, predicated) 2023-02-06 21:29:10 -05:00
Lioncache a89b7c5dbb ARMEmitter: Handle SQADD (vectors, predicated) 2023-02-06 21:29:07 -05:00
Lioncache c682f51811 OpcodeDispatcher: Handle VPBLENDW 2023-02-06 21:23:30 -05:00
Lioncache 2c7562c54c OpcodeDispatcher: Handle VBLENDPD 2023-02-06 21:03:54 -05:00
Lioncache 8f5ec20cb7 OpcodeDispatcher: Add helper for AVX vector blends 2023-02-06 20:38:35 -05:00
Lioncache 79abe2aa64 ARMEmitter: Simplify bitwise shift by immediate (predicated) category 
Centralizes the immediate handling in the encoding helper function.

Lets us move all the asserts there as well.
 2023-02-06 20:03:21 -05:00
Lioncache 9f3857b3b0 ARMEmitter: Simplify saturating extract narrow category 
Centralizes the immediate handling in the encoding function.
 2023-02-06 19:21:42 -05:00
Lioncache 9521638910 ARMEmitter: Simplify bitwise shift right narrow category 
Centralizes the immediate handling in one place, making everything much
shorter.
 2023-02-06 19:21:39 -05:00
Mai 60b76f53cf Merge pull request #2381 from Sonicadvance1/code_data_header 
JIT: Adds a JIT data header and tail.
 2023-02-06 18:07:20 -05:00
Mai 5da90aac46 Merge pull request #2378 from Sonicadvance1/fix_emitter_warnings 
ARMEmitter: Fixes some warnings that cropped up.
 2023-02-06 18:05:56 -05:00
Ryan Houdek ba5ad72ca2 JIT: Adds a JIT data header and tail. 
This will be used to store various bits of data about the code going
forward.

Currently unused but that will change as we move forward.
 2023-02-06 14:06:37 -08:00
Mai c7c47a827a Merge pull request #2377 from Sonicadvance1/code_data_support 
Core: Support Data in JIT buffer header
 2023-02-06 16:54:01 -05:00
Mai 6047ca9fe2 Merge pull request #2376 from Sonicadvance1/minor_flag_opt 
Dispatcher: Minor flags optimization
 2023-02-06 16:45:45 -05:00
Ryan Houdek 37421d36e6 ARMEmitter: Fixes some warnings that cropped up. 2023-02-05 18:06:29 -08:00
Ryan Houdek bd86deb9ba Core: Support Data in JIT buffer header 
Currently unused (The full data gets thrown away after CompileCode is
called), but allows us to separate code and data in what `CompileCode`
returns.

This will allow us put a header on JIT blocks which will fix a long
outstanding bug where RIP isn't always synchronized on block entry, but
since it only needs to synchronize on signal we can rebuild in the
handler. This future task will remove the `86dec_SynchronizeRIPOnAllBlocks`
config option, but the data will also end up being used for more things
in the future.
 2023-02-05 17:55:31 -08:00
Ryan Houdek 2e701fc9e6 Dispatcher: Minor flags optimization 
SelectCC shift wasn't necessary since we just need to ensure the final
result is zero when or'd together.

Also operations calculating SF can just use a BFE instead of a shifts
with a constant. BFE by immediate is more efficiently encoded in our IR.
 2023-02-04 17:50:36 -08:00
Ryan Houdek 5b97e7f1a0 ELFCodeLoader: Adds an option to inject libSegFault 
When used in conjuction with #2345 this is a useful way to enable
libSegFault in applications using application profiles.

Very useful for applications and games that use launcher scripts that
set LD_PRELOAD to nothing prior to launch.

A user was wanting this.
 2023-02-04 11:17:26 -08:00
Lioncache 6522d3d6e4 ARMEmitter: Move 128-bit check into SVE2IntegerMultiplyVectors 
Simplifies the amount of code needed. Also we can remove some
unnecessary namespacing to make these a little faster to grok when
looking at them.
 2023-02-04 05:08:43 -05:00
Lioncache d65fcf7bb8 ARMEmitter: Handle SVE SQRDMULH (vectors) 2023-02-04 05:06:56 -05:00
Lioncache 16e0f628cd ARMEmitter: Handle SVE SQDMULH (vectors) 2023-02-04 05:05:27 -05:00
Lioncache 75bc997ab7 ARMEmitter: Handle RDVL 2023-02-04 01:11:57 -05:00
Lioncache 600e8749d7 ARMEmitter: Handle ADDPL 2023-02-04 01:05:25 -05:00
Lioncache fc3863f444 ARMEmitter: Handle ADDVL 2023-02-04 01:03:24 -05:00
Lioncache 7442ef3a83 ARMEmitter: Handle SVE MSB 2023-02-03 23:14:10 -05:00
Lioncache 3783ad8dd1 ARMEmitter: Handle SVE MAD 2023-02-03 23:13:16 -05:00
Lioncache 65ad916984 ARMEmitter: Handle SVE MLS (vectors) 2023-02-03 23:06:42 -05:00
Lioncache d491ce7125 ARMEmitter: Handle SVE MLA (vectors) 2023-02-03 23:05:21 -05:00
Lioncache 3f6edf7b5a ARMEmitter: Clarify SVEReductionOperation as working on integer ops 2023-02-03 22:01:34 -05:00
Lioncache 5563a51b84 ARMEmitter: Allow 64-bit variants of min/max reduction 
The instructions allow specifying 64-bit element sizes.

With this, we can also completely remove the size checking from the
functions, since the general SVE integer reduction operation already
checks for invalid sizes for us.
 2023-02-03 22:00:56 -05:00
Lioncache dac075b871 ARMEmitter: Move min/max reduction over to generic reduction helper 
Also enforces the use of a VRegister for the destination argument like
the manual.
 2023-02-03 21:45:58 -05:00
Lioncache db8317caf8 ARMEmitter: Handle SVE ANDV (predicated) 2023-02-03 21:31:41 -05:00
Lioncache 3508f7a667 ARMEmitter: Handle SVE EORV (predicated) 2023-02-03 21:30:48 -05:00
Lioncache 02861f41eb ARMEmitter: Handle SVE ORV (predicated) 2023-02-03 21:26:06 -05:00
Lioncache 51c9f70904 ARMEmitter: Handle SVE UADDV (predicated) 2023-02-03 21:05:00 -05:00
Lioncache 4f9530cec3 ARMEmitter: Handle SVE SADDV (predicated) 2023-02-03 21:02:45 -05:00
Lioncache ecd711e691 ARMEmitter: Handle SVE UDIVR (predicated) 2023-02-03 20:49:57 -05:00
Lioncache 870115dd5d ARMEmitter: Handle SVE SDIVR (predicated) 2023-02-03 20:49:57 -05:00