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ARMEmitter: Handle SVE ANDV (predicated)

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Lioncache committed 2023-02-03 21:31:41 -05:00
1 parent 3508f7a667
commit db8317caf8
2 files changed
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External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl
Vendored
+4
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@@ -782,6 +782,10 @@ public:
constexpr uint32_t Op = 0b0000'0100'0001'1000'0010'0000'0000'0000;
SVEReductionOperation(Op, 0b01, size, vd, pg, zn);
}
void andv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
constexpr uint32_t Op = 0b0000'0100'0001'1000'0010'0000'0000'0000;
SVEReductionOperation(Op, 0b10, size, vd, pg, zn);
}
// SVE Bitwise Shift - Predicated
// SVE bitwise shift by immediate (predicated)
External/FEXCore/unittests/Emitter/SVE_Tests.cpp
Vendored
+5
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@@ -644,6 +644,11 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE bitwise logical reduction
TEST_SINGLE(eorv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z29), "eorv h30, p7, z29.h");
TEST_SINGLE(eorv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z29), "eorv s30, p7, z29.s");
TEST_SINGLE(eorv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z29), "eorv d30, p7, z29.d");
TEST_SINGLE(andv(SubRegSize::i8Bit, VReg::v30, PReg::p7, ZReg::z29), "andv b30, p7, z29.b");
TEST_SINGLE(andv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z29), "andv h30, p7, z29.h");
TEST_SINGLE(andv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z29), "andv s30, p7, z29.s");
TEST_SINGLE(andv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z29), "andv d30, p7, z29.d");
}
TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE bitwise shift by immediate (predicated)") {
TEST_SINGLE(asr(SubRegSize::i8Bit, ZReg::z30, PReg::p6.Merging(), ZReg::z30, 1), "asr z30.b, p6/m, z30.b, #1");