From db8317caf86d482f2feee45bce26d7d7fadfa0d2 Mon Sep 17 00:00:00 2001 From: Lioncache Date: Fri, 3 Feb 2023 21:29:08 -0500 Subject: [PATCH] ARMEmitter: Handle SVE ANDV (predicated) --- .../Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl | 4 ++++ External/FEXCore/unittests/Emitter/SVE_Tests.cpp | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index d39761c6e..5809864c4 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -782,6 +782,10 @@ public: constexpr uint32_t Op = 0b0000'0100'0001'1000'0010'0000'0000'0000; SVEReductionOperation(Op, 0b01, size, vd, pg, zn); } + void andv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) { + constexpr uint32_t Op = 0b0000'0100'0001'1000'0010'0000'0000'0000; + SVEReductionOperation(Op, 0b10, size, vd, pg, zn); + } // SVE Bitwise Shift - Predicated // SVE bitwise shift by immediate (predicated) diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index a428733a1..4d3ad26f5 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -644,6 +644,11 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE bitwise logical reduction TEST_SINGLE(eorv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z29), "eorv h30, p7, z29.h"); TEST_SINGLE(eorv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z29), "eorv s30, p7, z29.s"); TEST_SINGLE(eorv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z29), "eorv d30, p7, z29.d"); + + TEST_SINGLE(andv(SubRegSize::i8Bit, VReg::v30, PReg::p7, ZReg::z29), "andv b30, p7, z29.b"); + TEST_SINGLE(andv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z29), "andv h30, p7, z29.h"); + TEST_SINGLE(andv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z29), "andv s30, p7, z29.s"); + TEST_SINGLE(andv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z29), "andv d30, p7, z29.d"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE bitwise shift by immediate (predicated)") { TEST_SINGLE(asr(SubRegSize::i8Bit, ZReg::z30, PReg::p6.Merging(), ZReg::z30, 1), "asr z30.b, p6/m, z30.b, #1");