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ARMEmitter: Handle ADDPL

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Lioncache committed 2023-02-04 01:05:25 -05:00
1 parent fc3863f444
commit 600e8749d7
2 files changed
+9 -2
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External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl
Vendored
+3
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@@ -1350,6 +1350,9 @@ public:
void addvl(XRegister rd, XRegister rn, int32_t imm) {
SVEStackFrameOperation(0b00, rd, rn, imm);
}
void addpl(XRegister rd, XRegister rn, int32_t imm) {
SVEStackFrameOperation(0b01, rd, rn, imm);
}
// Streaming SVE stack frame adjustment
// XXX:
External/FEXCore/unittests/Emitter/SVE_Tests.cpp
Vendored
+6 -2
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@@ -890,8 +890,12 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE Index Generation") {
}
TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE stack frame adjustment") {
TEST_SINGLE(addvl(XReg::rsp, XReg::rsp, -32), "addvl sp, sp, #-32");
TEST_SINGLE(addvl(XReg::rsp, XReg::rsp, 31), "addvl sp, sp, #31");
TEST_SINGLE(addvl(XReg::x30, XReg::x29, 15), "addvl x30, x29, #15");
TEST_SINGLE(addvl(XReg::rsp, XReg::rsp, 31), "addvl sp, sp, #31");
TEST_SINGLE(addvl(XReg::x30, XReg::x29, 15), "addvl x30, x29, #15");
TEST_SINGLE(addpl(XReg::rsp, XReg::rsp, -32), "addpl sp, sp, #-32");
TEST_SINGLE(addpl(XReg::rsp, XReg::rsp, 31), "addpl sp, sp, #31");
TEST_SINGLE(addpl(XReg::x30, XReg::x29, 15), "addpl x30, x29, #15");
}
TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: Streaming SVE stack frame adjustment") {
// TODO: Implement in emitter.