Lioncache
6522d3d6e4
ARMEmitter: Move 128-bit check into SVE2IntegerMultiplyVectors
...
Simplifies the amount of code needed. Also we can remove some
unnecessary namespacing to make these a little faster to grok when
looking at them.
2023-02-04 05:08:43 -05:00
Lioncache
d65fcf7bb8
ARMEmitter: Handle SVE SQRDMULH (vectors)
2023-02-04 05:06:56 -05:00
Lioncache
16e0f628cd
ARMEmitter: Handle SVE SQDMULH (vectors)
2023-02-04 05:05:27 -05:00
Lioncache
75bc997ab7
ARMEmitter: Handle RDVL
2023-02-04 01:11:57 -05:00
Lioncache
600e8749d7
ARMEmitter: Handle ADDPL
2023-02-04 01:05:25 -05:00
Lioncache
fc3863f444
ARMEmitter: Handle ADDVL
2023-02-04 01:03:24 -05:00
Lioncache
7442ef3a83
ARMEmitter: Handle SVE MSB
2023-02-03 23:14:10 -05:00
Lioncache
3783ad8dd1
ARMEmitter: Handle SVE MAD
2023-02-03 23:13:16 -05:00
Lioncache
65ad916984
ARMEmitter: Handle SVE MLS (vectors)
2023-02-03 23:06:42 -05:00
Lioncache
d491ce7125
ARMEmitter: Handle SVE MLA (vectors)
2023-02-03 23:05:21 -05:00
Lioncache
3f6edf7b5a
ARMEmitter: Clarify SVEReductionOperation as working on integer ops
2023-02-03 22:01:34 -05:00
Lioncache
5563a51b84
ARMEmitter: Allow 64-bit variants of min/max reduction
...
The instructions allow specifying 64-bit element sizes.
With this, we can also completely remove the size checking from the
functions, since the general SVE integer reduction operation already
checks for invalid sizes for us.
2023-02-03 22:00:56 -05:00
Lioncache
dac075b871
ARMEmitter: Move min/max reduction over to generic reduction helper
...
Also enforces the use of a VRegister for the destination argument like
the manual.
2023-02-03 21:45:58 -05:00
Lioncache
db8317caf8
ARMEmitter: Handle SVE ANDV (predicated)
2023-02-03 21:31:41 -05:00
Lioncache
3508f7a667
ARMEmitter: Handle SVE EORV (predicated)
2023-02-03 21:30:48 -05:00
Lioncache
02861f41eb
ARMEmitter: Handle SVE ORV (predicated)
2023-02-03 21:26:06 -05:00
Lioncache
51c9f70904
ARMEmitter: Handle SVE UADDV (predicated)
2023-02-03 21:05:00 -05:00
Lioncache
4f9530cec3
ARMEmitter: Handle SVE SADDV (predicated)
2023-02-03 21:02:45 -05:00
Lioncache
ecd711e691
ARMEmitter: Handle SVE UDIVR (predicated)
2023-02-03 20:49:57 -05:00
Lioncache
870115dd5d
ARMEmitter: Handle SVE SDIVR (predicated)
2023-02-03 20:49:57 -05:00
Lioncache
848e5561ce
ARMEmitter: Handle SVE UDIV (predicated)
2023-02-03 20:49:57 -05:00
Lioncache
db8a9bb5cf
ARMEmitter: Handle SVE SDIV (predicated)
2023-02-03 20:49:54 -05:00
Lioncache
f8a1c43c06
ARMEmitter: Handle SVE UMULH (predicated)
2023-02-03 20:27:48 -05:00
Lioncache
3a98190119
ARMEmitter: Handle SVE SMULH (predicated)
2023-02-03 20:25:44 -05:00
Lioncache
19ad19193e
ARMEmitter: Handle SVE MUL (predicated)
2023-02-03 20:16:24 -05:00
Ryan Houdek
9d33bba1c8
Merge pull request #2366 from lioncash/addsub
...
ARMEmitter: Handle integer add/subtract vectors (predicated) instruction class
2023-02-03 10:31:56 -08:00
Lioncache
8c09356bd7
ARMEmitter: Handle SETF16
2023-02-02 23:27:40 -05:00
Lioncache
50bcc1b96f
ARMEmitter: Handle SETF8
2023-02-02 23:26:07 -05:00
Lioncache
36831ebc37
ARMEmitter: Handle RMIF
2023-02-02 23:18:22 -05:00
Lioncache
44f5d788c8
ARMEmitter: Handle SUBR (vector, predicated)
2023-02-02 21:44:44 -05:00
Lioncache
a42ae7d385
ARMEmitter: Handle SUB (vector, predicated)
2023-02-02 21:42:57 -05:00
Lioncache
5cf9bb2613
ARMEmitter: Handle ADD (vector, predicated)
2023-02-02 21:41:12 -05:00
Lioncache
4001dc1219
ARMEmitter: Handle SVE FMINV
2023-02-02 20:42:54 -05:00
Lioncache
f77de7f283
ARMEmitter: Handle SVE FMAXV
2023-02-02 20:41:10 -05:00
Lioncache
ac9f9d291b
ARMEmitter: Handle SVE FMINNMV
2023-02-02 20:35:43 -05:00
Lioncache
25f97065df
ARMEmitter: Handle SVE FMAXNMV
2023-02-02 20:33:37 -05:00
Lioncache
6fcbce0c52
ARMEmitter: Handle SVE FADDV
2023-02-02 20:28:11 -05:00
Lioncache
4c647a2e02
ARMEmitter: Handle NMATCH
2023-02-02 15:40:34 -05:00
Lioncache
d0f00d53d3
ARMEmitter: Handle MATCH
2023-02-02 15:40:34 -05:00
Lioncache
6174437667
ARMEmitter: Handle SVE FCMLA
2023-02-02 15:40:34 -05:00
Lioncache
9c762861f6
ARMEmitter: Handle SVE FCADD
2023-02-02 15:40:34 -05:00
Lioncache
448785e693
ARMEmitter: Handle HISTSEG
2023-02-02 15:40:26 -05:00
Lioncache
f8c68acc09
ARMEmitter: Handle HISTCNT
2023-02-02 15:40:18 -05:00
Lioncache
2e232ac3dd
OpcodeDispatcher: Handle VBLENDPS
2023-02-01 20:36:23 -05:00
Lioncache
88ff0db12a
OpcodeDispatcher: Handle VPBLENDD
2023-02-01 20:36:15 -05:00
Ryan Houdek
fa1193f14c
Merge pull request #2344 from Sonicadvance1/siginfo_32
...
FEXCore: Fixup 32-bit signal handling
2023-01-31 20:26:36 -08:00
Lioncache
4177d5c185
Arm64/VectorOps: Clamp shift amount to esize-1 for VSShr
...
Makes the behavior consistent with the x86 JIT.
We need to treat values larger than 31 as if they were 31 bit shifts in
order to handle sign-extending behavior properly.
2023-01-31 22:53:51 -05:00
Lioncache
d5316c8c7e
OpcodeDispatcher: Handle VPSRAVD
2023-01-31 17:31:24 -05:00
Lioncache
cc65f3e788
Arm64/VectorOps: Implement VSShr
...
This will be used for implementing VPSRAVD
2023-01-31 17:31:20 -05:00
Mai
787b6895e8
Merge pull request #2337 from Sonicadvance1/optimize_frontend
...
Frontend: Various optimizations
2023-01-31 14:46:11 +00:00
Lioncache