this will eliminate an annoying special case in post-RA opts.
No difference proven at 95.0% confidence
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
now that the algebraic/folding opts are gone, we can do this in one pass for a
2.5% speedup:
N Min Max Median Avg Stddev
x 50 0.44474704 0.46750433 0.45455258 0.45446569 0.0044727894
+ 50 0.43149892 0.45173984 0.44252267 0.44295575 0.0045621814
Difference at 95.0% confidence
-0.0115099 +/- 0.00179263
-2.53263% +/- 0.394447%
(Student's t, pooled s = 0.00451771)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
No longer needed.
The total difference from the beginning of this series (all the prep work to
make this change possible) plus this commit is a modest 0.4% win.
N Min Max Median Avg Stddev
x 100 0.4472467 0.46646308 0.45708424 0.45713057 0.0040838243
+ 100 0.44707586 0.46581227 0.45479448 0.45509309 0.0037548573
Difference at 95.0% confidence
-0.00203748 +/- 0.00108734
-0.445711% +/- 0.237862%
(Student's t, pooled s = 0.00392279)
...in addition to a net deletion of 144 lines of code.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
these can't work due to architectural limitations. they could be ported to
post-RA passes, I think, but having them here now is not helping anything and
they're in the way.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
combined results on node from this and the previous commit:
N Min Max Median Avg Stddev
x 50 0.44433582 0.46988457 0.45344824 0.45320041 0.0043288623
+ 50 0.4385365 0.46615359 0.45026179 0.44996216 0.0045742233
Difference at 95.0% confidence
-0.00323825 +/- 0.00176704
-0.71453% +/- 0.389903%
(Student's t, pooled s = 0.00445323)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
as a simple post-RA peephole. much much easier to do post-RA than pre-RA.
This isn't a post-RA /pass/ in the traditional sense... it's done while
assigning registers to coalesce the passes over the IR, since we pay per-pass
and we can merge the walks over the IR.
Closes: #4480
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
lots of instructions only exist for RA, so RA can garbage collect them before
post-RA passes (including the JIT) deals with them. this simplifies our life
now, and makes post-RA passes a LOT simpler for little cost.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Remove blows up because of use tracking, but we can do a much simpler version
for post-RA and elide lots of checks from trying to make Remove more general.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Now that we can just set registers directly, we can simplify RA a lot. All the
Map/Unmap nonsense - it all goes away. We just assign registers as we go and
everything clicks into place naturally.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This sideband is now unused, registers are encoded directly in the IR. So we can
garbage collect all this code for quite some savings.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Beyond the actual registers allocated, there are two pieces of sideband data we
store in the RAData object:
* # of spill slots (explicitly)
* whether RA has run (implicitly by the existence of RAData)
We want to get rid of RAData, so we'll move these to the header.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
this will let us encode registers directly inside OrderedNodeWrapper, rather
than pointers to OrderedNode *. that will let us speed up RA & onwards.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
There's no reasonable way to keep this around without adding significant
complexity to RA. This series prefers to drop complexity from RA, lessening the
need for validation in the first place.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
nothing else does this, and it complicates upcoming refactor to move away from
IR builder helpers doing IR dereferencing.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
FEAT_ECV added a new synchronizing cycle counter instruction that
restrict speculation across the cycle counter access. Because it
restricts speculation, it effectively acts like an isb and load dsb.
Luckily for us, this actually matches behaviour for what rdtscp does, so
we can take advantage of it if the host supports FEAT_ECV.
Alyssa Rosenzweig