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IR: extend the IR header with RA info
Beyond the actual registers allocated, there are two pieces of sideband data we store in the RAData object: * # of spill slots (explicitly) * whether RA has run (implicitly by the existence of RAData) We want to get rid of RAData, so we'll move these to the header. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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@@ -959,7 +959,7 @@ void ContextImpl::AddThunkTrampolineIRHandler(uintptr_t Entrypoint, uintptr_t Gu
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auto Result = AddCustomIREntrypoint(
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Entrypoint,
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[this, GuestThunkEntrypoint](uintptr_t Entrypoint, FEXCore::IR::IREmitter* emit) {
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auto IRHeader = emit->_IRHeader(emit->Invalid(), Entrypoint, 0, 0);
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auto IRHeader = emit->_IRHeader(emit->Invalid(), Entrypoint, 0, 0, 0, 0);
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auto Block = emit->CreateCodeNode();
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IRHeader.first->Blocks = emit->WrapNode(Block);
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emit->SetCurrentCodeBlock(Block);
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@@ -3933,7 +3933,7 @@ void OpDispatchBuilder::CreateJumpBlocks(const fextl::vector<FEXCore::Frontend::
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void OpDispatchBuilder::BeginFunction(uint64_t RIP, const fextl::vector<FEXCore::Frontend::Decoder::DecodedBlocks>* Blocks, uint32_t NumInstructions) {
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Entry = RIP;
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auto IRHeader = _IRHeader(InvalidNode, RIP, 0, NumInstructions);
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auto IRHeader = _IRHeader(InvalidNode, RIP, 0, NumInstructions, 0, 0);
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CreateJumpBlocks(Blocks);
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auto Block = GetNewJumpBlock(RIP);
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@@ -169,7 +169,7 @@
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"SwitchGen": false,
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"JITDispatchOverride": "NoOp"
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},
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"IRHeader SSA:$Blocks, u64:$OriginalRIP, u32:$BlockCount, u32:$NumHostInstructions, i1:$HasX87{false}, i1:$ReadsParity{false}": {
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"IRHeader SSA:$Blocks, u64:$OriginalRIP, u32:$BlockCount, u32:$NumHostInstructions, u32:$SpillSlots, i1:$PostRA{false}, i1:$HasX87{false}, i1:$ReadsParity{false}": {
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"SwitchGen": false,
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"JITDispatchOverride": "NoOp"
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},
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@@ -234,6 +234,16 @@ public:
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return GetOp<IROp_IRHeader>(GetHeaderNode());
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}
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[[nodiscard]]
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unsigned PostRA() const {
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return GetHeader()->PostRA;
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}
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[[nodiscard]]
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unsigned SpillSlots() const {
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return GetHeader()->SpillSlots;
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}
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template<typename T>
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[[nodiscard]]
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T* GetOp(Ref Node) const {
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