From a01e29ac99c5106366031f76100b617f7dfe1f05 Mon Sep 17 00:00:00 2001
From: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Date: Fri, 16 May 2025 14:33:27 -0400
Subject: [PATCH] IR: extend the IR header with RA info

Beyond the actual registers allocated, there are two pieces of sideband data we
store in the RAData object:

* # of spill slots (explicitly)
* whether RA has run (implicitly by the existence of RAData)

We want to get rid of RAData, so we'll move these to the header.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
---
 FEXCore/Source/Interface/Core/Core.cpp             |  2 +-
 FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp |  2 +-
 FEXCore/Source/Interface/IR/IR.json                |  2 +-
 FEXCore/Source/Interface/IR/IntrusiveIRList.h      | 10 ++++++++++
 4 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/FEXCore/Source/Interface/Core/Core.cpp b/FEXCore/Source/Interface/Core/Core.cpp
index eb1b38fe7..4e090acd7 100644
--- a/FEXCore/Source/Interface/Core/Core.cpp
+++ b/FEXCore/Source/Interface/Core/Core.cpp
@@ -959,7 +959,7 @@ void ContextImpl::AddThunkTrampolineIRHandler(uintptr_t Entrypoint, uintptr_t Gu
   auto Result = AddCustomIREntrypoint(
     Entrypoint,
     [this, GuestThunkEntrypoint](uintptr_t Entrypoint, FEXCore::IR::IREmitter* emit) {
-    auto IRHeader = emit->_IRHeader(emit->Invalid(), Entrypoint, 0, 0);
+    auto IRHeader = emit->_IRHeader(emit->Invalid(), Entrypoint, 0, 0, 0, 0);
     auto Block = emit->CreateCodeNode();
     IRHeader.first->Blocks = emit->WrapNode(Block);
     emit->SetCurrentCodeBlock(Block);
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 7164d6632..a08ed2b00 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -3933,7 +3933,7 @@ void OpDispatchBuilder::CreateJumpBlocks(const fextl::vector<FEXCore::Frontend::
 
 void OpDispatchBuilder::BeginFunction(uint64_t RIP, const fextl::vector<FEXCore::Frontend::Decoder::DecodedBlocks>* Blocks, uint32_t NumInstructions) {
   Entry = RIP;
-  auto IRHeader = _IRHeader(InvalidNode, RIP, 0, NumInstructions);
+  auto IRHeader = _IRHeader(InvalidNode, RIP, 0, NumInstructions, 0, 0);
   CreateJumpBlocks(Blocks);
 
   auto Block = GetNewJumpBlock(RIP);
diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
index 5aec513df..6b8c0bbcc 100644
--- a/FEXCore/Source/Interface/IR/IR.json
+++ b/FEXCore/Source/Interface/IR/IR.json
@@ -169,7 +169,7 @@
         "SwitchGen": false,
         "JITDispatchOverride": "NoOp"
       },
-      "IRHeader SSA:$Blocks, u64:$OriginalRIP, u32:$BlockCount, u32:$NumHostInstructions, i1:$HasX87{false}, i1:$ReadsParity{false}": {
+      "IRHeader SSA:$Blocks, u64:$OriginalRIP, u32:$BlockCount, u32:$NumHostInstructions, u32:$SpillSlots, i1:$PostRA{false}, i1:$HasX87{false}, i1:$ReadsParity{false}": {
         "SwitchGen": false,
         "JITDispatchOverride": "NoOp"
       },
diff --git a/FEXCore/Source/Interface/IR/IntrusiveIRList.h b/FEXCore/Source/Interface/IR/IntrusiveIRList.h
index 0cc49e6fe..3158d8c32 100644
--- a/FEXCore/Source/Interface/IR/IntrusiveIRList.h
+++ b/FEXCore/Source/Interface/IR/IntrusiveIRList.h
@@ -234,6 +234,16 @@ public:
     return GetOp<IROp_IRHeader>(GetHeaderNode());
   }
 
+  [[nodiscard]]
+  unsigned PostRA() const {
+    return GetHeader()->PostRA;
+  }
+
+  [[nodiscard]]
+  unsigned SpillSlots() const {
+    return GetHeader()->SpillSlots;
+  }
+
   template<typename T>
   [[nodiscard]]
   T* GetOp(Ref Node) const {