Alyssa Rosenzweig c4f00a05df IR: add space for registers right in OrderedNode * ...

This again follows the same idea of eliminating the RAData sideband.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2025-05-19 13:42:59 -04:00

..

Passes

IR: drop FillRegister original source

2025-05-16 15:18:06 -04:00

AOTIR.cpp

Fixes some instances of auto usage with unintentional copy

2025-02-12 23:51:57 -08:00

AOTIR.h

AOTIR: Move debugdata structure to internal header

2024-09-06 10:19:45 -07:00

IntrusiveIRList.h

ThreadPoolAllocator: Rename FixedSizePoolAllocation to PoolBufferWithTimedRetirement

2025-05-14 13:29:44 +02:00

IR.h

IR: add space for registers right in OrderedNode *

2025-05-19 13:42:59 -04:00

IR.json

IR: drop FillRegister original source

2025-05-16 15:18:06 -04:00

IRDumper.cpp

IR/IRDumper: static analysis warnings

2025-03-27 04:26:40 -07:00

IREmitter.cpp

Revert "Enable RA of SVE Predicate Registers"

2025-01-29 11:56:19 +01:00

IREmitter.h

IR/IREmitter: static analysis warnings

2025-03-27 04:26:40 -07:00

Passes.h

IR: drop RA validation

2025-05-16 15:18:06 -04:00

PassManager.cpp

IR: drop RA validation

2025-05-16 15:18:06 -04:00

PassManager.h

Various: More static analysis warnings cleanup

2025-03-12 17:27:41 -07:00

RegisterAllocationData.h

AOTIR: Remove obsolete fields from serialized data

2024-05-21 17:54:28 +02:00